1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #include "llvm/CodeGen/LiveVariables.h"
30 #include "llvm/CodeGen/MachineInstr.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetRegisterInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/ADT/DepthFirstIterator.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/Config/alloca.h"
42 char LiveVariables::ID = 0;
43 static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
45 void LiveVariables::VarInfo::dump() const {
46 cerr << " Alive in blocks: ";
47 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i)
48 if (AliveBlocks[i]) cerr << i << ", ";
49 cerr << " Used in blocks: ";
50 for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i)
51 if (UsedBlocks[i]) cerr << i << ", ";
52 cerr << "\n Killed by:";
54 cerr << " No instructions.\n";
56 for (unsigned i = 0, e = Kills.size(); i != e; ++i)
57 cerr << "\n #" << i << ": " << *Kills[i];
62 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
63 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
64 assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
65 "getVarInfo: not a virtual register!");
66 RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
67 if (RegIdx >= VirtRegInfo.size()) {
68 if (RegIdx >= 2*VirtRegInfo.size())
69 VirtRegInfo.resize(RegIdx*2);
71 VirtRegInfo.resize(2*VirtRegInfo.size());
73 VarInfo &VI = VirtRegInfo[RegIdx];
74 VI.AliveBlocks.resize(MF->getNumBlockIDs());
75 VI.UsedBlocks.resize(MF->getNumBlockIDs());
79 /// KillsRegister - Returns true if the machine instruction kills the specified
81 bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const {
82 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
83 const MachineOperand &MO = MI->getOperand(i);
84 if (MO.isRegister() && MO.isKill()) {
85 unsigned MOReg = MO.getReg();
87 (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
88 TargetRegisterInfo::isPhysicalRegister(Reg) &&
89 RegInfo->isSubRegister(MOReg, Reg)))
96 /// RegisterDefIsDead - Returns true if the register is dead in this machine
98 bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const {
99 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
100 const MachineOperand &MO = MI->getOperand(i);
101 if (MO.isRegister() && MO.isDead()) {
102 unsigned MOReg = MO.getReg();
103 if ((MOReg == Reg) ||
104 (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
105 TargetRegisterInfo::isPhysicalRegister(Reg) &&
106 RegInfo->isSubRegister(MOReg, Reg)))
113 /// ModifiesRegister - Returns true if the machine instruction modifies the
115 bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const {
116 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
117 const MachineOperand &MO = MI->getOperand(i);
118 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
124 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
125 MachineBasicBlock *DefBlock,
126 MachineBasicBlock *MBB,
127 std::vector<MachineBasicBlock*> &WorkList) {
128 unsigned BBNum = MBB->getNumber();
130 // Check to see if this basic block is one of the killing blocks. If so,
132 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
133 if (VRInfo.Kills[i]->getParent() == MBB) {
134 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
138 if (MBB == DefBlock) return; // Terminate recursion
140 if (VRInfo.AliveBlocks[BBNum])
141 return; // We already know the block is live
143 // Mark the variable known alive in this bb
144 VRInfo.AliveBlocks[BBNum] = true;
146 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
147 E = MBB->pred_rend(); PI != E; ++PI)
148 WorkList.push_back(*PI);
151 void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
152 MachineBasicBlock *DefBlock,
153 MachineBasicBlock *MBB) {
154 std::vector<MachineBasicBlock*> WorkList;
155 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
157 while (!WorkList.empty()) {
158 MachineBasicBlock *Pred = WorkList.back();
160 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
165 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
167 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
168 assert(MRI.getVRegDef(reg) && "Register use before def!");
170 unsigned BBNum = MBB->getNumber();
172 VarInfo& VRInfo = getVarInfo(reg);
173 VRInfo.UsedBlocks[BBNum] = true;
176 // Check to see if this basic block is already a kill block.
177 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
178 // Yes, this register is killed in this basic block already. Increase the
179 // live range by updating the kill instruction.
180 VRInfo.Kills.back() = MI;
185 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
186 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
189 assert(MBB != MRI.getVRegDef(reg)->getParent() &&
190 "Should have kill for defblock!");
192 // Add a new kill entry for this basic block. If this virtual register is
193 // already marked as alive in this basic block, that means it is alive in at
194 // least one of the successor blocks, it's not a kill.
195 if (!VRInfo.AliveBlocks[BBNum])
196 VRInfo.Kills.push_back(MI);
198 // Update all dominating blocks to mark them as "known live".
199 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
200 E = MBB->pred_end(); PI != E; ++PI)
201 MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI);
204 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
205 // Turn previous partial def's into read/mod/write.
206 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) {
207 MachineInstr *Def = PhysRegPartDef[Reg][i];
208 // First one is just a def. This means the use is reading some undef bits.
210 Def->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
211 true/*IsImp*/,true/*IsKill*/));
212 Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/));
215 PhysRegPartDef[Reg].clear();
217 // There was an earlier def of a super-register. Add implicit def to that MI.
220 // Add implicit def to A.
221 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] &&
223 MachineInstr *Def = PhysRegInfo[Reg];
224 if (!Def->findRegisterDefOperand(Reg))
225 Def->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
229 // There is a now a proper use, forget about the last partial use.
230 PhysRegPartUse[Reg] = NULL;
231 PhysRegInfo[Reg] = MI;
232 PhysRegUsed[Reg] = true;
234 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
235 unsigned SubReg = *SubRegs; ++SubRegs) {
236 PhysRegInfo[SubReg] = MI;
237 PhysRegUsed[SubReg] = true;
240 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
241 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
242 // Remember the partial use of this superreg if it was previously defined.
243 bool HasPrevDef = PhysRegInfo[SuperReg] != NULL;
245 for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg);
246 unsigned SSReg = *SSRegs; ++SSRegs) {
247 if (PhysRegInfo[SSReg] != NULL) {
254 PhysRegInfo[SuperReg] = MI;
255 PhysRegPartUse[SuperReg] = MI;
260 /// addRegisterKills - For all of a register's sub-registers that are killed in
261 /// other instructions (?), indicate that they are killed in this machine
262 /// instruction by marking the operand as "killed". (If the machine operand
263 /// isn't found, add it first.)
264 void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI,
265 SmallSet<unsigned, 4> &SubKills) {
266 if (SubKills.count(Reg) == 0) {
267 MI->addRegisterKilled(Reg, RegInfo, true);
271 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
272 unsigned SubReg = *SubRegs; ++SubRegs)
273 addRegisterKills(SubReg, MI, SubKills);
276 /// HandlePhysRegKill - The recursive version of HandlePhysRegKill. Returns true
279 /// - The register has no sub-registers and the machine instruction is the
280 /// last def/use of the register, or
281 /// - The register has sub-registers and none of them are killed elsewhere.
283 bool LiveVariables::HandlePhysRegKill(unsigned Reg, const MachineInstr *RefMI,
284 SmallSet<unsigned, 4> &SubKills) {
285 const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
287 for (; unsigned SubReg = *SubRegs; ++SubRegs) {
288 const MachineInstr *LastRef = PhysRegInfo[SubReg];
290 if (LastRef != RefMI ||
291 !HandlePhysRegKill(SubReg, RefMI, SubKills))
292 SubKills.insert(SubReg);
296 // No sub-registers, just check if reg is killed by RefMI.
297 if (PhysRegInfo[Reg] == RefMI)
299 } else if (SubKills.empty()) {
300 // None of the sub-registers are killed elsewhere.
307 /// HandlePhysRegKill - Calls the recursive version of HandlePhysRegKill. (See
308 /// above for details.)
309 bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) {
310 SmallSet<unsigned, 4> SubKills;
312 if (HandlePhysRegKill(Reg, RefMI, SubKills)) {
313 // This machine instruction kills this register.
314 RefMI->addRegisterKilled(Reg, RegInfo, true);
318 // Some sub-registers are killed by another machine instruction.
319 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg);
320 unsigned SubReg = *SubRegs; ++SubRegs)
321 addRegisterKills(SubReg, RefMI, SubKills);
326 void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
327 // Does this kill a previous version of this register?
328 if (MachineInstr *LastRef = PhysRegInfo[Reg]) {
329 if (PhysRegUsed[Reg]) {
330 if (!HandlePhysRegKill(Reg, LastRef)) {
331 if (PhysRegPartUse[Reg])
332 PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
334 } else if (PhysRegPartUse[Reg]) {
335 // Add implicit use / kill to last partial use.
336 PhysRegPartUse[Reg]->addRegisterKilled(Reg, RegInfo, true);
337 } else if (LastRef != MI) {
338 // Defined, but not used. However, watch out for cases where a super-reg
339 // is also defined on the same MI.
340 LastRef->addRegisterDead(Reg, RegInfo);
344 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
345 unsigned SubReg = *SubRegs; ++SubRegs) {
346 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) {
347 if (PhysRegUsed[SubReg]) {
348 if (!HandlePhysRegKill(SubReg, LastRef)) {
349 if (PhysRegPartUse[SubReg])
350 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
352 } else if (PhysRegPartUse[SubReg]) {
353 // Add implicit use / kill to last use of a sub-register.
354 PhysRegPartUse[SubReg]->addRegisterKilled(SubReg, RegInfo, true);
355 } else if (LastRef != MI) {
356 // This must be a def of the subreg on the same MI.
357 LastRef->addRegisterDead(SubReg, RegInfo);
363 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg);
364 unsigned SuperReg = *SuperRegs; ++SuperRegs) {
365 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) {
366 // The larger register is previously defined. Now a smaller part is
367 // being re-defined. Treat it as read/mod/write.
369 // AX = EAX<imp-use,kill>, EAX<imp-def>
370 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
371 true/*IsImp*/,true/*IsKill*/));
372 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
374 PhysRegInfo[SuperReg] = MI;
375 PhysRegUsed[SuperReg] = false;
376 PhysRegPartUse[SuperReg] = NULL;
378 // Remember this partial def.
379 PhysRegPartDef[SuperReg].push_back(MI);
383 PhysRegInfo[Reg] = MI;
384 PhysRegUsed[Reg] = false;
385 PhysRegPartDef[Reg].clear();
386 PhysRegPartUse[Reg] = NULL;
388 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg);
389 unsigned SubReg = *SubRegs; ++SubRegs) {
390 PhysRegInfo[SubReg] = MI;
391 PhysRegUsed[SubReg] = false;
392 PhysRegPartDef[SubReg].clear();
393 PhysRegPartUse[SubReg] = NULL;
398 bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
400 RegInfo = MF->getTarget().getRegisterInfo();
401 MachineRegisterInfo& MRI = mf.getRegInfo();
402 assert(RegInfo && "Target doesn't have register information?");
404 ReservedRegisters = RegInfo->getReservedRegs(mf);
406 unsigned NumRegs = RegInfo->getNumRegs();
407 PhysRegInfo = new MachineInstr*[NumRegs];
408 PhysRegUsed = new bool[NumRegs];
409 PhysRegPartUse = new MachineInstr*[NumRegs];
410 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs];
411 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
412 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
413 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
414 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
416 /// Get some space for a respectable number of registers...
417 VirtRegInfo.resize(64);
421 // Calculate live variable information in depth first order on the CFG of the
422 // function. This guarantees that we will see the definition of a virtual
423 // register before its uses due to dominance properties of SSA (except for PHI
424 // nodes, which are treated as a special case).
426 MachineBasicBlock *Entry = MF->begin();
427 SmallPtrSet<MachineBasicBlock*,16> Visited;
428 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
429 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
431 MachineBasicBlock *MBB = *DFI;
433 // Mark live-in registers as live-in.
434 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
435 EE = MBB->livein_end(); II != EE; ++II) {
436 assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
437 "Cannot have a live-in virtual register!");
438 HandlePhysRegDef(*II, 0);
441 // Loop over all of the instructions, processing them.
442 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
444 MachineInstr *MI = I;
446 // Process all of the operands of the instruction...
447 unsigned NumOperandsToProcess = MI->getNumOperands();
449 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
450 // of the uses. They will be handled in other basic blocks.
451 if (MI->getOpcode() == TargetInstrInfo::PHI)
452 NumOperandsToProcess = 1;
454 // Process all uses...
455 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
456 const MachineOperand &MO = MI->getOperand(i);
458 if (MO.isRegister() && MO.isUse() && MO.getReg()) {
459 unsigned MOReg = MO.getReg();
461 if (TargetRegisterInfo::isVirtualRegister(MOReg))
462 HandleVirtRegUse(MOReg, MBB, MI);
463 else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
464 !ReservedRegisters[MOReg])
465 HandlePhysRegUse(MOReg, MI);
469 // Process all defs...
470 for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
471 const MachineOperand &MO = MI->getOperand(i);
473 if (MO.isRegister() && MO.isDef() && MO.getReg()) {
474 unsigned MOReg = MO.getReg();
476 if (TargetRegisterInfo::isVirtualRegister(MOReg)) {
477 VarInfo &VRInfo = getVarInfo(MOReg);
479 if (VRInfo.AliveBlocks.none())
480 // If vr is not alive in any block, then defaults to dead.
481 VRInfo.Kills.push_back(MI);
482 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
483 !ReservedRegisters[MOReg]) {
484 HandlePhysRegDef(MOReg, MI);
490 // Handle any virtual assignments from PHI nodes which might be at the
491 // bottom of this basic block. We check all of our successor blocks to see
492 // if they have PHI nodes, and if so, we simulate an assignment at the end
493 // of the current block.
494 if (!PHIVarInfo[MBB->getNumber()].empty()) {
495 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
497 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
498 E = VarInfoVec.end(); I != E; ++I)
499 // Mark it alive only in the block we are representing.
500 MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(),
504 // Finally, if the last instruction in the block is a return, make sure to mark
505 // it as using all of the live-out values in the function.
506 if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
507 MachineInstr *Ret = &MBB->back();
509 for (MachineRegisterInfo::liveout_iterator
510 I = MF->getRegInfo().liveout_begin(),
511 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
512 assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
513 "Cannot have a live-in virtual register!");
514 HandlePhysRegUse(*I, Ret);
516 // Add live-out registers as implicit uses.
517 if (Ret->findRegisterUseOperandIdx(*I) == -1)
518 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
522 // Loop over PhysRegInfo, killing any registers that are available at the
523 // end of the basic block. This also resets the PhysRegInfo map.
524 for (unsigned i = 0; i != NumRegs; ++i)
526 HandlePhysRegDef(i, 0);
528 // Clear some states between BB's. These are purely local information.
529 for (unsigned i = 0; i != NumRegs; ++i)
530 PhysRegPartDef[i].clear();
532 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0);
533 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false);
534 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0);
537 // Convert and transfer the dead / killed information we have gathered into
538 // VirtRegInfo onto MI's.
540 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
541 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
542 if (VirtRegInfo[i].Kills[j] ==
543 MRI.getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
545 .Kills[j]->addRegisterDead(i +
546 TargetRegisterInfo::FirstVirtualRegister,
550 .Kills[j]->addRegisterKilled(i +
551 TargetRegisterInfo::FirstVirtualRegister,
554 // Check to make sure there are no unreachable blocks in the MC CFG for the
555 // function. If so, it is due to a bug in the instruction selector or some
556 // other part of the code generator if this happens.
558 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
559 assert(Visited.count(&*i) != 0 && "unreachable basic block found");
562 delete[] PhysRegInfo;
563 delete[] PhysRegUsed;
564 delete[] PhysRegPartUse;
565 delete[] PhysRegPartDef;
571 /// instructionChanged - When the address of an instruction changes, this
572 /// method should be called so that live variables can update its internal
573 /// data structures. This removes the records for OldMI, transfering them to
574 /// the records for NewMI.
575 void LiveVariables::instructionChanged(MachineInstr *OldMI,
576 MachineInstr *NewMI) {
577 // If the instruction defines any virtual registers, update the VarInfo,
578 // kill and dead information for the instruction.
579 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
580 MachineOperand &MO = OldMI->getOperand(i);
581 if (MO.isRegister() && MO.getReg() &&
582 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
583 unsigned Reg = MO.getReg();
584 VarInfo &VI = getVarInfo(Reg);
588 addVirtualRegisterDead(Reg, NewMI);
593 addVirtualRegisterKilled(Reg, NewMI);
595 // If this is a kill of the value, update the VI kills list.
596 if (VI.removeKill(OldMI))
597 VI.Kills.push_back(NewMI); // Yes, there was a kill of it
602 /// removeVirtualRegistersKilled - Remove all killed info for the specified
604 void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
605 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
606 MachineOperand &MO = MI->getOperand(i);
607 if (MO.isRegister() && MO.isKill()) {
609 unsigned Reg = MO.getReg();
610 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
611 bool removed = getVarInfo(Reg).removeKill(MI);
612 assert(removed && "kill not in register's VarInfo?");
618 /// removeVirtualRegistersDead - Remove all of the dead registers for the
619 /// specified instruction from the live variable information.
620 void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) {
621 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
622 MachineOperand &MO = MI->getOperand(i);
623 if (MO.isRegister() && MO.isDead()) {
625 unsigned Reg = MO.getReg();
626 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
627 bool removed = getVarInfo(Reg).removeKill(MI);
628 assert(removed && "kill not in register's VarInfo?");
634 /// analyzePHINodes - Gather information about the PHI nodes in here. In
635 /// particular, we want to map the variable information of a virtual
636 /// register which is used in a PHI node. We map that to the BB the vreg is
639 void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
640 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
642 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
643 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
644 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
645 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
646 .push_back(BBI->getOperand(i).getReg());