1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
13 // The parent register is never changed. Instead, a number of new virtual
14 // registers are created and added to the newRegs vector.
16 //===----------------------------------------------------------------------===//
18 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
19 #define LLVM_CODEGEN_LIVERANGEEDIT_H
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/CodeGen/LiveInterval.h"
29 class MachineLoopInfo;
30 class MachineRegisterInfo;
35 /// Callback methods for LiveRangeEdit owners.
37 virtual void anchor();
39 /// Called immediately before erasing a dead machine instruction.
40 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
42 /// Called when a virtual register is no longer used. Return false to defer
43 /// its deletion from LiveIntervals.
44 virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
46 /// Called before shrinking the live range of a virtual register.
47 virtual void LRE_WillShrinkVirtReg(unsigned) {}
49 /// Called after cloning a virtual register.
50 /// This is used for new registers representing connected components of Old.
51 virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
53 virtual ~Delegate() {}
57 LiveInterval &parent_;
58 SmallVectorImpl<LiveInterval*> &newRegs_;
59 Delegate *const delegate_;
60 const SmallVectorImpl<LiveInterval*> *uselessRegs_;
62 /// firstNew_ - Index of the first register added to newRegs_.
63 const unsigned firstNew_;
65 /// scannedRemattable_ - true when remattable values have been identified.
66 bool scannedRemattable_;
68 /// remattable_ - Values defined by remattable instructions as identified by
69 /// tii.isTriviallyReMaterializable().
70 SmallPtrSet<const VNInfo*,4> remattable_;
72 /// rematted_ - Values that were actually rematted, and so need to have their
73 /// live range trimmed or entirely removed.
74 SmallPtrSet<const VNInfo*,4> rematted_;
76 /// scanRemattable - Identify the parent_ values that may rematerialize.
77 void scanRemattable(LiveIntervals &lis,
78 const TargetInstrInfo &tii,
81 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
82 /// OrigIdx are also available with the same value at UseIdx.
83 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
84 SlotIndex UseIdx, LiveIntervals &lis);
86 /// foldAsLoad - If LI has a single use and a single def that can be folded as
87 /// a load, eliminate the register by folding the def into the use.
88 bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead,
89 MachineRegisterInfo&, LiveIntervals&, const TargetInstrInfo&);
92 /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
93 /// @param parent The register being spilled or split.
94 /// @param newRegs List to receive any new registers created. This needn't be
95 /// empty initially, any existing registers are ignored.
96 /// @param uselessRegs List of registers that can't be used when
97 /// rematerializing values because they are about to be removed.
98 LiveRangeEdit(LiveInterval &parent,
99 SmallVectorImpl<LiveInterval*> &newRegs,
100 Delegate *delegate = 0,
101 const SmallVectorImpl<LiveInterval*> *uselessRegs = 0)
102 : parent_(parent), newRegs_(newRegs),
104 uselessRegs_(uselessRegs),
105 firstNew_(newRegs.size()),
106 scannedRemattable_(false) {}
108 LiveInterval &getParent() const { return parent_; }
109 unsigned getReg() const { return parent_.reg; }
111 /// Iterator for accessing the new registers added by this edit.
112 typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
113 iterator begin() const { return newRegs_.begin()+firstNew_; }
114 iterator end() const { return newRegs_.end(); }
115 unsigned size() const { return newRegs_.size()-firstNew_; }
116 bool empty() const { return size() == 0; }
117 LiveInterval *get(unsigned idx) const { return newRegs_[idx+firstNew_]; }
119 ArrayRef<LiveInterval*> regs() const {
120 return makeArrayRef(newRegs_).slice(firstNew_);
123 /// FIXME: Temporary accessors until we can get rid of
124 /// LiveIntervals::AddIntervalsForSpills
125 SmallVectorImpl<LiveInterval*> *getNewVRegs() { return &newRegs_; }
126 const SmallVectorImpl<LiveInterval*> *getUselessVRegs() {
130 /// createFrom - Create a new virtual register based on OldReg.
131 LiveInterval &createFrom(unsigned OldReg, LiveIntervals&, VirtRegMap&);
133 /// create - Create a new register with the same class and original slot as
135 LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) {
136 return createFrom(getReg(), LIS, VRM);
139 /// anyRematerializable - Return true if any parent values may be
140 /// rematerializable.
141 /// This function must be called before any rematerialization is attempted.
142 bool anyRematerializable(LiveIntervals&, const TargetInstrInfo&,
145 /// checkRematerializable - Manually add VNI to the list of rematerializable
146 /// values if DefMI may be rematerializable.
147 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
148 const TargetInstrInfo&, AliasAnalysis*);
150 /// Remat - Information needed to rematerialize at a specific location.
152 VNInfo *ParentVNI; // parent_'s value at the remat location.
153 MachineInstr *OrigMI; // Instruction defining ParentVNI.
154 explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {}
157 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at
158 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
159 /// When cheapAsAMove is set, only cheap remats are allowed.
160 bool canRematerializeAt(Remat &RM,
165 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
166 /// instruction into MBB before MI. The new instruction is mapped, but
167 /// liveness is not updated.
168 /// Return the SlotIndex of the new instruction.
169 SlotIndex rematerializeAt(MachineBasicBlock &MBB,
170 MachineBasicBlock::iterator MI,
174 const TargetInstrInfo&,
175 const TargetRegisterInfo&,
178 /// markRematerialized - explicitly mark a value as rematerialized after doing
180 void markRematerialized(const VNInfo *ParentVNI) {
181 rematted_.insert(ParentVNI);
184 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
185 bool didRematerialize(const VNInfo *ParentVNI) const {
186 return rematted_.count(ParentVNI);
189 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
190 /// to erase it from LIS.
191 void eraseVirtReg(unsigned Reg, LiveIntervals &LIS);
193 /// eliminateDeadDefs - Try to delete machine instructions that are now dead
194 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed
195 /// and further dead efs to be eliminated.
196 /// RegsBeingSpilled lists registers currently being spilled by the register
197 /// allocator. These registers should not be split into new intervals
198 /// as currently those new intervals are not guaranteed to spill.
199 void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
200 LiveIntervals&, VirtRegMap&,
201 const TargetInstrInfo&,
202 ArrayRef<unsigned> RegsBeingSpilled
203 = ArrayRef<unsigned>());
205 /// calculateRegClassAndHint - Recompute register class and hint for each new
207 void calculateRegClassAndHint(MachineFunction&, LiveIntervals&,
208 const MachineLoopInfo&);