1 //===--- LiveRangeEdit.cpp - Basic tools for editing a register live range --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "regalloc"
15 #include "LiveRangeEdit.h"
16 #include "VirtRegMap.h"
17 #include "llvm/ADT/SetVector.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
26 LiveInterval &LiveRangeEdit::createFrom(unsigned OldReg,
29 MachineRegisterInfo &MRI = VRM.getRegInfo();
30 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
32 VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg));
33 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
34 newRegs_.push_back(&LI);
38 void LiveRangeEdit::checkRematerializable(VNInfo *VNI,
39 const MachineInstr *DefMI,
40 const TargetInstrInfo &tii,
42 assert(DefMI && "Missing instruction");
43 if (tii.isTriviallyReMaterializable(DefMI, aa))
44 remattable_.insert(VNI);
45 scannedRemattable_ = true;
48 void LiveRangeEdit::scanRemattable(LiveIntervals &lis,
49 const TargetInstrInfo &tii,
51 for (LiveInterval::vni_iterator I = parent_.vni_begin(),
52 E = parent_.vni_end(); I != E; ++I) {
56 MachineInstr *DefMI = lis.getInstructionFromIndex(VNI->def);
59 checkRematerializable(VNI, DefMI, tii, aa);
63 bool LiveRangeEdit::anyRematerializable(LiveIntervals &lis,
64 const TargetInstrInfo &tii,
66 if (!scannedRemattable_)
67 scanRemattable(lis, tii, aa);
68 return !remattable_.empty();
71 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
72 /// OrigIdx are also available with the same value at UseIdx.
73 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI,
77 OrigIdx = OrigIdx.getUseIndex();
78 UseIdx = UseIdx.getUseIndex();
79 for (unsigned i = 0, e = OrigMI->getNumOperands(); i != e; ++i) {
80 const MachineOperand &MO = OrigMI->getOperand(i);
81 if (!MO.isReg() || !MO.getReg() || MO.isDef())
83 // Reserved registers are OK.
84 if (MO.isUndef() || !lis.hasInterval(MO.getReg()))
86 // We cannot depend on virtual registers in uselessRegs_.
88 for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui)
89 if ((*uselessRegs_)[ui]->reg == MO.getReg())
92 LiveInterval &li = lis.getInterval(MO.getReg());
93 const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
96 if (OVNI != li.getVNInfoAt(UseIdx))
102 bool LiveRangeEdit::canRematerializeAt(Remat &RM,
105 LiveIntervals &lis) {
106 assert(scannedRemattable_ && "Call anyRematerializable first");
108 // Use scanRemattable info.
109 if (!remattable_.count(RM.ParentVNI))
112 // No defining instruction provided.
115 DefIdx = lis.getInstructionIndex(RM.OrigMI);
117 DefIdx = RM.ParentVNI->def;
118 RM.OrigMI = lis.getInstructionFromIndex(DefIdx);
119 assert(RM.OrigMI && "No defining instruction for remattable value");
122 // If only cheap remats were requested, bail out early.
123 if (cheapAsAMove && !RM.OrigMI->getDesc().isAsCheapAsAMove())
126 // Verify that all used registers are available with the same values.
127 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx, lis))
133 SlotIndex LiveRangeEdit::rematerializeAt(MachineBasicBlock &MBB,
134 MachineBasicBlock::iterator MI,
138 const TargetInstrInfo &tii,
139 const TargetRegisterInfo &tri) {
140 assert(RM.OrigMI && "Invalid remat");
141 tii.reMaterialize(MBB, MI, DestReg, 0, RM.OrigMI, tri);
142 rematted_.insert(RM.ParentVNI);
143 return lis.InsertMachineInstrInMaps(--MI).getDefIndex();
146 void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) {
147 if (delegate_ && delegate_->LRE_CanEraseVirtReg(Reg))
148 LIS.removeInterval(Reg);
151 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
152 LiveIntervals &LIS, VirtRegMap &VRM,
153 const TargetInstrInfo &TII) {
154 SetVector<LiveInterval*,
155 SmallVector<LiveInterval*, 8>,
156 SmallPtrSet<LiveInterval*, 8> > ToShrink;
159 // Erase all dead defs.
160 while (!Dead.empty()) {
161 MachineInstr *MI = Dead.pop_back_val();
162 assert(MI->allDefsAreDead() && "Def isn't really dead");
163 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex();
165 // Never delete inline asm.
166 if (MI->isInlineAsm()) {
167 DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
171 // Use the same criteria as DeadMachineInstructionElim.
172 bool SawStore = false;
173 if (!MI->isSafeToMove(&TII, 0, SawStore)) {
174 DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
178 DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
180 // Check for live intervals that may shrink
181 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
182 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
185 unsigned Reg = MOI->getReg();
186 if (!TargetRegisterInfo::isVirtualRegister(Reg))
188 LiveInterval &LI = LIS.getInterval(Reg);
190 // Shrink read registers.
191 if (MI->readsVirtualRegister(Reg))
192 ToShrink.insert(&LI);
194 // Remove defined value.
196 if (VNInfo *VNI = LI.getVNInfoAt(Idx)) {
198 delegate_->LRE_WillShrinkVirtReg(LI.reg);
201 ToShrink.remove(&LI);
202 eraseVirtReg(Reg, LIS);
209 delegate_->LRE_WillEraseInstruction(MI);
210 LIS.RemoveMachineInstrFromMaps(MI);
211 MI->eraseFromParent();
214 if (ToShrink.empty())
217 // Shrink just one live interval. Then delete new dead defs.
218 LiveInterval *LI = ToShrink.back();
221 delegate_->LRE_WillShrinkVirtReg(LI->reg);
222 if (!LIS.shrinkToUses(LI, &Dead))
225 // LI may have been separated, create new intervals.
226 LI->RenumberValues(LIS);
227 ConnectedVNInfoEqClasses ConEQ(LIS);
228 unsigned NumComp = ConEQ.Classify(LI);
231 DEBUG(dbgs() << NumComp << " components: " << *LI << '\n');
232 SmallVector<LiveInterval*, 8> Dups(1, LI);
233 for (unsigned i = 1; i != NumComp; ++i)
234 Dups.push_back(&createFrom(LI->reg, LIS, VRM));
235 ConEQ.Distribute(&Dups[0], VRM.getRegInfo());