1 //===-- LiveIntervalUnion.h - Live interval union data struct --*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // LiveIntervalUnion is a union of live segments across multiple live virtual
11 // registers. This may be used during coalescing to represent a congruence
12 // class, or during register allocation to model liveness of a physical
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_LIVEINTERVALUNION
18 #define LLVM_CODEGEN_LIVEINTERVALUNION
20 #include "llvm/ADT/IntervalMap.h"
21 #include "llvm/CodeGen/LiveInterval.h"
27 class MachineLoopRange;
28 class TargetRegisterInfo;
31 // forward declaration
32 template <unsigned Element> class SparseBitVector;
33 typedef SparseBitVector<128> LiveVirtRegBitSet;
36 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
38 overlap(const LiveRange &VRSeg,
39 const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
40 return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
43 /// Union of live intervals that are strong candidates for coalescing into a
44 /// single register (either physical or virtual depending on the context). We
45 /// expect the constituent live intervals to be disjoint, although we may
46 /// eventually make exceptions to handle value-based interference.
47 class LiveIntervalUnion {
48 // A set of live virtual register segments that supports fast insertion,
49 // intersection, and removal.
50 // Mapping SlotIndex intervals to virtual register numbers.
51 typedef IntervalMap<SlotIndex, LiveInterval*> LiveSegments;
54 // SegmentIter can advance to the next segment ordered by starting position
55 // which may belong to a different live virtual register. We also must be able
56 // to reach the current segment's containing virtual register.
57 typedef LiveSegments::iterator SegmentIter;
59 // LiveIntervalUnions share an external allocator.
60 typedef LiveSegments::Allocator Allocator;
62 class InterferenceResult;
66 const unsigned RepReg; // representative register number
67 LiveSegments Segments; // union of virtual reg segments
70 LiveIntervalUnion(unsigned r, Allocator &a) : RepReg(r), Segments(a) {}
72 // Iterate over all segments in the union of live virtual registers ordered
73 // by their starting position.
74 SegmentIter begin() { return Segments.begin(); }
75 SegmentIter end() { return Segments.end(); }
76 SegmentIter find(SlotIndex x) { return Segments.find(x); }
77 bool empty() const { return Segments.empty(); }
78 SlotIndex startIndex() const { return Segments.start(); }
80 // Provide public access to the underlying map to allow overlap iteration.
81 typedef LiveSegments Map;
82 const Map &getMap() { return Segments; }
84 // Add a live virtual register to this union and merge its segments.
85 void unify(LiveInterval &VirtReg);
87 // Remove a live virtual register's segments from this union.
88 void extract(LiveInterval &VirtReg);
90 // Print union, using TRI to translate register names
91 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
94 // Verify the live intervals in this union and add them to the visited set.
95 void verify(LiveVirtRegBitSet& VisitedVRegs);
98 /// Cache a single interference test result in the form of two intersecting
99 /// segments. This allows efficiently iterating over the interferences. The
100 /// iteration logic is handled by LiveIntervalUnion::Query which may
101 /// filter interferences depending on the type of query.
102 class InterferenceResult {
105 LiveInterval::iterator VirtRegI; // current position in VirtReg
106 SegmentIter LiveUnionI; // current position in LiveUnion
109 InterferenceResult(LiveInterval::iterator VRegI, SegmentIter UnionI)
110 : VirtRegI(VRegI), LiveUnionI(UnionI) {}
113 // Public default ctor.
114 InterferenceResult(): VirtRegI(), LiveUnionI() {}
116 /// start - Return the start of the current overlap.
117 SlotIndex start() const {
118 return std::max(VirtRegI->start, LiveUnionI.start());
121 /// stop - Return the end of the current overlap.
122 SlotIndex stop() const {
123 return std::min(VirtRegI->end, LiveUnionI.stop());
126 /// interference - Return the register that is interfering here.
127 LiveInterval *interference() const { return LiveUnionI.value(); }
129 // Note: this interface provides raw access to the iterators because the
130 // result has no way to tell if it's valid to dereference them.
132 // Access the VirtReg segment.
133 LiveInterval::iterator virtRegPos() const { return VirtRegI; }
135 // Access the LiveUnion segment.
136 const SegmentIter &liveUnionPos() const { return LiveUnionI; }
138 bool operator==(const InterferenceResult &IR) const {
139 return VirtRegI == IR.VirtRegI && LiveUnionI == IR.LiveUnionI;
141 bool operator!=(const InterferenceResult &IR) const {
142 return !operator==(IR);
145 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
148 /// Query interferences between a single live virtual register and a live
151 LiveIntervalUnion *LiveUnion;
152 LiveInterval *VirtReg;
153 InterferenceResult FirstInterference;
154 SmallVector<LiveInterval*,4> InterferingVRegs;
155 bool CheckedFirstInterference;
156 bool SeenAllInterferences;
157 bool SeenUnspillableVReg;
160 Query(): LiveUnion(), VirtReg() {}
162 Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
163 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
164 SeenAllInterferences(false), SeenUnspillableVReg(false)
170 InterferingVRegs.clear();
171 CheckedFirstInterference = false;
172 SeenAllInterferences = false;
173 SeenUnspillableVReg = false;
176 void init(LiveInterval *VReg, LiveIntervalUnion *LIU) {
177 assert(VReg && LIU && "Invalid arguments");
178 if (VirtReg == VReg && LiveUnion == LIU) {
179 // Retain cached results, e.g. firstInterference.
187 LiveInterval &virtReg() const {
188 assert(VirtReg && "uninitialized");
192 bool isInterference(const InterferenceResult &IR) const {
193 if (IR.VirtRegI != VirtReg->end()) {
194 assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
195 "invalid segment iterators");
201 // Does this live virtual register interfere with the union?
202 bool checkInterference() { return isInterference(firstInterference()); }
204 // Get the first pair of interfering segments, or a noninterfering result.
205 // This initializes the firstInterference_ cache.
206 const InterferenceResult &firstInterference();
208 // Treat the result as an iterator and advance to the next interfering pair
209 // of segments. Visiting each unique interfering pairs means that the same
210 // VirtReg or LiveUnion segment may be visited multiple times.
211 bool nextInterference(InterferenceResult &IR) const;
213 // Count the virtual registers in this union that interfere with this
214 // query's live virtual register, up to maxInterferingRegs.
215 unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
217 // Was this virtual register visited during collectInterferingVRegs?
218 bool isSeenInterference(LiveInterval *VReg) const;
220 // Did collectInterferingVRegs collect all interferences?
221 bool seenAllInterferences() const { return SeenAllInterferences; }
223 // Did collectInterferingVRegs encounter an unspillable vreg?
224 bool seenUnspillableVReg() const { return SeenUnspillableVReg; }
226 // Vector generated by collectInterferingVRegs.
227 const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
228 return InterferingVRegs;
231 /// checkLoopInterference - Return true if there is interference overlapping
233 bool checkLoopInterference(MachineLoopRange*);
235 void print(raw_ostream &OS, const TargetRegisterInfo *TRI);
237 Query(const Query&); // DO NOT IMPLEMENT
238 void operator=(const Query&); // DO NOT IMPLEMENT
240 // Private interface for queries
241 void findIntersection(InterferenceResult &IR) const;
245 } // end namespace llvm
247 #endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION)