1 //===-- LiveIntervalUnion.h - Live interval union data struct --*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // LiveIntervalUnion is a union of live segments across multiple live virtual
11 // registers. This may be used during coalescing to represent a congruence
12 // class, or during register allocation to model liveness of a physical
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_LIVEINTERVALUNION
18 #define LLVM_CODEGEN_LIVEINTERVALUNION
20 #include "llvm/ADT/IntervalMap.h"
21 #include "llvm/CodeGen/LiveInterval.h"
27 class TargetRegisterInfo;
30 // forward declaration
31 template <unsigned Element> class SparseBitVector;
32 typedef SparseBitVector<128> LiveVirtRegBitSet;
35 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
37 overlap(const LiveRange &VRSeg,
38 const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
39 return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
42 /// Union of live intervals that are strong candidates for coalescing into a
43 /// single register (either physical or virtual depending on the context). We
44 /// expect the constituent live intervals to be disjoint, although we may
45 /// eventually make exceptions to handle value-based interference.
46 class LiveIntervalUnion {
47 // A set of live virtual register segments that supports fast insertion,
48 // intersection, and removal.
49 // Mapping SlotIndex intervals to virtual register numbers.
50 typedef IntervalMap<SlotIndex, LiveInterval*> LiveSegments;
53 // SegmentIter can advance to the next segment ordered by starting position
54 // which may belong to a different live virtual register. We also must be able
55 // to reach the current segment's containing virtual register.
56 typedef LiveSegments::iterator SegmentIter;
58 // LiveIntervalUnions share an external allocator.
59 typedef LiveSegments::Allocator Allocator;
61 class InterferenceResult;
65 const unsigned RepReg; // representative register number
66 LiveSegments Segments; // union of virtual reg segments
69 LiveIntervalUnion(unsigned r, Allocator &a) : RepReg(r), Segments(a) {}
71 // Iterate over all segments in the union of live virtual registers ordered
72 // by their starting position.
73 SegmentIter begin() { return Segments.begin(); }
74 SegmentIter end() { return Segments.end(); }
75 SegmentIter find(SlotIndex x) { return Segments.find(x); }
76 bool empty() const { return Segments.empty(); }
77 SlotIndex startIndex() const { return Segments.start(); }
79 // Add a live virtual register to this union and merge its segments.
80 void unify(LiveInterval &VirtReg);
82 // Remove a live virtual register's segments from this union.
83 void extract(LiveInterval &VirtReg);
85 // Print union, using TRI to translate register names
86 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
89 // Verify the live intervals in this union and add them to the visited set.
90 void verify(LiveVirtRegBitSet& VisitedVRegs);
93 /// Cache a single interference test result in the form of two intersecting
94 /// segments. This allows efficiently iterating over the interferences. The
95 /// iteration logic is handled by LiveIntervalUnion::Query which may
96 /// filter interferences depending on the type of query.
97 class InterferenceResult {
100 LiveInterval::iterator VirtRegI; // current position in VirtReg
101 SegmentIter LiveUnionI; // current position in LiveUnion
104 InterferenceResult(LiveInterval::iterator VRegI, SegmentIter UnionI)
105 : VirtRegI(VRegI), LiveUnionI(UnionI) {}
108 // Public default ctor.
109 InterferenceResult(): VirtRegI(), LiveUnionI() {}
111 /// start - Return the start of the current overlap.
112 SlotIndex start() const {
113 return std::max(VirtRegI->start, LiveUnionI.start());
116 /// stop - Return the end of the current overlap.
117 SlotIndex stop() const {
118 return std::min(VirtRegI->end, LiveUnionI.stop());
121 /// interference - Return the register that is interfering here.
122 LiveInterval *interference() const { return LiveUnionI.value(); }
124 // Note: this interface provides raw access to the iterators because the
125 // result has no way to tell if it's valid to dereference them.
127 // Access the VirtReg segment.
128 LiveInterval::iterator virtRegPos() const { return VirtRegI; }
130 // Access the LiveUnion segment.
131 const SegmentIter &liveUnionPos() const { return LiveUnionI; }
133 bool operator==(const InterferenceResult &IR) const {
134 return VirtRegI == IR.VirtRegI && LiveUnionI == IR.LiveUnionI;
136 bool operator!=(const InterferenceResult &IR) const {
137 return !operator==(IR);
140 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
143 /// Query interferences between a single live virtual register and a live
146 LiveIntervalUnion *LiveUnion;
147 LiveInterval *VirtReg;
148 InterferenceResult FirstInterference;
149 SmallVector<LiveInterval*,4> InterferingVRegs;
150 bool CheckedFirstInterference;
151 bool SeenAllInterferences;
152 bool SeenUnspillableVReg;
155 Query(): LiveUnion(), VirtReg() {}
157 Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
158 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
159 SeenAllInterferences(false), SeenUnspillableVReg(false)
165 InterferingVRegs.clear();
166 CheckedFirstInterference = false;
167 SeenAllInterferences = false;
168 SeenUnspillableVReg = false;
171 void init(LiveInterval *VReg, LiveIntervalUnion *LIU) {
172 assert(VReg && LIU && "Invalid arguments");
173 if (VirtReg == VReg && LiveUnion == LIU) {
174 // Retain cached results, e.g. firstInterference.
182 LiveInterval &virtReg() const {
183 assert(VirtReg && "uninitialized");
187 bool isInterference(const InterferenceResult &IR) const {
188 if (IR.VirtRegI != VirtReg->end()) {
189 assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
190 "invalid segment iterators");
196 // Does this live virtual register interfere with the union?
197 bool checkInterference() { return isInterference(firstInterference()); }
199 // Get the first pair of interfering segments, or a noninterfering result.
200 // This initializes the firstInterference_ cache.
201 const InterferenceResult &firstInterference();
203 // Treat the result as an iterator and advance to the next interfering pair
204 // of segments. Visiting each unique interfering pairs means that the same
205 // VirtReg or LiveUnion segment may be visited multiple times.
206 bool nextInterference(InterferenceResult &IR) const;
208 // Count the virtual registers in this union that interfere with this
209 // query's live virtual register, up to maxInterferingRegs.
210 unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
212 // Was this virtual register visited during collectInterferingVRegs?
213 bool isSeenInterference(LiveInterval *VReg) const;
215 // Did collectInterferingVRegs collect all interferences?
216 bool seenAllInterferences() const { return SeenAllInterferences; }
218 // Did collectInterferingVRegs encounter an unspillable vreg?
219 bool seenUnspillableVReg() const { return SeenUnspillableVReg; }
221 // Vector generated by collectInterferingVRegs.
222 const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
223 return InterferingVRegs;
226 void print(raw_ostream &OS, const TargetRegisterInfo *TRI);
228 Query(const Query&); // DO NOT IMPLEMENT
229 void operator=(const Query&); // DO NOT IMPLEMENT
231 // Private interface for queries
232 void findIntersection(InterferenceResult &IR) const;
236 } // end namespace llvm
238 #endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION)