1 //===-- LiveIntervalUnion.h - Live interval union data struct --*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // LiveIntervalUnion is a union of live segments across multiple live virtual
11 // registers. This may be used during coalescing to represent a congruence
12 // class, or during register allocation to model liveness of a physical
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_LIVEINTERVALUNION
18 #define LLVM_CODEGEN_LIVEINTERVALUNION
20 #include "llvm/ADT/IntervalMap.h"
21 #include "llvm/CodeGen/LiveInterval.h"
27 class MachineLoopRange;
28 class TargetRegisterInfo;
31 // forward declaration
32 template <unsigned Element> class SparseBitVector;
33 typedef SparseBitVector<128> LiveVirtRegBitSet;
36 /// Compare a live virtual register segment to a LiveIntervalUnion segment.
38 overlap(const LiveRange &VRSeg,
39 const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
40 return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
43 /// Union of live intervals that are strong candidates for coalescing into a
44 /// single register (either physical or virtual depending on the context). We
45 /// expect the constituent live intervals to be disjoint, although we may
46 /// eventually make exceptions to handle value-based interference.
47 class LiveIntervalUnion {
48 // A set of live virtual register segments that supports fast insertion,
49 // intersection, and removal.
50 // Mapping SlotIndex intervals to virtual register numbers.
51 typedef IntervalMap<SlotIndex, LiveInterval*> LiveSegments;
54 // SegmentIter can advance to the next segment ordered by starting position
55 // which may belong to a different live virtual register. We also must be able
56 // to reach the current segment's containing virtual register.
57 typedef LiveSegments::iterator SegmentIter;
59 // LiveIntervalUnions share an external allocator.
60 typedef LiveSegments::Allocator Allocator;
62 class InterferenceResult;
66 const unsigned RepReg; // representative register number
67 unsigned Tag; // unique tag for current contents.
68 LiveSegments Segments; // union of virtual reg segments
71 LiveIntervalUnion(unsigned r, Allocator &a) : RepReg(r), Tag(0), Segments(a)
74 // Iterate over all segments in the union of live virtual registers ordered
75 // by their starting position.
76 SegmentIter begin() { return Segments.begin(); }
77 SegmentIter end() { return Segments.end(); }
78 SegmentIter find(SlotIndex x) { return Segments.find(x); }
79 bool empty() const { return Segments.empty(); }
80 SlotIndex startIndex() const { return Segments.start(); }
82 // Provide public access to the underlying map to allow overlap iteration.
83 typedef LiveSegments Map;
84 const Map &getMap() { return Segments; }
86 /// getTag - Return an opaque tag representing the current state of the union.
87 unsigned getTag() const { return Tag; }
89 /// changedSince - Return true if the union change since getTag returned tag.
90 bool changedSince(unsigned tag) const { return tag != Tag; }
92 // Add a live virtual register to this union and merge its segments.
93 void unify(LiveInterval &VirtReg);
95 // Remove a live virtual register's segments from this union.
96 void extract(LiveInterval &VirtReg);
98 // Remove all inserted virtual registers.
99 void clear() { Segments.clear(); ++Tag; }
101 // Print union, using TRI to translate register names
102 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
105 // Verify the live intervals in this union and add them to the visited set.
106 void verify(LiveVirtRegBitSet& VisitedVRegs);
109 /// Cache a single interference test result in the form of two intersecting
110 /// segments. This allows efficiently iterating over the interferences. The
111 /// iteration logic is handled by LiveIntervalUnion::Query which may
112 /// filter interferences depending on the type of query.
113 class InterferenceResult {
116 LiveInterval::iterator VirtRegI; // current position in VirtReg
117 SegmentIter LiveUnionI; // current position in LiveUnion
120 InterferenceResult(LiveInterval::iterator VRegI, SegmentIter UnionI)
121 : VirtRegI(VRegI), LiveUnionI(UnionI) {}
124 // Public default ctor.
125 InterferenceResult(): VirtRegI(), LiveUnionI() {}
127 /// interference - Return the register that is interfering here.
128 LiveInterval *interference() const { return LiveUnionI.value(); }
130 // Note: this interface provides raw access to the iterators because the
131 // result has no way to tell if it's valid to dereference them.
133 // Access the VirtReg segment.
134 LiveInterval::iterator virtRegPos() const { return VirtRegI; }
136 // Access the LiveUnion segment.
137 const SegmentIter &liveUnionPos() const { return LiveUnionI; }
140 /// Query interferences between a single live virtual register and a live
143 LiveIntervalUnion *LiveUnion;
144 LiveInterval *VirtReg;
145 InterferenceResult FirstInterference;
146 SmallVector<LiveInterval*,4> InterferingVRegs;
147 bool CheckedFirstInterference;
148 bool SeenAllInterferences;
149 bool SeenUnspillableVReg;
150 unsigned Tag, UserTag;
153 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
155 Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
156 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
157 SeenAllInterferences(false), SeenUnspillableVReg(false)
163 InterferingVRegs.clear();
164 CheckedFirstInterference = false;
165 SeenAllInterferences = false;
166 SeenUnspillableVReg = false;
171 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) {
172 assert(VReg && LIU && "Invalid arguments");
173 if (UserTag == UTag && VirtReg == VReg &&
174 LiveUnion == LIU && !LIU->changedSince(Tag)) {
175 // Retain cached results, e.g. firstInterference.
185 LiveInterval &virtReg() const {
186 assert(VirtReg && "uninitialized");
190 bool isInterference(const InterferenceResult &IR) const {
191 if (IR.VirtRegI != VirtReg->end()) {
192 assert(overlap(*IR.VirtRegI, IR.LiveUnionI) &&
193 "invalid segment iterators");
199 // Does this live virtual register interfere with the union?
200 bool checkInterference() { return isInterference(firstInterference()); }
202 // Get the first pair of interfering segments, or a noninterfering result.
203 // This initializes the firstInterference_ cache.
204 const InterferenceResult &firstInterference();
206 // Treat the result as an iterator and advance to the next interfering pair
207 // of segments. Visiting each unique interfering pairs means that the same
208 // VirtReg or LiveUnion segment may be visited multiple times.
209 bool nextInterference(InterferenceResult &IR) const;
211 // Count the virtual registers in this union that interfere with this
212 // query's live virtual register, up to maxInterferingRegs.
213 unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
215 // Was this virtual register visited during collectInterferingVRegs?
216 bool isSeenInterference(LiveInterval *VReg) const;
218 // Did collectInterferingVRegs collect all interferences?
219 bool seenAllInterferences() const { return SeenAllInterferences; }
221 // Did collectInterferingVRegs encounter an unspillable vreg?
222 bool seenUnspillableVReg() const { return SeenUnspillableVReg; }
224 // Vector generated by collectInterferingVRegs.
225 const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
226 return InterferingVRegs;
229 /// checkLoopInterference - Return true if there is interference overlapping
231 bool checkLoopInterference(MachineLoopRange*);
234 Query(const Query&); // DO NOT IMPLEMENT
235 void operator=(const Query&); // DO NOT IMPLEMENT
237 // Private interface for queries
238 void findIntersection(InterferenceResult &IR) const;
242 } // end namespace llvm
244 #endif // !defined(LLVM_CODEGEN_LIVEINTERVALUNION)