1 //===-- LiveIntervals.cpp - Live Interval Analysis ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervals.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetRegInfo.h"
31 #include "llvm/Support/CFG.h"
32 #include "Support/Debug.h"
33 #include "Support/DepthFirstIterator.h"
34 #include "Support/Statistic.h"
40 RegisterAnalysis<LiveIntervals> X("liveintervals",
41 "Live Interval Analysis");
43 Statistic<> numIntervals("liveintervals", "Number of intervals");
46 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
48 AU.addPreserved<LiveVariables>();
49 AU.addRequired<LiveVariables>();
50 AU.addPreservedID(PHIEliminationID);
51 AU.addRequiredID(PHIEliminationID);
52 MachineFunctionPass::getAnalysisUsage(AU);
55 /// runOnMachineFunction - Register allocate the whole function
57 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
58 DEBUG(std::cerr << "Machine Function\n");
60 tm_ = &fn.getTarget();
61 mri_ = tm_->getRegisterInfo();
62 lv_ = &getAnalysis<LiveVariables>();
63 allocatableRegisters_.clear();
70 // mark allocatable registers
71 allocatableRegisters_.resize(MRegisterInfo::FirstVirtualRegister);
72 // Loop over all of the register classes...
73 for (MRegisterInfo::regclass_iterator
74 rci = mri_->regclass_begin(), rce = mri_->regclass_end();
76 // Loop over all of the allocatable registers in the function...
77 for (TargetRegisterClass::iterator
78 i = (*rci)->allocation_order_begin(*mf_),
79 e = (*rci)->allocation_order_end(*mf_); i != e; ++i) {
80 allocatableRegisters_[*i] = true; // The reg is allocatable!
84 // number MachineInstrs
86 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
87 mbb != mbbEnd; ++mbb) {
88 const std::pair<MachineBasicBlock*, unsigned>& entry =
89 lv_->getMachineBasicBlockInfo(&*mbb);
90 bool inserted = mbbi2mbbMap_.insert(std::make_pair(entry.second,
92 assert(inserted && "multiple index -> MachineBasicBlock");
94 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
96 inserted = mi2iMap_.insert(std::make_pair(*mi, miIndex)).second;
97 assert(inserted && "multiple MachineInstr -> index mappings");
107 void LiveIntervals::printRegName(unsigned reg) const
109 if (reg < MRegisterInfo::FirstVirtualRegister)
110 std::cerr << mri_->getName(reg);
112 std::cerr << '%' << reg;
115 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
116 MachineBasicBlock::iterator mi,
119 DEBUG(std::cerr << "\t\t\tregister: ";printRegName(reg); std::cerr << '\n');
121 unsigned instrIndex = getInstructionIndex(*mi);
123 LiveVariables::VarInfo& vi = lv_->getVarInfo(reg);
125 Interval* interval = 0;
126 Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
127 if (r2iit == r2iMap_.end()) {
129 intervals_.push_back(Interval(reg));
130 // update interval index for this register
131 r2iMap_[reg] = intervals_.size() - 1;
132 interval = &intervals_.back();
135 interval = &intervals_[r2iit->second];
138 for (MbbIndex2MbbMap::iterator
139 it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
141 unsigned liveBlockIndex = it->first;
142 MachineBasicBlock* liveBlock = it->second;
143 if (liveBlockIndex < vi.AliveBlocks.size() &&
144 vi.AliveBlocks[liveBlockIndex]) {
145 unsigned start = getInstructionIndex(liveBlock->front());
146 unsigned end = getInstructionIndex(liveBlock->back()) + 1;
147 interval->addRange(start, end);
151 bool killedInDefiningBasicBlock = false;
152 for (int i = 0, e = vi.Kills.size(); i != e; ++i) {
153 MachineBasicBlock* killerBlock = vi.Kills[i].first;
154 MachineInstr* killerInstr = vi.Kills[i].second;
155 unsigned start = (mbb == killerBlock ?
157 getInstructionIndex(killerBlock->front()));
158 unsigned end = getInstructionIndex(killerInstr) + 1;
160 killedInDefiningBasicBlock |= mbb == killerBlock;
161 interval->addRange(start, end);
165 if (!killedInDefiningBasicBlock) {
166 unsigned end = getInstructionIndex(mbb->back()) + 1;
167 interval->addRange(instrIndex, end);
171 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock* mbb,
172 MachineBasicBlock::iterator mi,
175 DEBUG(std::cerr << "\t\t\tregister: ";printRegName(reg); std::cerr << '\n');
176 if (!lv_->getAllocatablePhysicalRegisters()[reg]) {
177 DEBUG(std::cerr << "\t\t\t\tnon allocatable register: ignoring\n");
181 unsigned start = getInstructionIndex(*mi);
182 unsigned end = start;
184 for (MachineBasicBlock::iterator e = mbb->end(); mi != e; ++mi) {
185 for (LiveVariables::killed_iterator
186 ki = lv_->dead_begin(*mi),
187 ke = lv_->dead_end(*mi);
189 if (reg == ki->second) {
190 end = getInstructionIndex(ki->first) + 1;
195 for (LiveVariables::killed_iterator
196 ki = lv_->killed_begin(*mi),
197 ke = lv_->killed_end(*mi);
199 if (reg == ki->second) {
200 end = getInstructionIndex(ki->first) + 1;
206 assert(start < end && "did not find end of interval?");
208 Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
209 if (r2iit != r2iMap_.end()) {
210 unsigned ii = r2iit->second;
211 Interval& interval = intervals_[ii];
212 interval.addRange(start, end);
215 intervals_.push_back(Interval(reg));
216 Interval& interval = intervals_.back();
217 // update interval index for this register
218 r2iMap_[reg] = intervals_.size() - 1;
219 interval.addRange(start, end);
223 void LiveIntervals::handleRegisterDef(MachineBasicBlock* mbb,
224 MachineBasicBlock::iterator mi,
227 if (reg < MRegisterInfo::FirstVirtualRegister) {
228 if (allocatableRegisters_[reg]) {
229 handlePhysicalRegisterDef(mbb, mi, reg);
233 handleVirtualRegisterDef(mbb, mi, reg);
237 unsigned LiveIntervals::getInstructionIndex(MachineInstr* instr) const
239 assert(mi2iMap_.find(instr) != mi2iMap_.end() &&
240 "instruction not assigned a number");
241 return mi2iMap_.find(instr)->second;
244 /// computeIntervals - computes the live intervals for virtual
245 /// registers. for some ordering of the machine instructions [1,N] a
246 /// live interval is an interval [i, j] where 1 <= i <= j <= N for
247 /// which a variable is live
248 void LiveIntervals::computeIntervals()
250 DEBUG(std::cerr << "computing live intervals:\n");
252 for (MbbIndex2MbbMap::iterator
253 it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
255 MachineBasicBlock* mbb = it->second;
256 DEBUG(std::cerr << "machine basic block: "
257 << mbb->getBasicBlock()->getName() << "\n");
258 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
260 MachineInstr* instr = *mi;
261 const TargetInstrDescriptor& tid =
262 tm_->getInstrInfo().get(instr->getOpcode());
263 DEBUG(std::cerr << "\t\tinstruction["
264 << getInstructionIndex(instr) << "]: ";
265 instr->print(std::cerr, *tm_););
267 // handle implicit defs
268 for (const unsigned* id = tid.ImplicitDefs; *id; ++id) {
269 unsigned physReg = *id;
270 handlePhysicalRegisterDef(mbb, mi, physReg);
273 // handle explicit defs
274 for (int i = instr->getNumOperands() - 1; i >= 0; --i) {
275 MachineOperand& mop = instr->getOperand(i);
277 if (!mop.isRegister())
281 unsigned reg = mop.getAllocatedRegNum();
282 if (reg < MRegisterInfo::FirstVirtualRegister)
283 handlePhysicalRegisterDef(mbb, mi, reg);
285 handleVirtualRegisterDef(mbb, mi, reg);
291 std::sort(intervals_.begin(), intervals_.end(), StartPointComp());
292 DEBUG(std::copy(intervals_.begin(), intervals_.end(),
293 std::ostream_iterator<Interval>(std::cerr, "\n")));
296 void LiveIntervals::Interval::addRange(unsigned start, unsigned end)
298 DEBUG(std::cerr << "\t\t\t\tadding range: [" << start <<','<< end << "]\n");
299 //assert(start < end && "invalid range?");
300 Range range = std::make_pair(start, end);
301 Ranges::iterator it =
302 ranges.insert(std::upper_bound(ranges.begin(), ranges.end(), range),
305 DEBUG(std::cerr << "\t\t\t\tbefore merge forward: " << *this << '\n');
306 mergeRangesForward(it);
307 DEBUG(std::cerr << "\t\t\t\tbefore merge backward: " << *this << '\n');
308 mergeRangesBackward(it);
309 DEBUG(std::cerr << "\t\t\t\tafter merging: " << *this << '\n');
312 void LiveIntervals::Interval::mergeRangesForward(Ranges::iterator it)
314 for (Ranges::iterator next = it + 1;
315 next != ranges.end() && it->second >= next->first; ) {
316 it->second = std::max(it->second, next->second);
317 next = ranges.erase(next);
321 void LiveIntervals::Interval::mergeRangesBackward(Ranges::iterator it)
323 for (Ranges::iterator prev = it - 1;
324 it != ranges.begin() && it->first <= prev->second; ) {
325 it->first = std::min(it->first, prev->first);
326 it->second = std::max(it->second, prev->second);
327 it = ranges.erase(prev);
332 std::ostream& llvm::operator<<(std::ostream& os,
333 const LiveIntervals::Interval& li)
335 os << "%reg" << li.reg << " = ";
336 for (LiveIntervals::Interval::Ranges::const_iterator
337 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
338 os << "[" << i->first << "," << i->second << "]";