1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "LiveRangeCalc.h"
20 #include "llvm/ADT/DenseSet.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Analysis/AliasAnalysis.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineDominators.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Value.h"
31 #include "llvm/Support/BlockFrequency.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/Format.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "regalloc"
47 char LiveIntervals::ID = 0;
48 char &llvm::LiveIntervalsID = LiveIntervals::ID;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
52 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
53 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
54 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
55 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
56 "Live Interval Analysis", false, false)
59 static cl::opt<bool> EnablePrecomputePhysRegs(
60 "precompute-phys-liveness", cl::Hidden,
61 cl::desc("Eagerly compute live intervals for all physreg units."));
63 static bool EnablePrecomputePhysRegs = false;
66 static cl::opt<bool> EnableSubRegLiveness(
67 "enable-subreg-liveness", cl::Hidden, cl::init(true),
68 cl::desc("Enable subregister liveness tracking."));
70 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addPreserved<AliasAnalysis>();
74 // LiveVariables isn't really required by this analysis, it is only required
75 // here to make sure it is live during TwoAddressInstructionPass and
76 // PHIElimination. This is temporary.
77 AU.addRequired<LiveVariables>();
78 AU.addPreserved<LiveVariables>();
79 AU.addPreservedID(MachineLoopInfoID);
80 AU.addRequiredTransitiveID(MachineDominatorsID);
81 AU.addPreservedID(MachineDominatorsID);
82 AU.addPreserved<SlotIndexes>();
83 AU.addRequiredTransitive<SlotIndexes>();
84 MachineFunctionPass::getAnalysisUsage(AU);
87 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
88 DomTree(nullptr), LRCalc(nullptr) {
89 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
92 LiveIntervals::~LiveIntervals() {
96 void LiveIntervals::releaseMemory() {
97 // Free the live intervals themselves.
98 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
99 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
100 VirtRegIntervals.clear();
101 RegMaskSlots.clear();
103 RegMaskBlocks.clear();
105 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
106 delete RegUnitRanges[i];
107 RegUnitRanges.clear();
109 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
110 VNInfoAllocator.Reset();
113 /// runOnMachineFunction - calculates LiveIntervals
115 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
117 MRI = &MF->getRegInfo();
118 TRI = MF->getSubtarget().getRegisterInfo();
119 TII = MF->getSubtarget().getInstrInfo();
120 AA = &getAnalysis<AliasAnalysis>();
121 Indexes = &getAnalysis<SlotIndexes>();
122 DomTree = &getAnalysis<MachineDominatorTree>();
124 if (EnableSubRegLiveness && MF->getSubtarget().enableSubRegLiveness())
125 MRI->enableSubRegLiveness(true);
128 LRCalc = new LiveRangeCalc();
130 // Allocate space for all virtual registers.
131 VirtRegIntervals.resize(MRI->getNumVirtRegs());
135 computeLiveInRegUnits();
137 if (EnablePrecomputePhysRegs) {
138 // For stress testing, precompute live ranges of all physical register
139 // units, including reserved registers.
140 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
147 /// print - Implement the dump method.
148 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
149 OS << "********** INTERVALS **********\n";
151 // Dump the regunits.
152 for (unsigned i = 0, e = RegUnitRanges.size(); i != e; ++i)
153 if (LiveRange *LR = RegUnitRanges[i])
154 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
156 // Dump the virtregs.
157 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
158 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
159 if (hasInterval(Reg))
160 OS << getInterval(Reg) << '\n';
164 for (unsigned i = 0, e = RegMaskSlots.size(); i != e; ++i)
165 OS << ' ' << RegMaskSlots[i];
171 void LiveIntervals::printInstrs(raw_ostream &OS) const {
172 OS << "********** MACHINEINSTRS **********\n";
173 MF->print(OS, Indexes);
176 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
177 void LiveIntervals::dumpInstrs() const {
182 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
183 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ?
184 llvm::huge_valf : 0.0F;
185 return new LiveInterval(reg, Weight);
189 /// computeVirtRegInterval - Compute the live interval of a virtual register,
190 /// based on defs and uses.
191 void LiveIntervals::computeVirtRegInterval(LiveInterval &LI) {
192 assert(LRCalc && "LRCalc not initialized.");
193 assert(LI.empty() && "Should only compute empty intervals.");
194 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
195 LRCalc->calculate(LI);
196 computeDeadValues(LI, LI);
199 void LiveIntervals::computeVirtRegs() {
200 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
201 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
202 if (MRI->reg_nodbg_empty(Reg))
204 createAndComputeVirtRegInterval(Reg);
208 void LiveIntervals::computeRegMasks() {
209 RegMaskBlocks.resize(MF->getNumBlockIDs());
211 // Find all instructions with regmask operands.
212 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
214 MachineBasicBlock *MBB = MBBI;
215 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
216 RMB.first = RegMaskSlots.size();
217 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
219 for (MIOperands MO(MI); MO.isValid(); ++MO) {
220 if (!MO->isRegMask())
222 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
223 RegMaskBits.push_back(MO->getRegMask());
225 // Compute the number of register mask instructions in this block.
226 RMB.second = RegMaskSlots.size() - RMB.first;
230 //===----------------------------------------------------------------------===//
231 // Register Unit Liveness
232 //===----------------------------------------------------------------------===//
234 // Fixed interference typically comes from ABI boundaries: Function arguments
235 // and return values are passed in fixed registers, and so are exception
236 // pointers entering landing pads. Certain instructions require values to be
237 // present in specific registers. That is also represented through fixed
241 /// computeRegUnitInterval - Compute the live range of a register unit, based
242 /// on the uses and defs of aliasing registers. The range should be empty,
243 /// or contain only dead phi-defs from ABI blocks.
244 void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
245 assert(LRCalc && "LRCalc not initialized.");
246 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
248 // The physregs aliasing Unit are the roots and their super-registers.
249 // Create all values as dead defs before extending to uses. Note that roots
250 // may share super-registers. That's OK because createDeadDefs() is
251 // idempotent. It is very rare for a register unit to have multiple roots, so
252 // uniquing super-registers is probably not worthwhile.
253 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
254 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
255 Supers.isValid(); ++Supers) {
256 unsigned Reg = *Supers;
257 if (MRI->reg_empty(Reg))
259 // Ignore uses of reserved registers. We only track defs of those.
260 bool IgnoreUses = MRI->isReserved(Reg);
261 LRCalc->calculate(LR, *Supers, IgnoreUses);
267 /// computeLiveInRegUnits - Precompute the live ranges of any register units
268 /// that are live-in to an ABI block somewhere. Register values can appear
269 /// without a corresponding def when entering the entry block or a landing pad.
271 void LiveIntervals::computeLiveInRegUnits() {
272 RegUnitRanges.resize(TRI->getNumRegUnits());
273 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
275 // Keep track of the live range sets allocated.
276 SmallVector<unsigned, 8> NewRanges;
278 // Check all basic blocks for live-ins.
279 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
281 const MachineBasicBlock *MBB = MFI;
283 // We only care about ABI blocks: Entry + landing pads.
284 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
287 // Create phi-defs at Begin for all live-in registers.
288 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
289 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
290 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
291 LIE = MBB->livein_end(); LII != LIE; ++LII) {
292 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
293 unsigned Unit = *Units;
294 LiveRange *LR = RegUnitRanges[Unit];
296 LR = RegUnitRanges[Unit] = new LiveRange();
297 NewRanges.push_back(Unit);
299 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
301 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
304 DEBUG(dbgs() << '\n');
306 DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
308 // Compute the 'normal' part of the ranges.
309 for (unsigned i = 0, e = NewRanges.size(); i != e; ++i) {
310 unsigned Unit = NewRanges[i];
311 computeRegUnitRange(*RegUnitRanges[Unit], Unit);
316 static void createSegmentsForValues(LiveRange &LR,
317 iterator_range<LiveInterval::vni_iterator> VNIs) {
318 for (auto VNI : VNIs) {
321 SlotIndex Def = VNI->def;
322 LR.addSegment(LiveRange::Segment(Def, Def.getDeadSlot(), VNI));
326 typedef SmallVector<std::pair<SlotIndex, VNInfo*>, 16> ShrinkToUsesWorkList;
328 static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
329 ShrinkToUsesWorkList &WorkList,
330 const LiveRange &OldRange) {
331 // Keep track of the PHIs that are in use.
332 SmallPtrSet<VNInfo*, 8> UsedPHIs;
333 // Blocks that have already been added to WorkList as live-out.
334 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
336 // Extend intervals to reach all uses in WorkList.
337 while (!WorkList.empty()) {
338 SlotIndex Idx = WorkList.back().first;
339 VNInfo *VNI = WorkList.back().second;
341 const MachineBasicBlock *MBB = Indexes.getMBBFromIndex(Idx.getPrevSlot());
342 SlotIndex BlockStart = Indexes.getMBBStartIdx(MBB);
344 // Extend the live range for VNI to be live at Idx.
345 if (VNInfo *ExtVNI = LR.extendInBlock(BlockStart, Idx)) {
346 assert(ExtVNI == VNI && "Unexpected existing value number");
348 // Is this a PHIDef we haven't seen before?
349 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
350 !UsedPHIs.insert(VNI).second)
352 // The PHI is live, make sure the predecessors are live-out.
353 for (auto &Pred : MBB->predecessors()) {
354 if (!LiveOut.insert(Pred).second)
356 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
357 // A predecessor is not required to have a live-out value for a PHI.
358 if (VNInfo *PVNI = OldRange.getVNInfoBefore(Stop))
359 WorkList.push_back(std::make_pair(Stop, PVNI));
364 // VNI is live-in to MBB.
365 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
366 LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
368 // Make sure VNI is live-out from the predecessors.
369 for (auto &Pred : MBB->predecessors()) {
370 if (!LiveOut.insert(Pred).second)
372 SlotIndex Stop = Indexes.getMBBEndIdx(Pred);
373 assert(OldRange.getVNInfoBefore(Stop) == VNI &&
374 "Wrong value out of predecessor");
375 WorkList.push_back(std::make_pair(Stop, VNI));
380 /// shrinkToUses - After removing some uses of a register, shrink its live
381 /// range to just the remaining uses. This method does not compute reaching
382 /// defs for new uses, and it doesn't remove dead defs.
383 bool LiveIntervals::shrinkToUses(LiveInterval *li,
384 SmallVectorImpl<MachineInstr*> *dead) {
385 DEBUG(dbgs() << "Shrink: " << *li << '\n');
386 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
387 && "Can only shrink virtual registers");
389 // Shrink subregister live ranges.
390 for (LiveInterval::SubRange &S : li->subranges()) {
391 shrinkToUses(S, li->reg);
394 // Find all the values used, including PHI kills.
395 ShrinkToUsesWorkList WorkList;
397 // Visit all instructions reading li->reg.
398 for (MachineRegisterInfo::reg_instr_iterator
399 I = MRI->reg_instr_begin(li->reg), E = MRI->reg_instr_end();
401 MachineInstr *UseMI = &*(I++);
402 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
404 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
405 LiveQueryResult LRQ = li->Query(Idx);
406 VNInfo *VNI = LRQ.valueIn();
408 // This shouldn't happen: readsVirtualRegister returns true, but there is
409 // no live value. It is likely caused by a target getting <undef> flags
411 DEBUG(dbgs() << Idx << '\t' << *UseMI
412 << "Warning: Instr claims to read non-existent value in "
416 // Special case: An early-clobber tied operand reads and writes the
417 // register one slot early.
418 if (VNInfo *DefVNI = LRQ.valueDefined())
421 WorkList.push_back(std::make_pair(Idx, VNI));
424 // Create new live ranges with only minimal live segments per def.
426 createSegmentsForValues(NewLR, make_range(li->vni_begin(), li->vni_end()));
427 extendSegmentsToUses(NewLR, *Indexes, WorkList, *li);
429 // Handle dead values.
431 computeDeadValues(NewLR, *li, &CanSeparate, li->reg, dead);
433 // Move the trimmed segments back.
434 li->segments.swap(NewLR.segments);
435 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
439 void LiveIntervals::computeDeadValues(LiveRange &Segments, LiveRange &LR,
440 bool *CanSeparateRes, unsigned Reg,
441 SmallVectorImpl<MachineInstr*> *dead) {
442 bool CanSeparate = false;
443 for (auto VNI : LR.valnos) {
446 LiveRange::iterator LRI = Segments.FindSegmentContaining(VNI->def);
447 assert(LRI != Segments.end() && "Missing segment for PHI");
448 if (LRI->end != VNI->def.getDeadSlot())
450 if (VNI->isPHIDef()) {
451 // This is a dead PHI. Remove it.
453 Segments.removeSegment(LRI->start, LRI->end);
454 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
456 } else if (dead != nullptr) {
457 // This is a dead def. Make sure the instruction knows.
458 MachineInstr *MI = getInstructionFromIndex(VNI->def);
459 assert(MI && "No instruction defining live value");
460 MI->addRegisterDead(Reg, TRI);
461 if (dead && MI->allDefsAreDead()) {
462 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
467 if (CanSeparateRes != nullptr)
468 *CanSeparateRes = CanSeparate;
471 bool LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg)
473 DEBUG(dbgs() << "Shrink: " << SR << '\n');
474 assert(TargetRegisterInfo::isVirtualRegister(Reg)
475 && "Can only shrink virtual registers");
476 // Find all the values used, including PHI kills.
477 ShrinkToUsesWorkList WorkList;
479 // Visit all instructions reading Reg.
481 for (MachineOperand &MO : MRI->reg_operands(Reg)) {
482 MachineInstr *UseMI = MO.getParent();
483 if (UseMI->isDebugValue())
485 // Maybe the operand is for a subregister we don't care about.
486 unsigned SubReg = MO.getSubReg();
488 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg);
489 if ((SubRegMask & SR.LaneMask) == 0)
492 // We only need to visit each instruction once.
493 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
498 LiveQueryResult LRQ = SR.Query(Idx);
499 VNInfo *VNI = LRQ.valueIn();
500 // For Subranges it is possible that only undef values are left in that
501 // part of the subregister, so there is no real liverange at the use
505 // Special case: An early-clobber tied operand reads and writes the
506 // register one slot early.
507 if (VNInfo *DefVNI = LRQ.valueDefined())
510 WorkList.push_back(std::make_pair(Idx, VNI));
513 // Create a new live ranges with only minimal live segments per def.
515 createSegmentsForValues(NewLR, make_range(SR.vni_begin(), SR.vni_end()));
516 extendSegmentsToUses(NewLR, *Indexes, WorkList, SR);
518 // Handle dead values.
520 computeDeadValues(NewLR, SR, &CanSeparate);
522 // Move the trimmed ranges back.
523 SR.segments.swap(NewLR.segments);
524 DEBUG(dbgs() << "Shrunk: " << SR << '\n');
528 void LiveIntervals::extendToIndices(LiveRange &LR,
529 ArrayRef<SlotIndex> Indices) {
530 assert(LRCalc && "LRCalc not initialized.");
531 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
532 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
533 LRCalc->extend(LR, Indices[i]);
536 void LiveIntervals::pruneValue(LiveRange &LR, SlotIndex Kill,
537 SmallVectorImpl<SlotIndex> *EndPoints) {
538 LiveQueryResult LRQ = LR.Query(Kill);
539 VNInfo *VNI = LRQ.valueOutOrDead();
543 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
544 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
546 // If VNI isn't live out from KillMBB, the value is trivially pruned.
547 if (LRQ.endPoint() < MBBEnd) {
548 LR.removeSegment(Kill, LRQ.endPoint());
549 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
553 // VNI is live out of KillMBB.
554 LR.removeSegment(Kill, MBBEnd);
555 if (EndPoints) EndPoints->push_back(MBBEnd);
557 // Find all blocks that are reachable from KillMBB without leaving VNI's live
558 // range. It is possible that KillMBB itself is reachable, so start a DFS
559 // from each successor.
560 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
562 for (MachineBasicBlock::succ_iterator
563 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
564 SuccI != SuccE; ++SuccI) {
565 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
566 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
568 MachineBasicBlock *MBB = *I;
570 // Check if VNI is live in to MBB.
571 SlotIndex MBBStart, MBBEnd;
572 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
573 LiveQueryResult LRQ = LR.Query(MBBStart);
574 if (LRQ.valueIn() != VNI) {
575 // This block isn't part of the VNI segment. Prune the search.
580 // Prune the search if VNI is killed in MBB.
581 if (LRQ.endPoint() < MBBEnd) {
582 LR.removeSegment(MBBStart, LRQ.endPoint());
583 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
588 // VNI is live through MBB.
589 LR.removeSegment(MBBStart, MBBEnd);
590 if (EndPoints) EndPoints->push_back(MBBEnd);
596 void LiveIntervals::pruneValue(LiveInterval &LI, SlotIndex Kill,
597 SmallVectorImpl<SlotIndex> *EndPoints) {
598 pruneValue((LiveRange&)LI, Kill, EndPoints);
600 for (LiveInterval::SubRange &SR : LI.subranges()) {
601 pruneValue(SR, Kill, nullptr);
605 //===----------------------------------------------------------------------===//
606 // Register allocator hooks.
609 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
610 // Keep track of regunit ranges.
611 SmallVector<std::pair<LiveRange*, LiveRange::iterator>, 8> RU;
613 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
614 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
615 if (MRI->reg_nodbg_empty(Reg))
617 LiveInterval *LI = &getInterval(Reg);
621 // Find the regunit intervals for the assigned register. They may overlap
622 // the virtual register live range, cancelling any kills.
624 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
626 LiveRange &RURanges = getRegUnit(*Units);
627 if (RURanges.empty())
629 RU.push_back(std::make_pair(&RURanges, RURanges.find(LI->begin()->end)));
632 // Every instruction that kills Reg corresponds to a segment range end
634 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
636 // A block index indicates an MBB edge.
637 if (RI->end.isBlock())
639 MachineInstr *MI = getInstructionFromIndex(RI->end);
643 // Check if any of the regunits are live beyond the end of RI. That could
644 // happen when a physreg is defined as a copy of a virtreg:
646 // %EAX = COPY %vreg5
647 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
650 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
651 bool CancelKill = false;
652 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
653 LiveRange &RRanges = *RU[u].first;
654 LiveRange::iterator &I = RU[u].second;
655 if (I == RRanges.end())
657 I = RRanges.advanceTo(I, RI->end);
658 if (I == RRanges.end() || I->start >= RI->end)
660 // I is overlapping RI.
665 // If an instruction writes to a subregister, a new segment starts in the
666 // LiveInterval. In this case adding Kill-Flags is incorrect if no
667 // super registers defs/uses are appended to the instruction which is
668 // what we do when subregister liveness tracking is enabled.
669 if (MRI->tracksSubRegLiveness()) {
670 // Next segment has to be adjacent in the subregister write case.
671 LiveRange::iterator N = std::next(RI);
672 if (N != LI->end() && N->start == RI->end) {
673 // See if we have a partial write operand
674 bool IsFullWrite = false;
675 for (MachineInstr::const_mop_iterator MOp = MI->operands_begin(),
676 MOpE = MI->operands_end(); MOp != MOpE; ++MOp) {
677 if (MOp->isReg() && !MOp->isDef() && MOp->getReg() == Reg
678 && MOp->getSubReg() == 0) {
689 MI->clearRegisterKills(Reg, nullptr);
691 MI->addRegisterKilled(Reg, nullptr);
697 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
698 // A local live range must be fully contained inside the block, meaning it is
699 // defined and killed at instructions, not at block boundaries. It is not
700 // live in or or out of any block.
702 // It is technically possible to have a PHI-defined live range identical to a
703 // single block, but we are going to return false in that case.
705 SlotIndex Start = LI.beginIndex();
709 SlotIndex Stop = LI.endIndex();
713 // getMBBFromIndex doesn't need to search the MBB table when both indexes
714 // belong to proper instructions.
715 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
716 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
717 return MBB1 == MBB2 ? MBB1 : nullptr;
721 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
722 for (const VNInfo *PHI : LI.valnos) {
723 if (PHI->isUnused() || !PHI->isPHIDef())
725 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
726 // Conservatively return true instead of scanning huge predecessor lists.
727 if (PHIMBB->pred_size() > 100)
729 for (MachineBasicBlock::const_pred_iterator
730 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
731 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
738 LiveIntervals::getSpillWeight(bool isDef, bool isUse,
739 const MachineBlockFrequencyInfo *MBFI,
740 const MachineInstr *MI) {
741 BlockFrequency Freq = MBFI->getBlockFreq(MI->getParent());
742 const float Scale = 1.0f / MBFI->getEntryFreq();
743 return (isDef + isUse) * (Freq.getFrequency() * Scale);
747 LiveIntervals::addSegmentToEndOfBlock(unsigned reg, MachineInstr* startInst) {
748 LiveInterval& Interval = createEmptyInterval(reg);
749 VNInfo* VN = Interval.getNextValue(
750 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
751 getVNInfoAllocator());
752 LiveRange::Segment S(
753 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
754 getMBBEndIdx(startInst->getParent()), VN);
755 Interval.addSegment(S);
761 //===----------------------------------------------------------------------===//
762 // Register mask functions
763 //===----------------------------------------------------------------------===//
765 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
766 BitVector &UsableRegs) {
769 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
771 // Use a smaller arrays for local live ranges.
772 ArrayRef<SlotIndex> Slots;
773 ArrayRef<const uint32_t*> Bits;
774 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
775 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
776 Bits = getRegMaskBitsInBlock(MBB->getNumber());
778 Slots = getRegMaskSlots();
779 Bits = getRegMaskBits();
782 // We are going to enumerate all the register mask slots contained in LI.
783 // Start with a binary search of RegMaskSlots to find a starting point.
784 ArrayRef<SlotIndex>::iterator SlotI =
785 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
786 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
788 // No slots in range, LI begins after the last call.
794 assert(*SlotI >= LiveI->start);
795 // Loop over all slots overlapping this segment.
796 while (*SlotI < LiveI->end) {
797 // *SlotI overlaps LI. Collect mask bits.
799 // This is the first overlap. Initialize UsableRegs to all ones.
801 UsableRegs.resize(TRI->getNumRegs(), true);
804 // Remove usable registers clobbered by this mask.
805 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
806 if (++SlotI == SlotE)
809 // *SlotI is beyond the current LI segment.
810 LiveI = LI.advanceTo(LiveI, *SlotI);
813 // Advance SlotI until it overlaps.
814 while (*SlotI < LiveI->start)
815 if (++SlotI == SlotE)
820 //===----------------------------------------------------------------------===//
821 // IntervalUpdate class.
822 //===----------------------------------------------------------------------===//
824 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
825 class LiveIntervals::HMEditor {
828 const MachineRegisterInfo& MRI;
829 const TargetRegisterInfo& TRI;
832 SmallPtrSet<LiveRange*, 8> Updated;
836 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
837 const TargetRegisterInfo& TRI,
838 SlotIndex OldIdx, SlotIndex NewIdx, bool UpdateFlags)
839 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx),
840 UpdateFlags(UpdateFlags) {}
842 // FIXME: UpdateFlags is a workaround that creates live intervals for all
843 // physregs, even those that aren't needed for regalloc, in order to update
844 // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
845 // flags, and postRA passes will use a live register utility instead.
846 LiveRange *getRegUnitLI(unsigned Unit) {
848 return &LIS.getRegUnit(Unit);
849 return LIS.getCachedRegUnit(Unit);
852 /// Update all live ranges touched by MI, assuming a move from OldIdx to
854 void updateAllRanges(MachineInstr *MI) {
855 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
856 bool hasRegMask = false;
857 for (MIOperands MO(MI); MO.isValid(); ++MO) {
862 // Aggressively clear all kill flags.
863 // They are reinserted by VirtRegRewriter.
865 MO->setIsKill(false);
867 unsigned Reg = MO->getReg();
870 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
871 LiveInterval &LI = LIS.getInterval(Reg);
872 if (LI.hasSubRanges()) {
873 unsigned SubReg = MO->getSubReg();
874 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
875 for (LiveInterval::SubRange &S : LI.subranges()) {
876 if ((S.LaneMask & LaneMask) == 0)
878 updateRange(S, Reg, S.LaneMask);
881 updateRange(LI, Reg, 0);
885 // For physregs, only update the regunits that actually have a
886 // precomputed live range.
887 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
888 if (LiveRange *LR = getRegUnitLI(*Units))
889 updateRange(*LR, *Units, 0);
892 updateRegMaskSlots();
896 /// Update a single live range, assuming an instruction has been moved from
897 /// OldIdx to NewIdx.
898 void updateRange(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
899 if (!Updated.insert(&LR).second)
903 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
904 dbgs() << PrintReg(Reg);
906 dbgs() << format(" L%04X", LaneMask);
908 dbgs() << PrintRegUnit(Reg, &TRI);
910 dbgs() << ":\t" << LR << '\n';
912 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
915 handleMoveUp(LR, Reg, LaneMask);
916 DEBUG(dbgs() << " -->\t" << LR << '\n');
920 /// Update LR to reflect an instruction has been moved downwards from OldIdx
923 /// 1. Live def at OldIdx:
924 /// Move def to NewIdx, assert endpoint after NewIdx.
926 /// 2. Live def at OldIdx, killed at NewIdx:
927 /// Change to dead def at NewIdx.
928 /// (Happens when bundling def+kill together).
930 /// 3. Dead def at OldIdx:
931 /// Move def to NewIdx, possibly across another live value.
933 /// 4. Def at OldIdx AND at NewIdx:
934 /// Remove segment [OldIdx;NewIdx) and value defined at OldIdx.
935 /// (Happens when bundling multiple defs together).
937 /// 5. Value read at OldIdx, killed before NewIdx:
938 /// Extend kill to NewIdx.
940 void handleMoveDown(LiveRange &LR) {
941 // First look for a kill at OldIdx.
942 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
943 LiveRange::iterator E = LR.end();
944 // Is LR even live at OldIdx?
945 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
948 // Handle a live-in value.
949 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
950 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
951 // If the live-in value already extends to NewIdx, there is nothing to do.
952 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
954 // Aggressively remove all kill flags from the old kill point.
955 // Kill flags shouldn't be used while live intervals exist, they will be
956 // reinserted by VirtRegRewriter.
957 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
958 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
959 if (MO->isReg() && MO->isUse())
960 MO->setIsKill(false);
961 // Adjust I->end to reach NewIdx. This may temporarily make LR invalid by
962 // overlapping ranges. Case 5 above.
963 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
964 // If this was a kill, there may also be a def. Otherwise we're done.
970 // Check for a def at OldIdx.
971 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
973 // We have a def at OldIdx.
974 VNInfo *DefVNI = I->valno;
975 assert(DefVNI->def == I->start && "Inconsistent def");
976 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
977 // If the defined value extends beyond NewIdx, just move the def down.
978 // This is case 1 above.
979 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
980 I->start = DefVNI->def;
983 // The remaining possibilities are now:
984 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
985 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
986 // In either case, it is possible that there is an existing def at NewIdx.
987 assert((I->end == OldIdx.getDeadSlot() ||
988 SlotIndex::isSameInstr(I->end, NewIdx)) &&
989 "Cannot move def below kill");
990 LiveRange::iterator NewI = LR.advanceTo(I, NewIdx.getRegSlot());
991 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
992 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
993 // coalesced into that value.
994 assert(NewI->valno != DefVNI && "Multiple defs of value?");
995 LR.removeValNo(DefVNI);
998 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
999 // If the def at OldIdx was dead, we allow it to be moved across other LR
1000 // values. The new range should be placed immediately before NewI, move any
1001 // intermediate ranges up.
1002 assert(NewI != I && "Inconsistent iterators");
1003 std::copy(std::next(I), NewI, I);
1005 = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1008 /// Update LR to reflect an instruction has been moved upwards from OldIdx
1011 /// 1. Live def at OldIdx:
1012 /// Hoist def to NewIdx.
1014 /// 2. Dead def at OldIdx:
1015 /// Hoist def+end to NewIdx, possibly move across other values.
1017 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1018 /// Remove value defined at OldIdx, coalescing it with existing value.
1020 /// 4. Live def at OldIdx AND existing def at NewIdx:
1021 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1022 /// (Happens when bundling multiple defs together).
1024 /// 5. Value killed at OldIdx:
1025 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1028 void handleMoveUp(LiveRange &LR, unsigned Reg, unsigned LaneMask) {
1029 // First look for a kill at OldIdx.
1030 LiveRange::iterator I = LR.find(OldIdx.getBaseIndex());
1031 LiveRange::iterator E = LR.end();
1032 // Is LR even live at OldIdx?
1033 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1036 // Handle a live-in value.
1037 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1038 // If the live-in value isn't killed here, there is nothing to do.
1039 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1041 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1042 // another use, we need to search for that use. Case 5 above.
1043 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1045 // If OldIdx also defines a value, there couldn't have been another use.
1046 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1047 // No def, search for the new kill.
1048 // This can never be an early clobber kill since there is no def.
1049 std::prev(I)->end = findLastUseBefore(Reg, LaneMask).getRegSlot();
1054 // Now deal with the def at OldIdx.
1055 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1056 VNInfo *DefVNI = I->valno;
1057 assert(DefVNI->def == I->start && "Inconsistent def");
1058 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1060 // Check for an existing def at NewIdx.
1061 LiveRange::iterator NewI = LR.find(NewIdx.getRegSlot());
1062 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1063 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1064 // There is an existing def at NewIdx.
1065 if (I->end.isDead()) {
1066 // Case 3: Remove the dead def at OldIdx.
1067 LR.removeValNo(DefVNI);
1070 // Case 4: Replace def at NewIdx with live def at OldIdx.
1071 I->start = DefVNI->def;
1072 LR.removeValNo(NewI->valno);
1076 // There is no existing def at NewIdx. Hoist DefVNI.
1077 if (!I->end.isDead()) {
1078 // Leave the end point of a live def.
1079 I->start = DefVNI->def;
1083 // DefVNI is a dead def. It may have been moved across other values in LR,
1084 // so move I up to NewI. Slide [NewI;I) down one position.
1085 std::copy_backward(NewI, I, std::next(I));
1086 *NewI = LiveRange::Segment(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1089 void updateRegMaskSlots() {
1090 SmallVectorImpl<SlotIndex>::iterator RI =
1091 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1093 assert(RI != LIS.RegMaskSlots.end() && *RI == OldIdx.getRegSlot() &&
1094 "No RegMask at OldIdx.");
1095 *RI = NewIdx.getRegSlot();
1096 assert((RI == LIS.RegMaskSlots.begin() ||
1097 SlotIndex::isEarlierInstr(*std::prev(RI), *RI)) &&
1098 "Cannot move regmask instruction above another call");
1099 assert((std::next(RI) == LIS.RegMaskSlots.end() ||
1100 SlotIndex::isEarlierInstr(*RI, *std::next(RI))) &&
1101 "Cannot move regmask instruction below another call");
1104 // Return the last use of reg between NewIdx and OldIdx.
1105 SlotIndex findLastUseBefore(unsigned Reg, unsigned LaneMask) {
1107 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1108 SlotIndex LastUse = NewIdx;
1109 for (MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
1110 unsigned SubReg = MO.getSubReg();
1111 if (SubReg != 0 && LaneMask != 0
1112 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0)
1115 const MachineInstr *MI = MO.getParent();
1116 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1117 if (InstSlot > LastUse && InstSlot < OldIdx)
1123 // This is a regunit interval, so scanning the use list could be very
1124 // expensive. Scan upwards from OldIdx instead.
1125 assert(NewIdx < OldIdx && "Expected upwards move");
1126 SlotIndexes *Indexes = LIS.getSlotIndexes();
1127 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(NewIdx);
1129 // OldIdx may not correspond to an instruction any longer, so set MII to
1130 // point to the next instruction after OldIdx, or MBB->end().
1131 MachineBasicBlock::iterator MII = MBB->end();
1132 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1133 Indexes->getNextNonNullIndex(OldIdx)))
1134 if (MI->getParent() == MBB)
1137 MachineBasicBlock::iterator Begin = MBB->begin();
1138 while (MII != Begin) {
1139 if ((--MII)->isDebugValue())
1141 SlotIndex Idx = Indexes->getInstructionIndex(MII);
1143 // Stop searching when NewIdx is reached.
1144 if (!SlotIndex::isEarlierInstr(NewIdx, Idx))
1147 // Check if MII uses Reg.
1148 for (MIBundleOperands MO(MII); MO.isValid(); ++MO)
1150 TargetRegisterInfo::isPhysicalRegister(MO->getReg()) &&
1151 TRI.hasRegUnit(MO->getReg(), Reg))
1154 // Didn't reach NewIdx. It must be the first instruction in the block.
1159 void LiveIntervals::handleMove(MachineInstr* MI, bool UpdateFlags) {
1160 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1161 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1162 Indexes->removeMachineInstrFromMaps(MI);
1163 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1164 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1165 OldIndex < getMBBEndIdx(MI->getParent()) &&
1166 "Cannot handle moves across basic block boundaries.");
1168 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1169 HME.updateAllRanges(MI);
1172 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1173 MachineInstr* BundleStart,
1175 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1176 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1177 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex, UpdateFlags);
1178 HME.updateAllRanges(MI);
1181 void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
1182 const MachineBasicBlock::iterator End,
1183 const SlotIndex endIdx,
1184 LiveRange &LR, const unsigned Reg,
1185 const unsigned LaneMask) {
1186 LiveInterval::iterator LII = LR.find(endIdx);
1187 SlotIndex lastUseIdx;
1188 if (LII != LR.end() && LII->start < endIdx)
1189 lastUseIdx = LII->end;
1193 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1195 MachineInstr *MI = I;
1196 if (MI->isDebugValue())
1199 SlotIndex instrIdx = getInstructionIndex(MI);
1200 bool isStartValid = getInstructionFromIndex(LII->start);
1201 bool isEndValid = getInstructionFromIndex(LII->end);
1203 // FIXME: This doesn't currently handle early-clobber or multiple removed
1204 // defs inside of the region to repair.
1205 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
1206 OE = MI->operands_end(); OI != OE; ++OI) {
1207 const MachineOperand &MO = *OI;
1208 if (!MO.isReg() || MO.getReg() != Reg)
1211 unsigned SubReg = MO.getSubReg();
1212 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg);
1213 if ((Mask & LaneMask) == 0)
1217 if (!isStartValid) {
1218 if (LII->end.isDead()) {
1219 SlotIndex prevStart;
1220 if (LII != LR.begin())
1221 prevStart = std::prev(LII)->start;
1223 // FIXME: This could be more efficient if there was a
1224 // removeSegment method that returned an iterator.
1225 LR.removeSegment(*LII, true);
1226 if (prevStart.isValid())
1227 LII = LR.find(prevStart);
1231 LII->start = instrIdx.getRegSlot();
1232 LII->valno->def = instrIdx.getRegSlot();
1233 if (MO.getSubReg() && !MO.isUndef())
1234 lastUseIdx = instrIdx.getRegSlot();
1236 lastUseIdx = SlotIndex();
1241 if (!lastUseIdx.isValid()) {
1242 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1243 LiveRange::Segment S(instrIdx.getRegSlot(),
1244 instrIdx.getDeadSlot(), VNI);
1245 LII = LR.addSegment(S);
1246 } else if (LII->start != instrIdx.getRegSlot()) {
1247 VNInfo *VNI = LR.getNextValue(instrIdx.getRegSlot(), VNInfoAllocator);
1248 LiveRange::Segment S(instrIdx.getRegSlot(), lastUseIdx, VNI);
1249 LII = LR.addSegment(S);
1252 if (MO.getSubReg() && !MO.isUndef())
1253 lastUseIdx = instrIdx.getRegSlot();
1255 lastUseIdx = SlotIndex();
1256 } else if (MO.isUse()) {
1257 // FIXME: This should probably be handled outside of this branch,
1258 // either as part of the def case (for defs inside of the region) or
1259 // after the loop over the region.
1260 if (!isEndValid && !LII->end.isBlock())
1261 LII->end = instrIdx.getRegSlot();
1262 if (!lastUseIdx.isValid())
1263 lastUseIdx = instrIdx.getRegSlot();
1270 LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
1271 MachineBasicBlock::iterator Begin,
1272 MachineBasicBlock::iterator End,
1273 ArrayRef<unsigned> OrigRegs) {
1274 // Find anchor points, which are at the beginning/end of blocks or at
1275 // instructions that already have indexes.
1276 while (Begin != MBB->begin() && !Indexes->hasIndex(Begin))
1278 while (End != MBB->end() && !Indexes->hasIndex(End))
1282 if (End == MBB->end())
1283 endIdx = getMBBEndIdx(MBB).getPrevSlot();
1285 endIdx = getInstructionIndex(End);
1287 Indexes->repairIndexesInRange(MBB, Begin, End);
1289 for (MachineBasicBlock::iterator I = End; I != Begin;) {
1291 MachineInstr *MI = I;
1292 if (MI->isDebugValue())
1294 for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
1295 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
1297 TargetRegisterInfo::isVirtualRegister(MOI->getReg()) &&
1298 !hasInterval(MOI->getReg())) {
1299 createAndComputeVirtRegInterval(MOI->getReg());
1304 for (unsigned i = 0, e = OrigRegs.size(); i != e; ++i) {
1305 unsigned Reg = OrigRegs[i];
1306 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1309 LiveInterval &LI = getInterval(Reg);
1310 // FIXME: Should we support undefs that gain defs?
1311 if (!LI.hasAtLeastOneValue())
1314 for (LiveInterval::SubRange &S : LI.subranges()) {
1315 repairOldRegInRange(Begin, End, endIdx, S, Reg, S.LaneMask);
1317 repairOldRegInRange(Begin, End, endIdx, LI, Reg);