1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/DenseSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "LiveRangeCalc.h"
42 STATISTIC(numIntervals , "Number of original intervals");
44 char LiveIntervals::ID = 0;
45 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
46 "Live Interval Analysis", false, false)
47 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
48 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
49 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
50 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
51 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
52 "Live Interval Analysis", false, false)
54 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
56 AU.addRequired<AliasAnalysis>();
57 AU.addPreserved<AliasAnalysis>();
58 AU.addRequired<LiveVariables>();
59 AU.addPreserved<LiveVariables>();
60 AU.addPreservedID(MachineLoopInfoID);
61 AU.addRequiredTransitiveID(MachineDominatorsID);
62 AU.addPreservedID(MachineDominatorsID);
63 AU.addPreserved<SlotIndexes>();
64 AU.addRequiredTransitive<SlotIndexes>();
65 MachineFunctionPass::getAnalysisUsage(AU);
68 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
69 DomTree(0), LRCalc(0) {
70 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
73 LiveIntervals::~LiveIntervals() {
77 void LiveIntervals::releaseMemory() {
78 // Free the live intervals themselves.
79 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
80 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
81 VirtRegIntervals.clear();
84 RegMaskBlocks.clear();
86 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
87 delete RegUnitIntervals[i];
88 RegUnitIntervals.clear();
90 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
91 VNInfoAllocator.Reset();
94 /// runOnMachineFunction - Register allocate the whole function
96 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
98 MRI = &MF->getRegInfo();
100 TRI = TM->getRegisterInfo();
101 TII = TM->getInstrInfo();
102 AA = &getAnalysis<AliasAnalysis>();
103 LV = &getAnalysis<LiveVariables>();
104 Indexes = &getAnalysis<SlotIndexes>();
105 DomTree = &getAnalysis<MachineDominatorTree>();
107 LRCalc = new LiveRangeCalc();
108 AllocatableRegs = TRI->getAllocatableSet(fn);
109 ReservedRegs = TRI->getReservedRegs(fn);
113 numIntervals += getNumIntervals();
115 computeLiveInRegUnits();
121 /// print - Implement the dump method.
122 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
123 OS << "********** INTERVALS **********\n";
125 // Dump the regunits.
126 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
127 if (LiveInterval *LI = RegUnitIntervals[i])
128 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
130 // Dump the virtregs.
131 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
132 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
133 if (hasInterval(Reg))
134 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
140 void LiveIntervals::printInstrs(raw_ostream &OS) const {
141 OS << "********** MACHINEINSTRS **********\n";
142 MF->print(OS, Indexes);
145 void LiveIntervals::dumpInstrs() const {
150 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
151 unsigned Reg = MI.getOperand(MOIdx).getReg();
152 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
153 const MachineOperand &MO = MI.getOperand(i);
156 if (MO.getReg() == Reg && MO.isDef()) {
157 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
158 MI.getOperand(MOIdx).getSubReg() &&
159 (MO.getSubReg() || MO.isImplicit()));
166 /// isPartialRedef - Return true if the specified def at the specific index is
167 /// partially re-defining the specified live interval. A common case of this is
168 /// a definition of the sub-register.
169 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
170 LiveInterval &interval) {
171 if (!MO.getSubReg() || MO.isEarlyClobber())
174 SlotIndex RedefIndex = MIIdx.getRegSlot();
175 const LiveRange *OldLR =
176 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
177 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
179 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
184 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
185 MachineBasicBlock::iterator mi,
189 LiveInterval &interval) {
190 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
192 // Virtual registers may be defined multiple times (due to phi
193 // elimination and 2-addr elimination). Much of what we do only has to be
194 // done once for the vreg. We use an empty interval to detect the first
195 // time we see a vreg.
196 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
197 if (interval.empty()) {
198 // Get the Idx of the defining instructions.
199 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
201 // Make sure the first definition is not a partial redefinition.
202 assert(!MO.readsReg() && "First def cannot also read virtual register "
203 "missing <undef> flag?");
205 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
206 assert(ValNo->id == 0 && "First value in interval is not 0?");
208 // Loop over all of the blocks that the vreg is defined in. There are
209 // two cases we have to handle here. The most common case is a vreg
210 // whose lifetime is contained within a basic block. In this case there
211 // will be a single kill, in MBB, which comes after the definition.
212 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
213 // FIXME: what about dead vars?
215 if (vi.Kills[0] != mi)
216 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
218 killIdx = defIndex.getDeadSlot();
220 // If the kill happens after the definition, we have an intra-block
222 if (killIdx > defIndex) {
223 assert(vi.AliveBlocks.empty() &&
224 "Shouldn't be alive across any blocks!");
225 LiveRange LR(defIndex, killIdx, ValNo);
226 interval.addRange(LR);
227 DEBUG(dbgs() << " +" << LR << "\n");
232 // The other case we handle is when a virtual register lives to the end
233 // of the defining block, potentially live across some blocks, then is
234 // live into some number of blocks, but gets killed. Start by adding a
235 // range that goes from this definition to the end of the defining block.
236 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
237 DEBUG(dbgs() << " +" << NewLR);
238 interval.addRange(NewLR);
240 bool PHIJoin = LV->isPHIJoin(interval.reg);
243 // A phi join register is killed at the end of the MBB and revived as a
244 // new valno in the killing blocks.
245 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
246 DEBUG(dbgs() << " phi-join");
247 ValNo->setHasPHIKill(true);
249 // Iterate over all of the blocks that the variable is completely
250 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
252 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
253 E = vi.AliveBlocks.end(); I != E; ++I) {
254 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
255 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
257 interval.addRange(LR);
258 DEBUG(dbgs() << " +" << LR);
262 // Finally, this virtual register is live from the start of any killing
263 // block to the 'use' slot of the killing instruction.
264 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
265 MachineInstr *Kill = vi.Kills[i];
266 SlotIndex Start = getMBBStartIdx(Kill->getParent());
267 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
269 // Create interval with one of a NEW value number. Note that this value
270 // number isn't actually defined by an instruction, weird huh? :)
272 assert(getInstructionFromIndex(Start) == 0 &&
273 "PHI def index points at actual instruction.");
274 ValNo = interval.getNextValue(Start, VNInfoAllocator);
275 ValNo->setIsPHIDef(true);
277 LiveRange LR(Start, killIdx, ValNo);
278 interval.addRange(LR);
279 DEBUG(dbgs() << " +" << LR);
283 if (MultipleDefsBySameMI(*mi, MOIdx))
284 // Multiple defs of the same virtual register by the same instruction.
285 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
286 // This is likely due to elimination of REG_SEQUENCE instructions. Return
287 // here since there is nothing to do.
290 // If this is the second time we see a virtual register definition, it
291 // must be due to phi elimination or two addr elimination. If this is
292 // the result of two address elimination, then the vreg is one of the
293 // def-and-use register operand.
295 // It may also be partial redef like this:
296 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
297 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
298 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
299 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
300 // If this is a two-address definition, then we have already processed
301 // the live range. The only problem is that we didn't realize there
302 // are actually two values in the live interval. Because of this we
303 // need to take the LiveRegion that defines this register and split it
305 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
307 const LiveRange *OldLR =
308 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
309 VNInfo *OldValNo = OldLR->valno;
310 SlotIndex DefIndex = OldValNo->def.getRegSlot();
312 // Delete the previous value, which should be short and continuous,
313 // because the 2-addr copy must be in the same MBB as the redef.
314 interval.removeRange(DefIndex, RedefIndex);
316 // The new value number (#1) is defined by the instruction we claimed
318 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
320 // Value#0 is now defined by the 2-addr instruction.
321 OldValNo->def = RedefIndex;
323 // Add the new live interval which replaces the range for the input copy.
324 LiveRange LR(DefIndex, RedefIndex, ValNo);
325 DEBUG(dbgs() << " replace range with " << LR);
326 interval.addRange(LR);
328 // If this redefinition is dead, we need to add a dummy unit live
329 // range covering the def slot.
331 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
334 DEBUG(dbgs() << " RESULT: " << interval);
335 } else if (LV->isPHIJoin(interval.reg)) {
336 // In the case of PHI elimination, each variable definition is only
337 // live until the end of the block. We've already taken care of the
338 // rest of the live range.
340 SlotIndex defIndex = MIIdx.getRegSlot();
341 if (MO.isEarlyClobber())
342 defIndex = MIIdx.getRegSlot(true);
344 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
346 SlotIndex killIndex = getMBBEndIdx(mbb);
347 LiveRange LR(defIndex, killIndex, ValNo);
348 interval.addRange(LR);
349 ValNo->setHasPHIKill(true);
350 DEBUG(dbgs() << " phi-join +" << LR);
352 llvm_unreachable("Multiply defined register");
356 DEBUG(dbgs() << '\n');
359 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
360 MachineBasicBlock::iterator MI,
364 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
365 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
366 getOrCreateInterval(MO.getReg()));
369 /// computeIntervals - computes the live intervals for virtual
370 /// registers. for some ordering of the machine instructions [1,N] a
371 /// live interval is an interval [i, j) where 1 <= i <= j < N for
372 /// which a variable is live
373 void LiveIntervals::computeIntervals() {
374 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
375 << "********** Function: "
376 << ((Value*)MF->getFunction())->getName() << '\n');
378 RegMaskBlocks.resize(MF->getNumBlockIDs());
380 SmallVector<unsigned, 8> UndefUses;
381 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
383 MachineBasicBlock *MBB = MBBI;
384 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
389 // Track the index of the current machine instr.
390 SlotIndex MIIndex = getMBBStartIdx(MBB);
391 DEBUG(dbgs() << "BB#" << MBB->getNumber()
392 << ":\t\t# derived from " << MBB->getName() << "\n");
394 // Skip over empty initial indices.
395 if (getInstructionFromIndex(MIIndex) == 0)
396 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
398 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
400 DEBUG(dbgs() << MIIndex << "\t" << *MI);
401 if (MI->isDebugValue())
403 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
404 "Lost SlotIndex synchronization");
407 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
408 MachineOperand &MO = MI->getOperand(i);
410 // Collect register masks.
411 if (MO.isRegMask()) {
412 RegMaskSlots.push_back(MIIndex.getRegSlot());
413 RegMaskBits.push_back(MO.getRegMask());
417 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
420 // handle register defs - build intervals
422 handleRegisterDef(MBB, MI, MIIndex, MO, i);
423 else if (MO.isUndef())
424 UndefUses.push_back(MO.getReg());
427 // Move to the next instr slot.
428 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
431 // Compute the number of register mask instructions in this block.
432 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
433 RMB.second = RegMaskSlots.size() - RMB.first;;
436 // Create empty intervals for registers defined by implicit_def's (except
437 // for those implicit_def that define values which are liveout of their
439 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
440 unsigned UndefReg = UndefUses[i];
441 (void)getOrCreateInterval(UndefReg);
445 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
446 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
447 return new LiveInterval(reg, Weight);
451 //===----------------------------------------------------------------------===//
452 // Register Unit Liveness
453 //===----------------------------------------------------------------------===//
455 // Fixed interference typically comes from ABI boundaries: Function arguments
456 // and return values are passed in fixed registers, and so are exception
457 // pointers entering landing pads. Certain instructions require values to be
458 // present in specific registers. That is also represented through fixed
462 /// computeRegUnitInterval - Compute the live interval of a register unit, based
463 /// on the uses and defs of aliasing registers. The interval should be empty,
464 /// or contain only dead phi-defs from ABI blocks.
465 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
466 unsigned Unit = LI->reg;
468 assert(LRCalc && "LRCalc not initialized.");
469 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
471 // The physregs aliasing Unit are the roots and their super-registers.
472 // Create all values as dead defs before extending to uses. Note that roots
473 // may share super-registers. That's OK because createDeadDefs() is
474 // idempotent. It is very rare for a register unit to have multiple roots, so
475 // uniquing super-registers is probably not worthwhile.
476 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
477 unsigned Root = *Roots;
478 if (!MRI->reg_empty(Root))
479 LRCalc->createDeadDefs(LI, Root);
480 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
481 if (!MRI->reg_empty(*Supers))
482 LRCalc->createDeadDefs(LI, *Supers);
486 // Now extend LI to reach all uses.
487 // Ignore uses of reserved registers. We only track defs of those.
488 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
489 unsigned Root = *Roots;
490 if (!isReserved(Root) && !MRI->reg_empty(Root))
491 LRCalc->extendToUses(LI, Root);
492 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
493 unsigned Reg = *Supers;
494 if (!isReserved(Reg) && !MRI->reg_empty(Reg))
495 LRCalc->extendToUses(LI, Reg);
501 /// computeLiveInRegUnits - Precompute the live ranges of any register units
502 /// that are live-in to an ABI block somewhere. Register values can appear
503 /// without a corresponding def when entering the entry block or a landing pad.
505 void LiveIntervals::computeLiveInRegUnits() {
506 RegUnitIntervals.resize(TRI->getNumRegUnits());
507 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
509 // Keep track of the intervals allocated.
510 SmallVector<LiveInterval*, 8> NewIntvs;
512 // Check all basic blocks for live-ins.
513 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
515 const MachineBasicBlock *MBB = MFI;
517 // We only care about ABI blocks: Entry + landing pads.
518 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
521 // Create phi-defs at Begin for all live-in registers.
522 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
523 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
524 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
525 LIE = MBB->livein_end(); LII != LIE; ++LII) {
526 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
527 unsigned Unit = *Units;
528 LiveInterval *Intv = RegUnitIntervals[Unit];
530 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
531 NewIntvs.push_back(Intv);
533 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
535 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
538 DEBUG(dbgs() << '\n');
540 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
542 // Compute the 'normal' part of the intervals.
543 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
544 computeRegUnitInterval(NewIntvs[i]);
548 /// shrinkToUses - After removing some uses of a register, shrink its live
549 /// range to just the remaining uses. This method does not compute reaching
550 /// defs for new uses, and it doesn't remove dead defs.
551 bool LiveIntervals::shrinkToUses(LiveInterval *li,
552 SmallVectorImpl<MachineInstr*> *dead) {
553 DEBUG(dbgs() << "Shrink: " << *li << '\n');
554 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
555 && "Can only shrink virtual registers");
556 // Find all the values used, including PHI kills.
557 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
559 // Blocks that have already been added to WorkList as live-out.
560 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
562 // Visit all instructions reading li->reg.
563 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
564 MachineInstr *UseMI = I.skipInstruction();) {
565 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
567 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
568 LiveRangeQuery LRQ(*li, Idx);
569 VNInfo *VNI = LRQ.valueIn();
571 // This shouldn't happen: readsVirtualRegister returns true, but there is
572 // no live value. It is likely caused by a target getting <undef> flags
574 DEBUG(dbgs() << Idx << '\t' << *UseMI
575 << "Warning: Instr claims to read non-existent value in "
579 // Special case: An early-clobber tied operand reads and writes the
580 // register one slot early.
581 if (VNInfo *DefVNI = LRQ.valueDefined())
584 WorkList.push_back(std::make_pair(Idx, VNI));
587 // Create a new live interval with only minimal live segments per def.
588 LiveInterval NewLI(li->reg, 0);
589 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
594 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
597 // Keep track of the PHIs that are in use.
598 SmallPtrSet<VNInfo*, 8> UsedPHIs;
600 // Extend intervals to reach all uses in WorkList.
601 while (!WorkList.empty()) {
602 SlotIndex Idx = WorkList.back().first;
603 VNInfo *VNI = WorkList.back().second;
605 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
606 SlotIndex BlockStart = getMBBStartIdx(MBB);
608 // Extend the live range for VNI to be live at Idx.
609 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
611 assert(ExtVNI == VNI && "Unexpected existing value number");
612 // Is this a PHIDef we haven't seen before?
613 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
615 // The PHI is live, make sure the predecessors are live-out.
616 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
617 PE = MBB->pred_end(); PI != PE; ++PI) {
618 if (!LiveOut.insert(*PI))
620 SlotIndex Stop = getMBBEndIdx(*PI);
621 // A predecessor is not required to have a live-out value for a PHI.
622 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
623 WorkList.push_back(std::make_pair(Stop, PVNI));
628 // VNI is live-in to MBB.
629 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
630 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
632 // Make sure VNI is live-out from the predecessors.
633 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
634 PE = MBB->pred_end(); PI != PE; ++PI) {
635 if (!LiveOut.insert(*PI))
637 SlotIndex Stop = getMBBEndIdx(*PI);
638 assert(li->getVNInfoBefore(Stop) == VNI &&
639 "Wrong value out of predecessor");
640 WorkList.push_back(std::make_pair(Stop, VNI));
644 // Handle dead values.
645 bool CanSeparate = false;
646 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
651 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
652 assert(LII != NewLI.end() && "Missing live range for PHI");
653 if (LII->end != VNI->def.getDeadSlot())
655 if (VNI->isPHIDef()) {
656 // This is a dead PHI. Remove it.
657 VNI->setIsUnused(true);
658 NewLI.removeRange(*LII);
659 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
662 // This is a dead def. Make sure the instruction knows.
663 MachineInstr *MI = getInstructionFromIndex(VNI->def);
664 assert(MI && "No instruction defining live value");
665 MI->addRegisterDead(li->reg, TRI);
666 if (dead && MI->allDefsAreDead()) {
667 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
673 // Move the trimmed ranges back.
674 li->ranges.swap(NewLI.ranges);
675 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
680 //===----------------------------------------------------------------------===//
681 // Register allocator hooks.
684 void LiveIntervals::addKillFlags() {
685 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
686 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
687 if (MRI->reg_nodbg_empty(Reg))
689 LiveInterval *LI = &getInterval(Reg);
691 // Every instruction that kills Reg corresponds to a live range end point.
692 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
694 // A block index indicates an MBB edge.
695 if (RI->end.isBlock())
697 MachineInstr *MI = getInstructionFromIndex(RI->end);
700 MI->addRegisterKilled(Reg, NULL);
706 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
707 // A local live range must be fully contained inside the block, meaning it is
708 // defined and killed at instructions, not at block boundaries. It is not
709 // live in or or out of any block.
711 // It is technically possible to have a PHI-defined live range identical to a
712 // single block, but we are going to return false in that case.
714 SlotIndex Start = LI.beginIndex();
718 SlotIndex Stop = LI.endIndex();
722 // getMBBFromIndex doesn't need to search the MBB table when both indexes
723 // belong to proper instructions.
724 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
725 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
726 return MBB1 == MBB2 ? MBB1 : NULL;
730 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
731 // Limit the loop depth ridiculousness.
735 // The loop depth is used to roughly estimate the number of times the
736 // instruction is executed. Something like 10^d is simple, but will quickly
737 // overflow a float. This expression behaves like 10^d for small d, but is
738 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
739 // headroom before overflow.
740 // By the way, powf() might be unavailable here. For consistency,
741 // We may take pow(double,double).
742 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
744 return (isDef + isUse) * lc;
747 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
748 MachineInstr* startInst) {
749 LiveInterval& Interval = getOrCreateInterval(reg);
750 VNInfo* VN = Interval.getNextValue(
751 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
752 getVNInfoAllocator());
753 VN->setHasPHIKill(true);
755 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
756 getMBBEndIdx(startInst->getParent()), VN);
757 Interval.addRange(LR);
763 //===----------------------------------------------------------------------===//
764 // Register mask functions
765 //===----------------------------------------------------------------------===//
767 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
768 BitVector &UsableRegs) {
771 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
773 // Use a smaller arrays for local live ranges.
774 ArrayRef<SlotIndex> Slots;
775 ArrayRef<const uint32_t*> Bits;
776 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
777 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
778 Bits = getRegMaskBitsInBlock(MBB->getNumber());
780 Slots = getRegMaskSlots();
781 Bits = getRegMaskBits();
784 // We are going to enumerate all the register mask slots contained in LI.
785 // Start with a binary search of RegMaskSlots to find a starting point.
786 ArrayRef<SlotIndex>::iterator SlotI =
787 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
788 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
790 // No slots in range, LI begins after the last call.
796 assert(*SlotI >= LiveI->start);
797 // Loop over all slots overlapping this segment.
798 while (*SlotI < LiveI->end) {
799 // *SlotI overlaps LI. Collect mask bits.
801 // This is the first overlap. Initialize UsableRegs to all ones.
803 UsableRegs.resize(TRI->getNumRegs(), true);
806 // Remove usable registers clobbered by this mask.
807 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
808 if (++SlotI == SlotE)
811 // *SlotI is beyond the current LI segment.
812 LiveI = LI.advanceTo(LiveI, *SlotI);
815 // Advance SlotI until it overlaps.
816 while (*SlotI < LiveI->start)
817 if (++SlotI == SlotE)
822 //===----------------------------------------------------------------------===//
823 // IntervalUpdate class.
824 //===----------------------------------------------------------------------===//
826 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
827 class LiveIntervals::HMEditor {
830 const MachineRegisterInfo& MRI;
831 const TargetRegisterInfo& TRI;
834 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
835 typedef DenseSet<IntRangePair> RangeSet;
842 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
844 typedef DenseMap<unsigned, RegRanges> BundleRanges;
847 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
848 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
849 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
851 // Update intervals for all operands of MI from OldIdx to NewIdx.
852 // This assumes that MI used to be at OldIdx, and now resides at
854 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
855 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
857 // Collect the operands.
858 RangeSet Entering, Internal, Exiting;
859 bool hasRegMaskOp = false;
860 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
862 // To keep the LiveRanges valid within an interval, move the ranges closest
863 // to the destination first. This prevents ranges from overlapping, to that
864 // APIs like removeRange still work.
865 if (NewIdx < OldIdx) {
866 moveAllEnteringFrom(OldIdx, Entering);
867 moveAllInternalFrom(OldIdx, Internal);
868 moveAllExitingFrom(OldIdx, Exiting);
871 moveAllExitingFrom(OldIdx, Exiting);
872 moveAllInternalFrom(OldIdx, Internal);
873 moveAllEnteringFrom(OldIdx, Entering);
877 updateRegMaskSlots(OldIdx);
880 LIValidator validator;
881 validator = std::for_each(Entering.begin(), Entering.end(), validator);
882 validator = std::for_each(Internal.begin(), Internal.end(), validator);
883 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
884 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
889 // Update intervals for all operands of MI to refer to BundleStart's
891 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
892 if (MI == BundleStart)
893 return; // Bundling instr with itself - nothing to do.
895 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
896 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
897 "SlotIndex <-> Instruction mapping broken for MI");
899 // Collect all ranges already in the bundle.
900 MachineBasicBlock::instr_iterator BII(BundleStart);
901 RangeSet Entering, Internal, Exiting;
902 bool hasRegMaskOp = false;
903 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
904 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
905 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
908 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
909 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
912 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
917 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
918 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
920 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
921 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
922 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
924 moveAllEnteringFromInto(OldIdx, Entering, BR);
925 moveAllInternalFromInto(OldIdx, Internal, BR);
926 moveAllExitingFromInto(OldIdx, Exiting, BR);
930 LIValidator validator;
931 validator = std::for_each(Entering.begin(), Entering.end(), validator);
932 validator = std::for_each(Internal.begin(), Internal.end(), validator);
933 validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
934 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
943 DenseSet<const LiveInterval*> Checked, Bogus;
945 void operator()(const IntRangePair& P) {
946 const LiveInterval* LI = P.first;
947 if (Checked.count(LI))
952 SlotIndex LastEnd = LI->begin()->start;
953 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
955 const LiveRange& LR = *LRI;
956 if (LastEnd > LR.start || LR.start >= LR.end)
962 bool rangesOk() const {
963 return Bogus.empty();
968 // Collect IntRangePairs for all operands of MI that may need fixing.
969 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
971 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
972 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
973 hasRegMaskOp = false;
974 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
975 MOE = MI->operands_end();
977 const MachineOperand& MO = *MOI;
979 if (MO.isRegMask()) {
984 if (!MO.isReg() || MO.getReg() == 0)
987 unsigned Reg = MO.getReg();
989 // TODO: Currently we're skipping uses that are reserved or have no
990 // interval, but we're not updating their kills. This should be
992 if (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg))
995 // Collect ranges for register units. These live ranges are computed on
996 // demand, so just skip any that haven't been computed yet.
997 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
998 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
999 if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
1000 collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx);
1002 // Collect ranges for individual virtual registers.
1003 collectRanges(MO, &LIS.getInterval(Reg),
1004 Entering, Internal, Exiting, OldIdx);
1009 void collectRanges(const MachineOperand &MO, LiveInterval *LI,
1010 RangeSet &Entering, RangeSet &Internal, RangeSet &Exiting,
1012 if (MO.readsReg()) {
1013 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1015 Entering.insert(std::make_pair(LI, LR));
1018 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1019 assert(LR != 0 && "No live range for def?");
1020 if (LR->end > OldIdx.getDeadSlot())
1021 Exiting.insert(std::make_pair(LI, LR));
1023 Internal.insert(std::make_pair(LI, LR));
1027 BundleRanges createBundleRanges(RangeSet& Entering,
1029 RangeSet& Exiting) {
1032 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1034 LiveInterval* LI = EI->first;
1035 LiveRange* LR = EI->second;
1036 BR[LI->reg].Use = LR;
1039 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1041 LiveInterval* LI = II->first;
1042 LiveRange* LR = II->second;
1043 if (LR->end.isDead()) {
1044 BR[LI->reg].Dead = LR;
1046 BR[LI->reg].EC = LR;
1050 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1052 LiveInterval* LI = EI->first;
1053 LiveRange* LR = EI->second;
1054 BR[LI->reg].Def = LR;
1060 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1061 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1062 if (!OldKillMI->killsRegister(reg))
1063 return; // Bail out if we don't have kill flags on the old register.
1064 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1065 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1066 assert(!NewKillMI->killsRegister(reg) &&
1067 "New kill instr is already a kill.");
1068 OldKillMI->clearRegisterKills(reg, &TRI);
1069 NewKillMI->addRegisterKilled(reg, &TRI);
1072 void updateRegMaskSlots(SlotIndex OldIdx) {
1073 SmallVectorImpl<SlotIndex>::iterator RI =
1074 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1076 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1078 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1079 "RegSlots out of order. Did you move one call across another?");
1082 // Return the last use of reg between NewIdx and OldIdx.
1083 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1084 SlotIndex LastUse = NewIdx;
1085 for (MachineRegisterInfo::use_nodbg_iterator
1086 UI = MRI.use_nodbg_begin(Reg),
1087 UE = MRI.use_nodbg_end();
1088 UI != UE; UI.skipInstruction()) {
1089 const MachineInstr* MI = &*UI;
1090 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1091 if (InstSlot > LastUse && InstSlot < OldIdx)
1097 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1098 LiveInterval* LI = P.first;
1099 LiveRange* LR = P.second;
1100 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1103 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1104 if (LastUse != NewIdx)
1105 moveKillFlags(LI->reg, NewIdx, LastUse);
1106 LR->end = LastUse.getRegSlot();
1109 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1110 LiveInterval* LI = P.first;
1111 LiveRange* LR = P.second;
1112 // Extend the LiveRange if NewIdx is past the end.
1113 if (NewIdx > LR->end) {
1114 // Move kill flags if OldIdx was not originally the end
1115 // (otherwise LR->end points to an invalid slot).
1116 if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
1117 assert(LR->end > OldIdx && "LiveRange does not cover original slot");
1118 moveKillFlags(LI->reg, LR->end, NewIdx);
1120 LR->end = NewIdx.getRegSlot();
1124 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1125 bool GoingUp = NewIdx < OldIdx;
1128 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1130 moveEnteringUpFrom(OldIdx, *EI);
1132 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1134 moveEnteringDownFrom(OldIdx, *EI);
1138 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1139 LiveInterval* LI = P.first;
1140 LiveRange* LR = P.second;
1141 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1142 LR->end <= OldIdx.getDeadSlot() &&
1143 "Range should be internal to OldIdx.");
1145 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1146 Tmp.valno->def = Tmp.start;
1147 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1148 LI->removeRange(*LR);
1152 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1153 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1155 moveInternalFrom(OldIdx, *II);
1158 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1159 LiveRange* LR = P.second;
1160 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1161 "Range should start in OldIdx.");
1162 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1163 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1164 LR->start = NewStart;
1165 LR->valno->def = NewStart;
1168 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1169 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1171 moveExitingFrom(OldIdx, *EI);
1174 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1176 LiveInterval* LI = P.first;
1177 LiveRange* LR = P.second;
1178 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1180 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1181 "Def in bundle should be def range.");
1182 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1183 "If bundle has use for this reg it should be LR.");
1184 BR[LI->reg].Use = LR;
1188 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1189 moveKillFlags(LI->reg, OldIdx, LastUse);
1191 if (LR->start < NewIdx) {
1192 // Becoming a new entering range.
1193 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1194 "Bundle shouldn't be re-defining reg mid-range.");
1195 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1196 "Bundle shouldn't have different use range for same reg.");
1197 LR->end = LastUse.getRegSlot();
1198 BR[LI->reg].Use = LR;
1200 // Becoming a new Dead-def.
1201 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1202 "Live range starting at unexpected slot.");
1203 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1204 assert(BR[LI->reg].Dead == 0 &&
1205 "Can't have def and dead def of same reg in a bundle.");
1206 LR->end = LastUse.getDeadSlot();
1207 BR[LI->reg].Dead = BR[LI->reg].Def;
1208 BR[LI->reg].Def = 0;
1212 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1214 LiveInterval* LI = P.first;
1215 LiveRange* LR = P.second;
1216 if (NewIdx > LR->end) {
1217 // Range extended to bundle. Add to bundle uses.
1218 // Note: Currently adds kill flags to bundle start.
1219 assert(BR[LI->reg].Use == 0 &&
1220 "Bundle already has use range for reg.");
1221 moveKillFlags(LI->reg, LR->end, NewIdx);
1222 LR->end = NewIdx.getRegSlot();
1223 BR[LI->reg].Use = LR;
1225 assert(BR[LI->reg].Use != 0 &&
1226 "Bundle should already have a use range for reg.");
1230 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1232 bool GoingUp = NewIdx < OldIdx;
1235 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1237 moveEnteringUpFromInto(OldIdx, *EI, BR);
1239 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1241 moveEnteringDownFromInto(OldIdx, *EI, BR);
1245 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1247 // TODO: Sane rules for moving ranges into bundles.
1250 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1252 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1254 moveInternalFromInto(OldIdx, *II, BR);
1257 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1259 LiveInterval* LI = P.first;
1260 LiveRange* LR = P.second;
1262 assert(LR->start.isRegister() &&
1263 "Don't know how to merge exiting ECs into bundles yet.");
1265 if (LR->end > NewIdx.getDeadSlot()) {
1266 // This range is becoming an exiting range on the bundle.
1267 // If there was an old dead-def of this reg, delete it.
1268 if (BR[LI->reg].Dead != 0) {
1269 LI->removeRange(*BR[LI->reg].Dead);
1270 BR[LI->reg].Dead = 0;
1272 assert(BR[LI->reg].Def == 0 &&
1273 "Can't have two defs for the same variable exiting a bundle.");
1274 LR->start = NewIdx.getRegSlot();
1275 LR->valno->def = LR->start;
1276 BR[LI->reg].Def = LR;
1278 // This range is becoming internal to the bundle.
1279 assert(LR->end == NewIdx.getRegSlot() &&
1280 "Can't bundle def whose kill is before the bundle");
1281 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1282 // Already have a def for this. Just delete range.
1283 LI->removeRange(*LR);
1285 // Make range dead, record.
1286 LR->end = NewIdx.getDeadSlot();
1287 BR[LI->reg].Dead = LR;
1288 assert(BR[LI->reg].Use == LR &&
1289 "Range becoming dead should currently be use.");
1291 // In both cases the range is no longer a use on the bundle.
1292 BR[LI->reg].Use = 0;
1296 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1298 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1300 moveExitingFromInto(OldIdx, *EI, BR);
1305 void LiveIntervals::handleMove(MachineInstr* MI) {
1306 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1307 Indexes->removeMachineInstrFromMaps(MI);
1308 SlotIndex NewIndex = MI->isInsideBundle() ?
1309 Indexes->getInstructionIndex(MI) :
1310 Indexes->insertMachineInstrInMaps(MI);
1311 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1312 OldIndex < getMBBEndIdx(MI->getParent()) &&
1313 "Cannot handle moves across basic block boundaries.");
1314 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1316 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1317 HME.moveAllRangesFrom(MI, OldIndex);
1320 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1321 MachineInstr* BundleStart) {
1322 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1323 HMEditor HME(*this, *MRI, *TRI, NewIndex);
1324 HME.moveAllRangesInto(MI, BundleStart);