1 //===-- LiveIntervals.cpp - Live Interval Analysis ------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "liveintervals"
19 #include "llvm/CodeGen/LiveIntervals.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetRegInfo.h"
31 #include "llvm/Support/CFG.h"
32 #include "Support/Debug.h"
33 #include "Support/DepthFirstIterator.h"
34 #include "Support/Statistic.h"
40 RegisterAnalysis<LiveIntervals> X("liveintervals",
41 "Live Interval Analysis");
43 Statistic<> numIntervals("liveintervals", "Number of intervals");
46 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
49 AU.addRequired<LiveVariables>();
50 AU.addRequiredID(PHIEliminationID);
51 MachineFunctionPass::getAnalysisUsage(AU);
54 /// runOnMachineFunction - Register allocate the whole function
56 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
57 DEBUG(std::cerr << "Machine Function\n");
59 tm_ = &fn.getTarget();
60 mri_ = tm_->getRegisterInfo();
61 lv_ = &getAnalysis<LiveVariables>();
62 allocatableRegisters_.clear();
69 // mark allocatable registers
70 allocatableRegisters_.resize(MRegisterInfo::FirstVirtualRegister);
71 // Loop over all of the register classes...
72 for (MRegisterInfo::regclass_iterator
73 rci = mri_->regclass_begin(), rce = mri_->regclass_end();
75 // Loop over all of the allocatable registers in the function...
76 for (TargetRegisterClass::iterator
77 i = (*rci)->allocation_order_begin(*mf_),
78 e = (*rci)->allocation_order_end(*mf_); i != e; ++i) {
79 allocatableRegisters_[*i] = true; // The reg is allocatable!
83 // number MachineInstrs
85 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
86 mbb != mbbEnd; ++mbb) {
87 const std::pair<MachineBasicBlock*, unsigned>& entry =
88 lv_->getMachineBasicBlockInfo(&*mbb);
89 bool inserted = mbbi2mbbMap_.insert(std::make_pair(entry.second,
91 assert(inserted && "multiple index -> MachineBasicBlock");
93 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
95 inserted = mi2iMap_.insert(std::make_pair(*mi, miIndex)).second;
96 assert(inserted && "multiple MachineInstr -> index mappings");
106 void LiveIntervals::printRegName(unsigned reg) const
108 if (reg < MRegisterInfo::FirstVirtualRegister)
109 std::cerr << mri_->getName(reg);
111 std::cerr << '%' << reg;
114 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
115 MachineBasicBlock::iterator mi,
118 DEBUG(std::cerr << "\t\t\tregister: ";printRegName(reg); std::cerr << '\n');
120 unsigned instrIndex = getInstructionIndex(*mi);
122 LiveVariables::VarInfo& vi = lv_->getVarInfo(reg);
124 Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
125 // handle multiple definition case (machine instructions violating
126 // ssa after phi-elimination
127 if (r2iit != r2iMap_.end()) {
128 unsigned ii = r2iit->second;
129 Interval& interval = intervals_[ii];
130 unsigned end = getInstructionIndex(mbb->back()) + 1;
131 DEBUG(std::cerr << "\t\t\t\tadding range: ["
132 << instrIndex << ',' << end << "]\n");
133 interval.addRange(instrIndex, end);
134 DEBUG(std::cerr << "\t\t\t\t" << interval << '\n');
138 intervals_.push_back(Interval(reg));
139 Interval& interval = intervals_.back();
140 // update interval index for this register
141 r2iMap_[reg] = intervals_.size() - 1;
143 for (MbbIndex2MbbMap::iterator
144 it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
146 unsigned liveBlockIndex = it->first;
147 MachineBasicBlock* liveBlock = it->second;
148 if (liveBlockIndex < vi.AliveBlocks.size() &&
149 vi.AliveBlocks[liveBlockIndex]) {
150 unsigned start = getInstructionIndex(liveBlock->front());
151 unsigned end = getInstructionIndex(liveBlock->back()) + 1;
152 DEBUG(std::cerr << "\t\t\t\tadding range: ["
153 << start << ',' << end << "]\n");
154 interval.addRange(start, end);
158 bool killedInDefiningBasicBlock = false;
159 for (int i = 0, e = vi.Kills.size(); i != e; ++i) {
160 MachineBasicBlock* killerBlock = vi.Kills[i].first;
161 MachineInstr* killerInstr = vi.Kills[i].second;
162 killedInDefiningBasicBlock |= mbb == killerBlock;
163 unsigned start = (mbb == killerBlock ?
165 getInstructionIndex(killerBlock->front()));
166 unsigned end = getInstructionIndex(killerInstr) + 1;
167 DEBUG(std::cerr << "\t\t\t\tadding range: ["
168 << start << ',' << end << "]\n");
169 interval.addRange(start, end);
172 if (!killedInDefiningBasicBlock) {
173 unsigned end = getInstructionIndex(mbb->back()) + 1;
174 interval.addRange(instrIndex, end);
177 DEBUG(std::cerr << "\t\t\t\t" << interval << '\n');
181 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock* mbb,
182 MachineBasicBlock::iterator mi,
185 DEBUG(std::cerr << "\t\t\tregister: ";printRegName(reg); std::cerr << '\n');
186 if (!lv_->getAllocatablePhysicalRegisters()[reg]) {
187 DEBUG(std::cerr << "\t\t\t\tnon allocatable register: ignoring\n");
191 unsigned start = getInstructionIndex(*mi);
192 unsigned end = start;
194 for (MachineBasicBlock::iterator e = mbb->end(); mi != e; ++mi) {
195 for (LiveVariables::killed_iterator
196 ki = lv_->dead_begin(*mi),
197 ke = lv_->dead_end(*mi);
199 if (reg == ki->second) {
200 end = getInstructionIndex(ki->first) + 1;
205 for (LiveVariables::killed_iterator
206 ki = lv_->killed_begin(*mi),
207 ke = lv_->killed_end(*mi);
209 if (reg == ki->second) {
210 end = getInstructionIndex(ki->first) + 1;
216 assert(start < end && "did not find end of interval?");
218 Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
219 if (r2iit != r2iMap_.end()) {
220 unsigned ii = r2iit->second;
221 Interval& interval = intervals_[ii];
222 DEBUG(std::cerr << "\t\t\t\tadding range: ["
223 << start << ',' << end << "]\n");
224 interval.addRange(start, end);
225 DEBUG(std::cerr << "\t\t\t\t" << interval << '\n');
228 intervals_.push_back(Interval(reg));
229 Interval& interval = intervals_.back();
230 // update interval index for this register
231 r2iMap_[reg] = intervals_.size() - 1;
232 DEBUG(std::cerr << "\t\t\t\tadding range: ["
233 << start << ',' << end << "]\n");
234 interval.addRange(start, end);
235 DEBUG(std::cerr << "\t\t\t\t" << interval << '\n');
239 void LiveIntervals::handleRegisterDef(MachineBasicBlock* mbb,
240 MachineBasicBlock::iterator mi,
243 if (reg < MRegisterInfo::FirstVirtualRegister) {
244 if (allocatableRegisters_[reg]) {
245 handlePhysicalRegisterDef(mbb, mi, reg);
249 handleVirtualRegisterDef(mbb, mi, reg);
253 unsigned LiveIntervals::getInstructionIndex(MachineInstr* instr) const
255 assert(mi2iMap_.find(instr) != mi2iMap_.end() &&
256 "instruction not assigned a number");
257 return mi2iMap_.find(instr)->second;
260 /// computeIntervals - computes the live intervals for virtual
261 /// registers. for some ordering of the machine instructions [1,N] a
262 /// live interval is an interval [i, j] where 1 <= i <= j <= N for
263 /// which a variable is live
264 void LiveIntervals::computeIntervals()
266 DEBUG(std::cerr << "computing live intervals:\n");
268 for (MbbIndex2MbbMap::iterator
269 it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
271 MachineBasicBlock* mbb = it->second;
272 DEBUG(std::cerr << "machine basic block: "
273 << mbb->getBasicBlock()->getName() << "\n");
274 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
276 MachineInstr* instr = *mi;
277 const TargetInstrDescriptor& tid =
278 tm_->getInstrInfo().get(instr->getOpcode());
279 DEBUG(std::cerr << "\t\tinstruction["
280 << getInstructionIndex(instr) << "]: ";
281 instr->print(std::cerr, *tm_););
283 // handle implicit defs
284 for (const unsigned* id = tid.ImplicitDefs; *id; ++id) {
285 unsigned physReg = *id;
286 handlePhysicalRegisterDef(mbb, mi, physReg);
289 // handle explicit defs
290 for (int i = instr->getNumOperands() - 1; i >= 0; --i) {
291 MachineOperand& mop = instr->getOperand(i);
293 if (!mop.isRegister())
296 if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
297 unsigned reg = mop.getAllocatedRegNum();
298 if (reg < MRegisterInfo::FirstVirtualRegister)
299 handlePhysicalRegisterDef(mbb, mi, reg);
301 handleVirtualRegisterDef(mbb, mi, reg);
307 std::sort(intervals_.begin(), intervals_.end(), StartPointComp());
308 DEBUG(std::copy(intervals_.begin(), intervals_.end(),
309 std::ostream_iterator<Interval>(std::cerr, "\n")));
312 std::ostream& llvm::operator<<(std::ostream& os,
313 const LiveIntervals::Interval& li)
315 os << "%reg" << li.reg << " = ";
316 for (LiveIntervals::Interval::Ranges::const_iterator
317 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) {
318 os << "[" << i->first << "," << i->second << "]";