1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/ProcessImplicitDefs.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/ADT/Statistic.h"
36 #include "llvm/ADT/STLExtras.h"
42 // Hidden options for help debugging.
43 static cl::opt<bool> DisableReMat("disable-rematerialization",
44 cl::init(false), cl::Hidden);
46 STATISTIC(numIntervals , "Number of original intervals");
48 char LiveIntervals::ID = 0;
49 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
50 "Live Interval Analysis", false, false)
51 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
52 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
53 INITIALIZE_PASS_DEPENDENCY(PHIElimination)
54 INITIALIZE_PASS_DEPENDENCY(TwoAddressInstructionPass)
55 INITIALIZE_PASS_DEPENDENCY(ProcessImplicitDefs)
56 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
57 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
58 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
59 "Live Interval Analysis", false, false)
61 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addRequired<AliasAnalysis>();
64 AU.addPreserved<AliasAnalysis>();
65 AU.addRequired<LiveVariables>();
66 AU.addPreserved<LiveVariables>();
67 AU.addRequired<MachineLoopInfo>();
68 AU.addPreserved<MachineLoopInfo>();
69 AU.addPreservedID(MachineDominatorsID);
72 AU.addPreservedID(PHIEliminationID);
73 AU.addRequiredID(PHIEliminationID);
76 AU.addRequiredID(TwoAddressInstructionPassID);
77 AU.addPreserved<ProcessImplicitDefs>();
78 AU.addRequired<ProcessImplicitDefs>();
79 AU.addPreserved<SlotIndexes>();
80 AU.addRequiredTransitive<SlotIndexes>();
81 MachineFunctionPass::getAnalysisUsage(AU);
84 void LiveIntervals::releaseMemory() {
85 // Free the live intervals themselves.
86 for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
87 E = r2iMap_.end(); I != E; ++I)
93 RegMaskBlocks.clear();
95 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
96 VNInfoAllocator.Reset();
99 /// runOnMachineFunction - Register allocate the whole function
101 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
103 mri_ = &mf_->getRegInfo();
104 tm_ = &fn.getTarget();
105 tri_ = tm_->getRegisterInfo();
106 tii_ = tm_->getInstrInfo();
107 aa_ = &getAnalysis<AliasAnalysis>();
108 lv_ = &getAnalysis<LiveVariables>();
109 indexes_ = &getAnalysis<SlotIndexes>();
110 allocatableRegs_ = tri_->getAllocatableSet(fn);
114 numIntervals += getNumIntervals();
120 /// print - Implement the dump method.
121 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
122 OS << "********** INTERVALS **********\n";
123 for (const_iterator I = begin(), E = end(); I != E; ++I) {
124 I->second->print(OS, tri_);
131 void LiveIntervals::printInstrs(raw_ostream &OS) const {
132 OS << "********** MACHINEINSTRS **********\n";
133 mf_->print(OS, indexes_);
136 void LiveIntervals::dumpInstrs() const {
141 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
142 unsigned Reg = MI.getOperand(MOIdx).getReg();
143 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
144 const MachineOperand &MO = MI.getOperand(i);
147 if (MO.getReg() == Reg && MO.isDef()) {
148 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
149 MI.getOperand(MOIdx).getSubReg() &&
150 (MO.getSubReg() || MO.isImplicit()));
157 /// isPartialRedef - Return true if the specified def at the specific index is
158 /// partially re-defining the specified live interval. A common case of this is
159 /// a definition of the sub-register.
160 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
161 LiveInterval &interval) {
162 if (!MO.getSubReg() || MO.isEarlyClobber())
165 SlotIndex RedefIndex = MIIdx.getRegSlot();
166 const LiveRange *OldLR =
167 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
168 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
170 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
175 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
176 MachineBasicBlock::iterator mi,
180 LiveInterval &interval) {
181 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
183 // Virtual registers may be defined multiple times (due to phi
184 // elimination and 2-addr elimination). Much of what we do only has to be
185 // done once for the vreg. We use an empty interval to detect the first
186 // time we see a vreg.
187 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
188 if (interval.empty()) {
189 // Get the Idx of the defining instructions.
190 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
192 // Make sure the first definition is not a partial redefinition. Add an
193 // <imp-def> of the full register.
194 // FIXME: LiveIntervals shouldn't modify the code like this. Whoever
195 // created the machine instruction should annotate it with <undef> flags
196 // as needed. Then we can simply assert here. The REG_SEQUENCE lowering
197 // is the main suspect.
198 if (MO.getSubReg()) {
199 mi->addRegisterDefined(interval.reg);
200 // Mark all defs of interval.reg on this instruction as reading <undef>.
201 for (unsigned i = MOIdx, e = mi->getNumOperands(); i != e; ++i) {
202 MachineOperand &MO2 = mi->getOperand(i);
203 if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg())
208 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
209 assert(ValNo->id == 0 && "First value in interval is not 0?");
211 // Loop over all of the blocks that the vreg is defined in. There are
212 // two cases we have to handle here. The most common case is a vreg
213 // whose lifetime is contained within a basic block. In this case there
214 // will be a single kill, in MBB, which comes after the definition.
215 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
216 // FIXME: what about dead vars?
218 if (vi.Kills[0] != mi)
219 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
221 killIdx = defIndex.getDeadSlot();
223 // If the kill happens after the definition, we have an intra-block
225 if (killIdx > defIndex) {
226 assert(vi.AliveBlocks.empty() &&
227 "Shouldn't be alive across any blocks!");
228 LiveRange LR(defIndex, killIdx, ValNo);
229 interval.addRange(LR);
230 DEBUG(dbgs() << " +" << LR << "\n");
235 // The other case we handle is when a virtual register lives to the end
236 // of the defining block, potentially live across some blocks, then is
237 // live into some number of blocks, but gets killed. Start by adding a
238 // range that goes from this definition to the end of the defining block.
239 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
240 DEBUG(dbgs() << " +" << NewLR);
241 interval.addRange(NewLR);
243 bool PHIJoin = lv_->isPHIJoin(interval.reg);
246 // A phi join register is killed at the end of the MBB and revived as a new
247 // valno in the killing blocks.
248 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
249 DEBUG(dbgs() << " phi-join");
250 ValNo->setHasPHIKill(true);
252 // Iterate over all of the blocks that the variable is completely
253 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
255 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
256 E = vi.AliveBlocks.end(); I != E; ++I) {
257 MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
258 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
259 interval.addRange(LR);
260 DEBUG(dbgs() << " +" << LR);
264 // Finally, this virtual register is live from the start of any killing
265 // block to the 'use' slot of the killing instruction.
266 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
267 MachineInstr *Kill = vi.Kills[i];
268 SlotIndex Start = getMBBStartIdx(Kill->getParent());
269 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
271 // Create interval with one of a NEW value number. Note that this value
272 // number isn't actually defined by an instruction, weird huh? :)
274 assert(getInstructionFromIndex(Start) == 0 &&
275 "PHI def index points at actual instruction.");
276 ValNo = interval.getNextValue(Start, VNInfoAllocator);
277 ValNo->setIsPHIDef(true);
279 LiveRange LR(Start, killIdx, ValNo);
280 interval.addRange(LR);
281 DEBUG(dbgs() << " +" << LR);
285 if (MultipleDefsBySameMI(*mi, MOIdx))
286 // Multiple defs of the same virtual register by the same instruction.
287 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
288 // This is likely due to elimination of REG_SEQUENCE instructions. Return
289 // here since there is nothing to do.
292 // If this is the second time we see a virtual register definition, it
293 // must be due to phi elimination or two addr elimination. If this is
294 // the result of two address elimination, then the vreg is one of the
295 // def-and-use register operand.
297 // It may also be partial redef like this:
298 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
299 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
300 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
301 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
302 // If this is a two-address definition, then we have already processed
303 // the live range. The only problem is that we didn't realize there
304 // are actually two values in the live interval. Because of this we
305 // need to take the LiveRegion that defines this register and split it
307 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
309 const LiveRange *OldLR =
310 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
311 VNInfo *OldValNo = OldLR->valno;
312 SlotIndex DefIndex = OldValNo->def.getRegSlot();
314 // Delete the previous value, which should be short and continuous,
315 // because the 2-addr copy must be in the same MBB as the redef.
316 interval.removeRange(DefIndex, RedefIndex);
318 // The new value number (#1) is defined by the instruction we claimed
320 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
322 // Value#0 is now defined by the 2-addr instruction.
323 OldValNo->def = RedefIndex;
325 // Add the new live interval which replaces the range for the input copy.
326 LiveRange LR(DefIndex, RedefIndex, ValNo);
327 DEBUG(dbgs() << " replace range with " << LR);
328 interval.addRange(LR);
330 // If this redefinition is dead, we need to add a dummy unit live
331 // range covering the def slot.
333 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
337 dbgs() << " RESULT: ";
338 interval.print(dbgs(), tri_);
340 } else if (lv_->isPHIJoin(interval.reg)) {
341 // In the case of PHI elimination, each variable definition is only
342 // live until the end of the block. We've already taken care of the
343 // rest of the live range.
345 SlotIndex defIndex = MIIdx.getRegSlot();
346 if (MO.isEarlyClobber())
347 defIndex = MIIdx.getRegSlot(true);
349 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
351 SlotIndex killIndex = getMBBEndIdx(mbb);
352 LiveRange LR(defIndex, killIndex, ValNo);
353 interval.addRange(LR);
354 ValNo->setHasPHIKill(true);
355 DEBUG(dbgs() << " phi-join +" << LR);
357 llvm_unreachable("Multiply defined register");
361 DEBUG(dbgs() << '\n');
364 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
365 MachineBasicBlock::iterator mi,
368 LiveInterval &interval) {
369 // A physical register cannot be live across basic block, so its
370 // lifetime must end somewhere in its defining basic block.
371 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
373 SlotIndex baseIndex = MIIdx;
374 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
375 SlotIndex end = start;
377 // If it is not used after definition, it is considered dead at
378 // the instruction defining it. Hence its interval is:
379 // [defSlot(def), defSlot(def)+1)
380 // For earlyclobbers, the defSlot was pushed back one; the extra
381 // advance below compensates.
383 DEBUG(dbgs() << " dead");
384 end = start.getDeadSlot();
388 // If it is not dead on definition, it must be killed by a
389 // subsequent instruction. Hence its interval is:
390 // [defSlot(def), useSlot(kill)+1)
391 baseIndex = baseIndex.getNextIndex();
392 while (++mi != MBB->end()) {
394 if (mi->isDebugValue())
396 if (getInstructionFromIndex(baseIndex) == 0)
397 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
399 if (mi->killsRegister(interval.reg, tri_)) {
400 DEBUG(dbgs() << " killed");
401 end = baseIndex.getRegSlot();
404 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
406 if (mi->isRegTiedToUseOperand(DefIdx)) {
407 // Two-address instruction.
408 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
410 // Another instruction redefines the register before it is ever read.
411 // Then the register is essentially dead at the instruction that
412 // defines it. Hence its interval is:
413 // [defSlot(def), defSlot(def)+1)
414 DEBUG(dbgs() << " dead");
415 end = start.getDeadSlot();
421 baseIndex = baseIndex.getNextIndex();
424 // The only case we should have a dead physreg here without a killing or
425 // instruction where we know it's dead is if it is live-in to the function
426 // and never used. Another possible case is the implicit use of the
427 // physical register has been deleted by two-address pass.
428 end = start.getDeadSlot();
431 assert(start < end && "did not find end of interval?");
433 // Already exists? Extend old live interval.
434 VNInfo *ValNo = interval.getVNInfoAt(start);
435 bool Extend = ValNo != 0;
437 ValNo = interval.getNextValue(start, VNInfoAllocator);
438 LiveRange LR(start, end, ValNo);
439 interval.addRange(LR);
440 DEBUG(dbgs() << " +" << LR << '\n');
443 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
444 MachineBasicBlock::iterator MI,
448 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
449 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
450 getOrCreateInterval(MO.getReg()));
452 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
453 getOrCreateInterval(MO.getReg()));
456 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
458 LiveInterval &interval) {
459 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
461 // Look for kills, if it reaches a def before it's killed, then it shouldn't
462 // be considered a livein.
463 MachineBasicBlock::iterator mi = MBB->begin();
464 MachineBasicBlock::iterator E = MBB->end();
465 // Skip over DBG_VALUE at the start of the MBB.
466 if (mi != E && mi->isDebugValue()) {
467 while (++mi != E && mi->isDebugValue())
470 // MBB is empty except for DBG_VALUE's.
474 SlotIndex baseIndex = MIIdx;
475 SlotIndex start = baseIndex;
476 if (getInstructionFromIndex(baseIndex) == 0)
477 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
479 SlotIndex end = baseIndex;
480 bool SeenDefUse = false;
483 if (mi->killsRegister(interval.reg, tri_)) {
484 DEBUG(dbgs() << " killed");
485 end = baseIndex.getRegSlot();
488 } else if (mi->definesRegister(interval.reg, tri_)) {
489 // Another instruction redefines the register before it is ever read.
490 // Then the register is essentially dead at the instruction that defines
491 // it. Hence its interval is:
492 // [defSlot(def), defSlot(def)+1)
493 DEBUG(dbgs() << " dead");
494 end = start.getDeadSlot();
499 while (++mi != E && mi->isDebugValue())
500 // Skip over DBG_VALUE.
503 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
506 // Live-in register might not be used at all.
508 DEBUG(dbgs() << " live through");
509 end = getMBBEndIdx(MBB);
512 SlotIndex defIdx = getMBBStartIdx(MBB);
513 assert(getInstructionFromIndex(defIdx) == 0 &&
514 "PHI def index points at actual instruction.");
515 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
516 vni->setIsPHIDef(true);
517 LiveRange LR(start, end, vni);
519 interval.addRange(LR);
520 DEBUG(dbgs() << " +" << LR << '\n');
523 /// computeIntervals - computes the live intervals for virtual
524 /// registers. for some ordering of the machine instructions [1,N] a
525 /// live interval is an interval [i, j) where 1 <= i <= j < N for
526 /// which a variable is live
527 void LiveIntervals::computeIntervals() {
528 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
529 << "********** Function: "
530 << ((Value*)mf_->getFunction())->getName() << '\n');
532 RegMaskBlocks.resize(mf_->getNumBlockIDs());
534 SmallVector<unsigned, 8> UndefUses;
535 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
537 MachineBasicBlock *MBB = MBBI;
538 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
543 // Track the index of the current machine instr.
544 SlotIndex MIIndex = getMBBStartIdx(MBB);
545 DEBUG(dbgs() << "BB#" << MBB->getNumber()
546 << ":\t\t# derived from " << MBB->getName() << "\n");
548 // Create intervals for live-ins to this BB first.
549 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
550 LE = MBB->livein_end(); LI != LE; ++LI) {
551 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
554 // Skip over empty initial indices.
555 if (getInstructionFromIndex(MIIndex) == 0)
556 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
558 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
560 DEBUG(dbgs() << MIIndex << "\t" << *MI);
561 if (MI->isDebugValue())
563 assert(indexes_->getInstructionFromIndex(MIIndex) == MI &&
564 "Lost SlotIndex synchronization");
567 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
568 MachineOperand &MO = MI->getOperand(i);
570 // Collect register masks.
571 if (MO.isRegMask()) {
572 RegMaskSlots.push_back(MIIndex.getRegSlot());
573 RegMaskBits.push_back(MO.getRegMask());
577 if (!MO.isReg() || !MO.getReg())
580 // handle register defs - build intervals
582 handleRegisterDef(MBB, MI, MIIndex, MO, i);
583 else if (MO.isUndef())
584 UndefUses.push_back(MO.getReg());
587 // Move to the next instr slot.
588 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
591 // Compute the number of register mask instructions in this block.
592 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
593 RMB.second = RegMaskSlots.size() - RMB.first;;
596 // Create empty intervals for registers defined by implicit_def's (except
597 // for those implicit_def that define values which are liveout of their
599 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
600 unsigned UndefReg = UndefUses[i];
601 (void)getOrCreateInterval(UndefReg);
605 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
606 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
607 return new LiveInterval(reg, Weight);
610 /// dupInterval - Duplicate a live interval. The caller is responsible for
611 /// managing the allocated memory.
612 LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
613 LiveInterval *NewLI = createInterval(li->reg);
614 NewLI->Copy(*li, mri_, getVNInfoAllocator());
618 /// shrinkToUses - After removing some uses of a register, shrink its live
619 /// range to just the remaining uses. This method does not compute reaching
620 /// defs for new uses, and it doesn't remove dead defs.
621 bool LiveIntervals::shrinkToUses(LiveInterval *li,
622 SmallVectorImpl<MachineInstr*> *dead) {
623 DEBUG(dbgs() << "Shrink: " << *li << '\n');
624 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
625 && "Can only shrink virtual registers");
626 // Find all the values used, including PHI kills.
627 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
629 // Blocks that have already been added to WorkList as live-out.
630 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
632 // Visit all instructions reading li->reg.
633 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
634 MachineInstr *UseMI = I.skipInstruction();) {
635 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
637 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
638 // Note: This intentionally picks up the wrong VNI in case of an EC redef.
640 VNInfo *VNI = li->getVNInfoBefore(Idx);
642 // This shouldn't happen: readsVirtualRegister returns true, but there is
643 // no live value. It is likely caused by a target getting <undef> flags
645 DEBUG(dbgs() << Idx << '\t' << *UseMI
646 << "Warning: Instr claims to read non-existent value in "
650 // Special case: An early-clobber tied operand reads and writes the
651 // register one slot early. The getVNInfoBefore call above would have
652 // picked up the value defined by UseMI. Adjust the kill slot and value.
653 if (SlotIndex::isSameInstr(VNI->def, Idx)) {
655 VNI = li->getVNInfoBefore(Idx);
656 assert(VNI && "Early-clobber tied value not available");
658 WorkList.push_back(std::make_pair(Idx, VNI));
661 // Create a new live interval with only minimal live segments per def.
662 LiveInterval NewLI(li->reg, 0);
663 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
668 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
671 // Keep track of the PHIs that are in use.
672 SmallPtrSet<VNInfo*, 8> UsedPHIs;
674 // Extend intervals to reach all uses in WorkList.
675 while (!WorkList.empty()) {
676 SlotIndex Idx = WorkList.back().first;
677 VNInfo *VNI = WorkList.back().second;
679 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
680 SlotIndex BlockStart = getMBBStartIdx(MBB);
682 // Extend the live range for VNI to be live at Idx.
683 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
685 assert(ExtVNI == VNI && "Unexpected existing value number");
686 // Is this a PHIDef we haven't seen before?
687 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
689 // The PHI is live, make sure the predecessors are live-out.
690 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
691 PE = MBB->pred_end(); PI != PE; ++PI) {
692 if (!LiveOut.insert(*PI))
694 SlotIndex Stop = getMBBEndIdx(*PI);
695 // A predecessor is not required to have a live-out value for a PHI.
696 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
697 WorkList.push_back(std::make_pair(Stop, PVNI));
702 // VNI is live-in to MBB.
703 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
704 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
706 // Make sure VNI is live-out from the predecessors.
707 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
708 PE = MBB->pred_end(); PI != PE; ++PI) {
709 if (!LiveOut.insert(*PI))
711 SlotIndex Stop = getMBBEndIdx(*PI);
712 assert(li->getVNInfoBefore(Stop) == VNI &&
713 "Wrong value out of predecessor");
714 WorkList.push_back(std::make_pair(Stop, VNI));
718 // Handle dead values.
719 bool CanSeparate = false;
720 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
725 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
726 assert(LII != NewLI.end() && "Missing live range for PHI");
727 if (LII->end != VNI->def.getDeadSlot())
729 if (VNI->isPHIDef()) {
730 // This is a dead PHI. Remove it.
731 VNI->setIsUnused(true);
732 NewLI.removeRange(*LII);
733 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
736 // This is a dead def. Make sure the instruction knows.
737 MachineInstr *MI = getInstructionFromIndex(VNI->def);
738 assert(MI && "No instruction defining live value");
739 MI->addRegisterDead(li->reg, tri_);
740 if (dead && MI->allDefsAreDead()) {
741 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
747 // Move the trimmed ranges back.
748 li->ranges.swap(NewLI.ranges);
749 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
754 //===----------------------------------------------------------------------===//
755 // Register allocator hooks.
758 void LiveIntervals::addKillFlags() {
759 for (iterator I = begin(), E = end(); I != E; ++I) {
760 unsigned Reg = I->first;
761 if (TargetRegisterInfo::isPhysicalRegister(Reg))
763 if (mri_->reg_nodbg_empty(Reg))
765 LiveInterval *LI = I->second;
767 // Every instruction that kills Reg corresponds to a live range end point.
768 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
770 // A block index indicates an MBB edge.
771 if (RI->end.isBlock())
773 MachineInstr *MI = getInstructionFromIndex(RI->end);
776 MI->addRegisterKilled(Reg, NULL);
782 static bool intervalRangesSane(const LiveInterval& li) {
787 SlotIndex lastEnd = li.begin()->start;
788 for (LiveInterval::const_iterator lrItr = li.begin(), lrEnd = li.end();
789 lrItr != lrEnd; ++lrItr) {
790 const LiveRange& lr = *lrItr;
791 if (lastEnd > lr.start || lr.start >= lr.end)
800 template <typename DefSetT>
801 static void handleMoveDefs(LiveIntervals& lis, SlotIndex origIdx,
802 SlotIndex miIdx, const DefSetT& defs) {
803 for (typename DefSetT::const_iterator defItr = defs.begin(),
805 defItr != defEnd; ++defItr) {
806 unsigned def = *defItr;
807 LiveInterval& li = lis.getInterval(def);
808 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot());
809 assert(lr != 0 && "No range for def?");
810 lr->start = miIdx.getRegSlot();
811 lr->valno->def = miIdx.getRegSlot();
812 assert(intervalRangesSane(li) && "Broke live interval moving def.");
816 template <typename DeadDefSetT>
817 static void handleMoveDeadDefs(LiveIntervals& lis, SlotIndex origIdx,
818 SlotIndex miIdx, const DeadDefSetT& deadDefs) {
819 for (typename DeadDefSetT::const_iterator deadDefItr = deadDefs.begin(),
820 deadDefEnd = deadDefs.end();
821 deadDefItr != deadDefEnd; ++deadDefItr) {
822 unsigned deadDef = *deadDefItr;
823 LiveInterval& li = lis.getInterval(deadDef);
824 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot());
825 assert(lr != 0 && "No range for dead def?");
826 assert(lr->start == origIdx.getRegSlot() && "Bad dead range start?");
827 assert(lr->end == origIdx.getDeadSlot() && "Bad dead range end?");
828 assert(lr->valno->def == origIdx.getRegSlot() && "Bad dead valno def.");
830 t.start = miIdx.getRegSlot();
831 t.valno->def = miIdx.getRegSlot();
832 t.end = miIdx.getDeadSlot();
835 assert(intervalRangesSane(li) && "Broke live interval moving dead def.");
839 template <typename ECSetT>
840 static void handleMoveECs(LiveIntervals& lis, SlotIndex origIdx,
841 SlotIndex miIdx, const ECSetT& ecs) {
842 for (typename ECSetT::const_iterator ecItr = ecs.begin(), ecEnd = ecs.end();
843 ecItr != ecEnd; ++ecItr) {
844 unsigned ec = *ecItr;
845 LiveInterval& li = lis.getInterval(ec);
846 LiveRange* lr = li.getLiveRangeContaining(origIdx.getRegSlot(true));
847 assert(lr != 0 && "No range for early clobber?");
848 assert(lr->start == origIdx.getRegSlot(true) && "Bad EC range start?");
849 assert(lr->end == origIdx.getRegSlot() && "Bad EC range end.");
850 assert(lr->valno->def == origIdx.getRegSlot(true) && "Bad EC valno def.");
852 t.start = miIdx.getRegSlot(true);
853 t.valno->def = miIdx.getRegSlot(true);
854 t.end = miIdx.getRegSlot();
857 assert(intervalRangesSane(li) && "Broke live interval moving EC.");
861 static void moveKillFlags(unsigned reg, SlotIndex oldIdx, SlotIndex newIdx,
863 const TargetRegisterInfo& tri) {
864 MachineInstr* oldKillMI = lis.getInstructionFromIndex(oldIdx);
865 MachineInstr* newKillMI = lis.getInstructionFromIndex(newIdx);
866 assert(oldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
867 assert(!newKillMI->killsRegister(reg) && "New kill instr is already a kill.");
868 oldKillMI->clearRegisterKills(reg, &tri);
869 newKillMI->addRegisterKilled(reg, &tri);
872 template <typename UseSetT>
873 static void handleMoveUses(const MachineBasicBlock *mbb,
874 const MachineRegisterInfo& mri,
875 const TargetRegisterInfo& tri,
876 const BitVector& reservedRegs, LiveIntervals &lis,
877 SlotIndex origIdx, SlotIndex miIdx,
878 const UseSetT &uses) {
879 bool movingUp = miIdx < origIdx;
880 for (typename UseSetT::const_iterator usesItr = uses.begin(),
881 usesEnd = uses.end();
882 usesItr != usesEnd; ++usesItr) {
883 unsigned use = *usesItr;
884 if (!lis.hasInterval(use))
886 if (TargetRegisterInfo::isPhysicalRegister(use) && reservedRegs.test(use))
888 LiveInterval& li = lis.getInterval(use);
889 LiveRange* lr = li.getLiveRangeBefore(origIdx.getRegSlot());
890 assert(lr != 0 && "No range for use?");
891 bool liveThrough = lr->end > origIdx.getRegSlot();
894 // If moving up and liveThrough - nothing to do.
895 // If not live through we need to extend the range to the last use
896 // between the old location and the new one.
898 SlotIndex lastUseInRange = miIdx.getRegSlot();
899 for (MachineRegisterInfo::use_iterator useI = mri.use_begin(use),
900 useE = mri.use_end();
901 useI != useE; ++useI) {
902 const MachineInstr* mopI = &*useI;
903 const MachineOperand& mop = useI.getOperand();
904 SlotIndex instSlot = lis.getSlotIndexes()->getInstructionIndex(mopI);
905 SlotIndex opSlot = instSlot.getRegSlot(mop.isEarlyClobber());
906 if (opSlot > lastUseInRange && opSlot < origIdx)
907 lastUseInRange = opSlot;
910 // If we found a new instr endpoint update the kill flags.
911 if (lastUseInRange != miIdx.getRegSlot())
912 moveKillFlags(use, miIdx, lastUseInRange, lis, tri);
914 // Fix up the range end.
915 lr->end = lastUseInRange;
918 // Moving down is easy - the existing live range end tells us where
921 // Easy fix - just update the range endpoint.
922 lr->end = miIdx.getRegSlot();
924 bool liveOut = lr->end >= lis.getSlotIndexes()->getMBBEndIdx(mbb);
925 if (!liveOut && miIdx.getRegSlot() > lr->end) {
926 moveKillFlags(use, lr->end, miIdx, lis, tri);
927 lr->end = miIdx.getRegSlot();
931 assert(intervalRangesSane(li) && "Broke live interval moving use.");
935 void LiveIntervals::moveInstr(MachineBasicBlock::iterator insertPt,
937 MachineBasicBlock* mbb = mi->getParent();
938 assert((insertPt == mbb->end() || insertPt->getParent() == mbb) &&
939 "Cannot handle moves across basic block boundaries.");
940 assert(&*insertPt != mi && "No-op move requested?");
941 assert(!mi->isBundled() && "Can't handle bundled instructions yet.");
943 // Grab the original instruction index.
944 SlotIndex origIdx = indexes_->getInstructionIndex(mi);
946 // Move the machine instr and obtain its new index.
947 indexes_->removeMachineInstrFromMaps(mi);
948 mbb->splice(insertPt, mbb, mi);
949 SlotIndex miIdx = indexes_->insertMachineInstrInMaps(mi);
951 // Pick the direction.
952 bool movingUp = miIdx < origIdx;
954 // Collect the operands.
955 DenseSet<unsigned> uses, defs, deadDefs, ecs;
956 for (MachineInstr::mop_iterator mopItr = mi->operands_begin(),
957 mopEnd = mi->operands_end();
958 mopItr != mopEnd; ++mopItr) {
959 const MachineOperand& mop = *mopItr;
961 if (!mop.isReg() || mop.getReg() == 0)
963 unsigned reg = mop.getReg();
965 if (mop.readsReg() && !ecs.count(reg)) {
970 assert(!defs.count(reg) && "Can't mix defs with dead-defs.");
971 deadDefs.insert(reg);
972 } else if (mop.isEarlyClobber()) {
976 assert(!deadDefs.count(reg) && "Can't mix defs with dead-defs.");
982 BitVector reservedRegs(tri_->getReservedRegs(*mbb->getParent()));
985 handleMoveUses(mbb, *mri_, *tri_, reservedRegs, *this, origIdx, miIdx, uses);
986 handleMoveECs(*this, origIdx, miIdx, ecs);
987 handleMoveDeadDefs(*this, origIdx, miIdx, deadDefs);
988 handleMoveDefs(*this, origIdx, miIdx, defs);
990 handleMoveDefs(*this, origIdx, miIdx, defs);
991 handleMoveDeadDefs(*this, origIdx, miIdx, deadDefs);
992 handleMoveECs(*this, origIdx, miIdx, ecs);
993 handleMoveUses(mbb, *mri_, *tri_, reservedRegs, *this, origIdx, miIdx, uses);
997 /// getReMatImplicitUse - If the remat definition MI has one (for now, we only
998 /// allow one) virtual register operand, then its uses are implicitly using
999 /// the register. Returns the virtual register.
1000 unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
1001 MachineInstr *MI) const {
1003 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1004 MachineOperand &MO = MI->getOperand(i);
1005 if (!MO.isReg() || !MO.isUse())
1007 unsigned Reg = MO.getReg();
1008 if (Reg == 0 || Reg == li.reg)
1011 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
1012 !allocatableRegs_[Reg])
1014 RegOp = MO.getReg();
1015 break; // Found vreg operand - leave the loop.
1020 /// isValNoAvailableAt - Return true if the val# of the specified interval
1021 /// which reaches the given instruction also reaches the specified use index.
1022 bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
1023 SlotIndex UseIdx) const {
1024 VNInfo *UValNo = li.getVNInfoAt(UseIdx);
1025 return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
1028 /// isReMaterializable - Returns true if the definition MI of the specified
1029 /// val# of the specified interval is re-materializable.
1031 LiveIntervals::isReMaterializable(const LiveInterval &li,
1032 const VNInfo *ValNo, MachineInstr *MI,
1033 const SmallVectorImpl<LiveInterval*> *SpillIs,
1038 if (!tii_->isTriviallyReMaterializable(MI, aa_))
1041 // Target-specific code can mark an instruction as being rematerializable
1042 // if it has one virtual reg use, though it had better be something like
1043 // a PIC base register which is likely to be live everywhere.
1044 unsigned ImpUse = getReMatImplicitUse(li, MI);
1046 const LiveInterval &ImpLi = getInterval(ImpUse);
1047 for (MachineRegisterInfo::use_nodbg_iterator
1048 ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
1050 MachineInstr *UseMI = &*ri;
1051 SlotIndex UseIdx = getInstructionIndex(UseMI);
1052 if (li.getVNInfoAt(UseIdx) != ValNo)
1054 if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
1058 // If a register operand of the re-materialized instruction is going to
1059 // be spilled next, then it's not legal to re-materialize this instruction.
1061 for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
1062 if (ImpUse == (*SpillIs)[i]->reg)
1068 /// isReMaterializable - Returns true if every definition of MI of every
1069 /// val# of the specified interval is re-materializable.
1071 LiveIntervals::isReMaterializable(const LiveInterval &li,
1072 const SmallVectorImpl<LiveInterval*> *SpillIs,
1075 for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
1077 const VNInfo *VNI = *i;
1078 if (VNI->isUnused())
1079 continue; // Dead val#.
1080 // Is the def for the val# rematerializable?
1081 MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
1084 bool DefIsLoad = false;
1086 !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
1088 isLoad |= DefIsLoad;
1094 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
1095 // A local live range must be fully contained inside the block, meaning it is
1096 // defined and killed at instructions, not at block boundaries. It is not
1097 // live in or or out of any block.
1099 // It is technically possible to have a PHI-defined live range identical to a
1100 // single block, but we are going to return false in that case.
1102 SlotIndex Start = LI.beginIndex();
1103 if (Start.isBlock())
1106 SlotIndex Stop = LI.endIndex();
1110 // getMBBFromIndex doesn't need to search the MBB table when both indexes
1111 // belong to proper instructions.
1112 MachineBasicBlock *MBB1 = indexes_->getMBBFromIndex(Start);
1113 MachineBasicBlock *MBB2 = indexes_->getMBBFromIndex(Stop);
1114 return MBB1 == MBB2 ? MBB1 : NULL;
1118 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
1119 // Limit the loop depth ridiculousness.
1120 if (loopDepth > 200)
1123 // The loop depth is used to roughly estimate the number of times the
1124 // instruction is executed. Something like 10^d is simple, but will quickly
1125 // overflow a float. This expression behaves like 10^d for small d, but is
1126 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
1127 // headroom before overflow.
1128 // By the way, powf() might be unavailable here. For consistency,
1129 // We may take pow(double,double).
1130 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
1132 return (isDef + isUse) * lc;
1135 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
1136 MachineInstr* startInst) {
1137 LiveInterval& Interval = getOrCreateInterval(reg);
1138 VNInfo* VN = Interval.getNextValue(
1139 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
1140 getVNInfoAllocator());
1141 VN->setHasPHIKill(true);
1143 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
1144 getMBBEndIdx(startInst->getParent()), VN);
1145 Interval.addRange(LR);
1151 //===----------------------------------------------------------------------===//
1152 // Register mask functions
1153 //===----------------------------------------------------------------------===//
1155 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
1156 BitVector &UsableRegs) {
1159 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
1161 // Use a smaller arrays for local live ranges.
1162 ArrayRef<SlotIndex> Slots;
1163 ArrayRef<const uint32_t*> Bits;
1164 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
1165 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
1166 Bits = getRegMaskBitsInBlock(MBB->getNumber());
1168 Slots = getRegMaskSlots();
1169 Bits = getRegMaskBits();
1172 // We are going to enumerate all the register mask slots contained in LI.
1173 // Start with a binary search of RegMaskSlots to find a starting point.
1174 ArrayRef<SlotIndex>::iterator SlotI =
1175 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
1176 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
1178 // No slots in range, LI begins after the last call.
1184 assert(*SlotI >= LiveI->start);
1185 // Loop over all slots overlapping this segment.
1186 while (*SlotI < LiveI->end) {
1187 // *SlotI overlaps LI. Collect mask bits.
1189 // This is the first overlap. Initialize UsableRegs to all ones.
1191 UsableRegs.resize(tri_->getNumRegs(), true);
1194 // Remove usable registers clobbered by this mask.
1195 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
1196 if (++SlotI == SlotE)
1199 // *SlotI is beyond the current LI segment.
1200 LiveI = LI.advanceTo(LiveI, *SlotI);
1203 // Advance SlotI until it overlaps.
1204 while (*SlotI < LiveI->start)
1205 if (++SlotI == SlotE)