1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineDominators.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/DenseSet.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "LiveRangeCalc.h"
37 #include "VirtRegMap.h"
43 // Switch to the new experimental algorithm for computing live intervals.
45 NewLiveIntervals("new-live-intervals", cl::Hidden,
46 cl::desc("Use new algorithm forcomputing live intervals"));
48 char LiveIntervals::ID = 0;
49 char &llvm::LiveIntervalsID = LiveIntervals::ID;
50 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
51 "Live Interval Analysis", false, false)
52 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
53 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
54 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
55 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
56 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
57 "Live Interval Analysis", false, false)
59 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<AliasAnalysis>();
62 AU.addPreserved<AliasAnalysis>();
63 AU.addRequired<LiveVariables>();
64 AU.addPreserved<LiveVariables>();
65 AU.addPreservedID(MachineLoopInfoID);
66 AU.addRequiredTransitiveID(MachineDominatorsID);
67 AU.addPreservedID(MachineDominatorsID);
68 AU.addPreserved<SlotIndexes>();
69 AU.addRequiredTransitive<SlotIndexes>();
70 MachineFunctionPass::getAnalysisUsage(AU);
73 LiveIntervals::LiveIntervals() : MachineFunctionPass(ID),
74 DomTree(0), LRCalc(0) {
75 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
78 LiveIntervals::~LiveIntervals() {
82 void LiveIntervals::releaseMemory() {
83 // Free the live intervals themselves.
84 for (unsigned i = 0, e = VirtRegIntervals.size(); i != e; ++i)
85 delete VirtRegIntervals[TargetRegisterInfo::index2VirtReg(i)];
86 VirtRegIntervals.clear();
89 RegMaskBlocks.clear();
91 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
92 delete RegUnitIntervals[i];
93 RegUnitIntervals.clear();
95 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
96 VNInfoAllocator.Reset();
99 /// runOnMachineFunction - Register allocate the whole function
101 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
103 MRI = &MF->getRegInfo();
104 TM = &fn.getTarget();
105 TRI = TM->getRegisterInfo();
106 TII = TM->getInstrInfo();
107 AA = &getAnalysis<AliasAnalysis>();
108 LV = &getAnalysis<LiveVariables>();
109 Indexes = &getAnalysis<SlotIndexes>();
110 DomTree = &getAnalysis<MachineDominatorTree>();
112 LRCalc = new LiveRangeCalc();
114 // Allocate space for all virtual registers.
115 VirtRegIntervals.resize(MRI->getNumVirtRegs());
117 if (NewLiveIntervals) {
118 // This is the new way of computing live intervals.
119 // It is independent of LiveVariables, and it can run at any time.
123 // This is the old way of computing live intervals.
124 // It depends on LiveVariables.
127 computeLiveInRegUnits();
133 /// print - Implement the dump method.
134 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
135 OS << "********** INTERVALS **********\n";
137 // Dump the regunits.
138 for (unsigned i = 0, e = RegUnitIntervals.size(); i != e; ++i)
139 if (LiveInterval *LI = RegUnitIntervals[i])
140 OS << PrintRegUnit(i, TRI) << " = " << *LI << '\n';
142 // Dump the virtregs.
143 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
144 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
145 if (hasInterval(Reg))
146 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n';
152 void LiveIntervals::printInstrs(raw_ostream &OS) const {
153 OS << "********** MACHINEINSTRS **********\n";
154 MF->print(OS, Indexes);
157 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
158 void LiveIntervals::dumpInstrs() const {
164 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
165 unsigned Reg = MI.getOperand(MOIdx).getReg();
166 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
167 const MachineOperand &MO = MI.getOperand(i);
170 if (MO.getReg() == Reg && MO.isDef()) {
171 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
172 MI.getOperand(MOIdx).getSubReg() &&
173 (MO.getSubReg() || MO.isImplicit()));
180 /// isPartialRedef - Return true if the specified def at the specific index is
181 /// partially re-defining the specified live interval. A common case of this is
182 /// a definition of the sub-register.
183 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
184 LiveInterval &interval) {
185 if (!MO.getSubReg() || MO.isEarlyClobber())
188 SlotIndex RedefIndex = MIIdx.getRegSlot();
189 const LiveRange *OldLR =
190 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
191 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
193 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
198 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
199 MachineBasicBlock::iterator mi,
203 LiveInterval &interval) {
204 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, TRI));
206 // Virtual registers may be defined multiple times (due to phi
207 // elimination and 2-addr elimination). Much of what we do only has to be
208 // done once for the vreg. We use an empty interval to detect the first
209 // time we see a vreg.
210 LiveVariables::VarInfo& vi = LV->getVarInfo(interval.reg);
211 if (interval.empty()) {
212 // Get the Idx of the defining instructions.
213 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
215 // Make sure the first definition is not a partial redefinition.
216 assert(!MO.readsReg() && "First def cannot also read virtual register "
217 "missing <undef> flag?");
219 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
220 assert(ValNo->id == 0 && "First value in interval is not 0?");
222 // Loop over all of the blocks that the vreg is defined in. There are
223 // two cases we have to handle here. The most common case is a vreg
224 // whose lifetime is contained within a basic block. In this case there
225 // will be a single kill, in MBB, which comes after the definition.
226 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
227 // FIXME: what about dead vars?
229 if (vi.Kills[0] != mi)
230 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
232 killIdx = defIndex.getDeadSlot();
234 // If the kill happens after the definition, we have an intra-block
236 if (killIdx > defIndex) {
237 assert(vi.AliveBlocks.empty() &&
238 "Shouldn't be alive across any blocks!");
239 LiveRange LR(defIndex, killIdx, ValNo);
240 interval.addRange(LR);
241 DEBUG(dbgs() << " +" << LR << "\n");
246 // The other case we handle is when a virtual register lives to the end
247 // of the defining block, potentially live across some blocks, then is
248 // live into some number of blocks, but gets killed. Start by adding a
249 // range that goes from this definition to the end of the defining block.
250 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
251 DEBUG(dbgs() << " +" << NewLR);
252 interval.addRange(NewLR);
254 bool PHIJoin = LV->isPHIJoin(interval.reg);
257 // A phi join register is killed at the end of the MBB and revived as a
258 // new valno in the killing blocks.
259 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
260 DEBUG(dbgs() << " phi-join");
262 // Iterate over all of the blocks that the variable is completely
263 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
265 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
266 E = vi.AliveBlocks.end(); I != E; ++I) {
267 MachineBasicBlock *aliveBlock = MF->getBlockNumbered(*I);
268 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock),
270 interval.addRange(LR);
271 DEBUG(dbgs() << " +" << LR);
275 // Finally, this virtual register is live from the start of any killing
276 // block to the 'use' slot of the killing instruction.
277 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
278 MachineInstr *Kill = vi.Kills[i];
279 SlotIndex Start = getMBBStartIdx(Kill->getParent());
280 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
282 // Create interval with one of a NEW value number. Note that this value
283 // number isn't actually defined by an instruction, weird huh? :)
285 assert(getInstructionFromIndex(Start) == 0 &&
286 "PHI def index points at actual instruction.");
287 ValNo = interval.getNextValue(Start, VNInfoAllocator);
289 LiveRange LR(Start, killIdx, ValNo);
290 interval.addRange(LR);
291 DEBUG(dbgs() << " +" << LR);
295 if (MultipleDefsBySameMI(*mi, MOIdx))
296 // Multiple defs of the same virtual register by the same instruction.
297 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
298 // This is likely due to elimination of REG_SEQUENCE instructions. Return
299 // here since there is nothing to do.
302 // If this is the second time we see a virtual register definition, it
303 // must be due to phi elimination or two addr elimination. If this is
304 // the result of two address elimination, then the vreg is one of the
305 // def-and-use register operand.
307 // It may also be partial redef like this:
308 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
309 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
310 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
311 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
312 // If this is a two-address definition, then we have already processed
313 // the live range. The only problem is that we didn't realize there
314 // are actually two values in the live interval. Because of this we
315 // need to take the LiveRegion that defines this register and split it
317 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
319 const LiveRange *OldLR =
320 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
321 VNInfo *OldValNo = OldLR->valno;
322 SlotIndex DefIndex = OldValNo->def.getRegSlot();
324 // Delete the previous value, which should be short and continuous,
325 // because the 2-addr copy must be in the same MBB as the redef.
326 interval.removeRange(DefIndex, RedefIndex);
328 // The new value number (#1) is defined by the instruction we claimed
330 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
332 // Value#0 is now defined by the 2-addr instruction.
333 OldValNo->def = RedefIndex;
335 // Add the new live interval which replaces the range for the input copy.
336 LiveRange LR(DefIndex, RedefIndex, ValNo);
337 DEBUG(dbgs() << " replace range with " << LR);
338 interval.addRange(LR);
340 // If this redefinition is dead, we need to add a dummy unit live
341 // range covering the def slot.
343 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
346 DEBUG(dbgs() << " RESULT: " << interval);
347 } else if (LV->isPHIJoin(interval.reg)) {
348 // In the case of PHI elimination, each variable definition is only
349 // live until the end of the block. We've already taken care of the
350 // rest of the live range.
352 SlotIndex defIndex = MIIdx.getRegSlot();
353 if (MO.isEarlyClobber())
354 defIndex = MIIdx.getRegSlot(true);
356 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
358 SlotIndex killIndex = getMBBEndIdx(mbb);
359 LiveRange LR(defIndex, killIndex, ValNo);
360 interval.addRange(LR);
361 DEBUG(dbgs() << " phi-join +" << LR);
363 llvm_unreachable("Multiply defined register");
367 DEBUG(dbgs() << '\n');
370 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
371 MachineBasicBlock::iterator MI,
375 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
376 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
377 getOrCreateInterval(MO.getReg()));
380 /// computeIntervals - computes the live intervals for virtual
381 /// registers. for some ordering of the machine instructions [1,N] a
382 /// live interval is an interval [i, j) where 1 <= i <= j < N for
383 /// which a variable is live
384 void LiveIntervals::computeIntervals() {
385 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
386 << "********** Function: " << MF->getName() << '\n');
388 RegMaskBlocks.resize(MF->getNumBlockIDs());
390 SmallVector<unsigned, 8> UndefUses;
391 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
393 MachineBasicBlock *MBB = MBBI;
394 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
399 // Track the index of the current machine instr.
400 SlotIndex MIIndex = getMBBStartIdx(MBB);
401 DEBUG(dbgs() << "BB#" << MBB->getNumber()
402 << ":\t\t# derived from " << MBB->getName() << "\n");
404 // Skip over empty initial indices.
405 if (getInstructionFromIndex(MIIndex) == 0)
406 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
408 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
410 DEBUG(dbgs() << MIIndex << "\t" << *MI);
411 if (MI->isDebugValue())
413 assert(Indexes->getInstructionFromIndex(MIIndex) == MI &&
414 "Lost SlotIndex synchronization");
417 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
418 MachineOperand &MO = MI->getOperand(i);
420 // Collect register masks.
421 if (MO.isRegMask()) {
422 RegMaskSlots.push_back(MIIndex.getRegSlot());
423 RegMaskBits.push_back(MO.getRegMask());
427 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
430 // handle register defs - build intervals
432 handleRegisterDef(MBB, MI, MIIndex, MO, i);
433 else if (MO.isUndef())
434 UndefUses.push_back(MO.getReg());
437 // Move to the next instr slot.
438 MIIndex = Indexes->getNextNonNullIndex(MIIndex);
441 // Compute the number of register mask instructions in this block.
442 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
443 RMB.second = RegMaskSlots.size() - RMB.first;
446 // Create empty intervals for registers defined by implicit_def's (except
447 // for those implicit_def that define values which are liveout of their
449 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
450 unsigned UndefReg = UndefUses[i];
451 (void)getOrCreateInterval(UndefReg);
455 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
456 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
457 return new LiveInterval(reg, Weight);
461 /// computeVirtRegInterval - Compute the live interval of a virtual register,
462 /// based on defs and uses.
463 void LiveIntervals::computeVirtRegInterval(LiveInterval *LI) {
464 assert(LRCalc && "LRCalc not initialized.");
465 assert(LI->empty() && "Should only compute empty intervals.");
466 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
467 LRCalc->createDeadDefs(LI);
468 LRCalc->extendToUses(LI);
471 void LiveIntervals::computeVirtRegs() {
472 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
473 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
474 if (MRI->reg_nodbg_empty(Reg))
476 LiveInterval *LI = createInterval(Reg);
477 VirtRegIntervals[Reg] = LI;
478 computeVirtRegInterval(LI);
482 void LiveIntervals::computeRegMasks() {
483 RegMaskBlocks.resize(MF->getNumBlockIDs());
485 // Find all instructions with regmask operands.
486 for (MachineFunction::iterator MBBI = MF->begin(), E = MF->end();
488 MachineBasicBlock *MBB = MBBI;
489 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
490 RMB.first = RegMaskSlots.size();
491 for (MachineBasicBlock::iterator MI = MBB->begin(), ME = MBB->end();
493 for (MIOperands MO(MI); MO.isValid(); ++MO) {
494 if (!MO->isRegMask())
496 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
497 RegMaskBits.push_back(MO->getRegMask());
499 // Compute the number of register mask instructions in this block.
500 RMB.second = RegMaskSlots.size() - RMB.first;
504 //===----------------------------------------------------------------------===//
505 // Register Unit Liveness
506 //===----------------------------------------------------------------------===//
508 // Fixed interference typically comes from ABI boundaries: Function arguments
509 // and return values are passed in fixed registers, and so are exception
510 // pointers entering landing pads. Certain instructions require values to be
511 // present in specific registers. That is also represented through fixed
515 /// computeRegUnitInterval - Compute the live interval of a register unit, based
516 /// on the uses and defs of aliasing registers. The interval should be empty,
517 /// or contain only dead phi-defs from ABI blocks.
518 void LiveIntervals::computeRegUnitInterval(LiveInterval *LI) {
519 unsigned Unit = LI->reg;
521 assert(LRCalc && "LRCalc not initialized.");
522 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
524 // The physregs aliasing Unit are the roots and their super-registers.
525 // Create all values as dead defs before extending to uses. Note that roots
526 // may share super-registers. That's OK because createDeadDefs() is
527 // idempotent. It is very rare for a register unit to have multiple roots, so
528 // uniquing super-registers is probably not worthwhile.
529 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
530 unsigned Root = *Roots;
531 if (!MRI->reg_empty(Root))
532 LRCalc->createDeadDefs(LI, Root);
533 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
534 if (!MRI->reg_empty(*Supers))
535 LRCalc->createDeadDefs(LI, *Supers);
539 // Now extend LI to reach all uses.
540 // Ignore uses of reserved registers. We only track defs of those.
541 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
542 unsigned Root = *Roots;
543 if (!MRI->isReserved(Root) && !MRI->reg_empty(Root))
544 LRCalc->extendToUses(LI, Root);
545 for (MCSuperRegIterator Supers(Root, TRI); Supers.isValid(); ++Supers) {
546 unsigned Reg = *Supers;
547 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg))
548 LRCalc->extendToUses(LI, Reg);
554 /// computeLiveInRegUnits - Precompute the live ranges of any register units
555 /// that are live-in to an ABI block somewhere. Register values can appear
556 /// without a corresponding def when entering the entry block or a landing pad.
558 void LiveIntervals::computeLiveInRegUnits() {
559 RegUnitIntervals.resize(TRI->getNumRegUnits());
560 DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
562 // Keep track of the intervals allocated.
563 SmallVector<LiveInterval*, 8> NewIntvs;
565 // Check all basic blocks for live-ins.
566 for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
568 const MachineBasicBlock *MBB = MFI;
570 // We only care about ABI blocks: Entry + landing pads.
571 if ((MFI != MF->begin() && !MBB->isLandingPad()) || MBB->livein_empty())
574 // Create phi-defs at Begin for all live-in registers.
575 SlotIndex Begin = Indexes->getMBBStartIdx(MBB);
576 DEBUG(dbgs() << Begin << "\tBB#" << MBB->getNumber());
577 for (MachineBasicBlock::livein_iterator LII = MBB->livein_begin(),
578 LIE = MBB->livein_end(); LII != LIE; ++LII) {
579 for (MCRegUnitIterator Units(*LII, TRI); Units.isValid(); ++Units) {
580 unsigned Unit = *Units;
581 LiveInterval *Intv = RegUnitIntervals[Unit];
583 Intv = RegUnitIntervals[Unit] = new LiveInterval(Unit, HUGE_VALF);
584 NewIntvs.push_back(Intv);
586 VNInfo *VNI = Intv->createDeadDef(Begin, getVNInfoAllocator());
588 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << '#' << VNI->id);
591 DEBUG(dbgs() << '\n');
593 DEBUG(dbgs() << "Created " << NewIntvs.size() << " new intervals.\n");
595 // Compute the 'normal' part of the intervals.
596 for (unsigned i = 0, e = NewIntvs.size(); i != e; ++i)
597 computeRegUnitInterval(NewIntvs[i]);
601 /// shrinkToUses - After removing some uses of a register, shrink its live
602 /// range to just the remaining uses. This method does not compute reaching
603 /// defs for new uses, and it doesn't remove dead defs.
604 bool LiveIntervals::shrinkToUses(LiveInterval *li,
605 SmallVectorImpl<MachineInstr*> *dead) {
606 DEBUG(dbgs() << "Shrink: " << *li << '\n');
607 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
608 && "Can only shrink virtual registers");
609 // Find all the values used, including PHI kills.
610 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
612 // Blocks that have already been added to WorkList as live-out.
613 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
615 // Visit all instructions reading li->reg.
616 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(li->reg);
617 MachineInstr *UseMI = I.skipInstruction();) {
618 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
620 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
621 LiveRangeQuery LRQ(*li, Idx);
622 VNInfo *VNI = LRQ.valueIn();
624 // This shouldn't happen: readsVirtualRegister returns true, but there is
625 // no live value. It is likely caused by a target getting <undef> flags
627 DEBUG(dbgs() << Idx << '\t' << *UseMI
628 << "Warning: Instr claims to read non-existent value in "
632 // Special case: An early-clobber tied operand reads and writes the
633 // register one slot early.
634 if (VNInfo *DefVNI = LRQ.valueDefined())
637 WorkList.push_back(std::make_pair(Idx, VNI));
640 // Create a new live interval with only minimal live segments per def.
641 LiveInterval NewLI(li->reg, 0);
642 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
647 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
650 // Keep track of the PHIs that are in use.
651 SmallPtrSet<VNInfo*, 8> UsedPHIs;
653 // Extend intervals to reach all uses in WorkList.
654 while (!WorkList.empty()) {
655 SlotIndex Idx = WorkList.back().first;
656 VNInfo *VNI = WorkList.back().second;
658 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
659 SlotIndex BlockStart = getMBBStartIdx(MBB);
661 // Extend the live range for VNI to be live at Idx.
662 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
664 assert(ExtVNI == VNI && "Unexpected existing value number");
665 // Is this a PHIDef we haven't seen before?
666 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
668 // The PHI is live, make sure the predecessors are live-out.
669 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
670 PE = MBB->pred_end(); PI != PE; ++PI) {
671 if (!LiveOut.insert(*PI))
673 SlotIndex Stop = getMBBEndIdx(*PI);
674 // A predecessor is not required to have a live-out value for a PHI.
675 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
676 WorkList.push_back(std::make_pair(Stop, PVNI));
681 // VNI is live-in to MBB.
682 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
683 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
685 // Make sure VNI is live-out from the predecessors.
686 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
687 PE = MBB->pred_end(); PI != PE; ++PI) {
688 if (!LiveOut.insert(*PI))
690 SlotIndex Stop = getMBBEndIdx(*PI);
691 assert(li->getVNInfoBefore(Stop) == VNI &&
692 "Wrong value out of predecessor");
693 WorkList.push_back(std::make_pair(Stop, VNI));
697 // Handle dead values.
698 bool CanSeparate = false;
699 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
704 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
705 assert(LII != NewLI.end() && "Missing live range for PHI");
706 if (LII->end != VNI->def.getDeadSlot())
708 if (VNI->isPHIDef()) {
709 // This is a dead PHI. Remove it.
711 NewLI.removeRange(*LII);
712 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
715 // This is a dead def. Make sure the instruction knows.
716 MachineInstr *MI = getInstructionFromIndex(VNI->def);
717 assert(MI && "No instruction defining live value");
718 MI->addRegisterDead(li->reg, TRI);
719 if (dead && MI->allDefsAreDead()) {
720 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
726 // Move the trimmed ranges back.
727 li->ranges.swap(NewLI.ranges);
728 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
732 void LiveIntervals::extendToIndices(LiveInterval *LI,
733 ArrayRef<SlotIndex> Indices) {
734 assert(LRCalc && "LRCalc not initialized.");
735 LRCalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
736 for (unsigned i = 0, e = Indices.size(); i != e; ++i)
737 LRCalc->extend(LI, Indices[i]);
740 void LiveIntervals::pruneValue(LiveInterval *LI, SlotIndex Kill,
741 SmallVectorImpl<SlotIndex> *EndPoints) {
742 LiveRangeQuery LRQ(*LI, Kill);
743 VNInfo *VNI = LRQ.valueOut();
747 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
748 SlotIndex MBBStart, MBBEnd;
749 tie(MBBStart, MBBEnd) = Indexes->getMBBRange(KillMBB);
751 // If VNI isn't live out from KillMBB, the value is trivially pruned.
752 if (LRQ.endPoint() < MBBEnd) {
753 LI->removeRange(Kill, LRQ.endPoint());
754 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
758 // VNI is live out of KillMBB.
759 LI->removeRange(Kill, MBBEnd);
760 if (EndPoints) EndPoints->push_back(MBBEnd);
762 // Find all blocks that are reachable from KillMBB without leaving VNI's live
763 // range. It is possible that KillMBB itself is reachable, so start a DFS
764 // from each successor.
765 typedef SmallPtrSet<MachineBasicBlock*, 9> VisitedTy;
767 for (MachineBasicBlock::succ_iterator
768 SuccI = KillMBB->succ_begin(), SuccE = KillMBB->succ_end();
769 SuccI != SuccE; ++SuccI) {
770 for (df_ext_iterator<MachineBasicBlock*, VisitedTy>
771 I = df_ext_begin(*SuccI, Visited), E = df_ext_end(*SuccI, Visited);
773 MachineBasicBlock *MBB = *I;
775 // Check if VNI is live in to MBB.
776 tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
777 LiveRangeQuery LRQ(*LI, MBBStart);
778 if (LRQ.valueIn() != VNI) {
779 // This block isn't part of the VNI live range. Prune the search.
784 // Prune the search if VNI is killed in MBB.
785 if (LRQ.endPoint() < MBBEnd) {
786 LI->removeRange(MBBStart, LRQ.endPoint());
787 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
792 // VNI is live through MBB.
793 LI->removeRange(MBBStart, MBBEnd);
794 if (EndPoints) EndPoints->push_back(MBBEnd);
800 //===----------------------------------------------------------------------===//
801 // Register allocator hooks.
804 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
805 // Keep track of regunit ranges.
806 SmallVector<std::pair<LiveInterval*, LiveInterval::iterator>, 8> RU;
808 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
809 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
810 if (MRI->reg_nodbg_empty(Reg))
812 LiveInterval *LI = &getInterval(Reg);
816 // Find the regunit intervals for the assigned register. They may overlap
817 // the virtual register live range, cancelling any kills.
819 for (MCRegUnitIterator Units(VRM->getPhys(Reg), TRI); Units.isValid();
821 LiveInterval *RUInt = &getRegUnit(*Units);
824 RU.push_back(std::make_pair(RUInt, RUInt->find(LI->begin()->end)));
827 // Every instruction that kills Reg corresponds to a live range end point.
828 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
830 // A block index indicates an MBB edge.
831 if (RI->end.isBlock())
833 MachineInstr *MI = getInstructionFromIndex(RI->end);
837 // Check if any of the reguints are live beyond the end of RI. That could
838 // happen when a physreg is defined as a copy of a virtreg:
840 // %EAX = COPY %vreg5
841 // FOO %vreg5 <--- MI, cancel kill because %EAX is live.
844 // There should be no kill flag on FOO when %vreg5 is rewritten as %EAX.
845 bool CancelKill = false;
846 for (unsigned u = 0, e = RU.size(); u != e; ++u) {
847 LiveInterval *RInt = RU[u].first;
848 LiveInterval::iterator &I = RU[u].second;
849 if (I == RInt->end())
851 I = RInt->advanceTo(I, RI->end);
852 if (I == RInt->end() || I->start >= RI->end)
854 // I is overlapping RI.
859 MI->clearRegisterKills(Reg, NULL);
861 MI->addRegisterKilled(Reg, NULL);
867 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
868 // A local live range must be fully contained inside the block, meaning it is
869 // defined and killed at instructions, not at block boundaries. It is not
870 // live in or or out of any block.
872 // It is technically possible to have a PHI-defined live range identical to a
873 // single block, but we are going to return false in that case.
875 SlotIndex Start = LI.beginIndex();
879 SlotIndex Stop = LI.endIndex();
883 // getMBBFromIndex doesn't need to search the MBB table when both indexes
884 // belong to proper instructions.
885 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
886 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
887 return MBB1 == MBB2 ? MBB1 : NULL;
891 LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
892 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
894 const VNInfo *PHI = *I;
895 if (PHI->isUnused() || !PHI->isPHIDef())
897 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
898 // Conservatively return true instead of scanning huge predecessor lists.
899 if (PHIMBB->pred_size() > 100)
901 for (MachineBasicBlock::const_pred_iterator
902 PI = PHIMBB->pred_begin(), PE = PHIMBB->pred_end(); PI != PE; ++PI)
903 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(*PI)))
910 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
911 // Limit the loop depth ridiculousness.
915 // The loop depth is used to roughly estimate the number of times the
916 // instruction is executed. Something like 10^d is simple, but will quickly
917 // overflow a float. This expression behaves like 10^d for small d, but is
918 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
919 // headroom before overflow.
920 // By the way, powf() might be unavailable here. For consistency,
921 // We may take pow(double,double).
922 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
924 return (isDef + isUse) * lc;
927 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
928 MachineInstr* startInst) {
929 LiveInterval& Interval = getOrCreateInterval(reg);
930 VNInfo* VN = Interval.getNextValue(
931 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
932 getVNInfoAllocator());
934 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
935 getMBBEndIdx(startInst->getParent()), VN);
936 Interval.addRange(LR);
942 //===----------------------------------------------------------------------===//
943 // Register mask functions
944 //===----------------------------------------------------------------------===//
946 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
947 BitVector &UsableRegs) {
950 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
952 // Use a smaller arrays for local live ranges.
953 ArrayRef<SlotIndex> Slots;
954 ArrayRef<const uint32_t*> Bits;
955 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
956 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
957 Bits = getRegMaskBitsInBlock(MBB->getNumber());
959 Slots = getRegMaskSlots();
960 Bits = getRegMaskBits();
963 // We are going to enumerate all the register mask slots contained in LI.
964 // Start with a binary search of RegMaskSlots to find a starting point.
965 ArrayRef<SlotIndex>::iterator SlotI =
966 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
967 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
969 // No slots in range, LI begins after the last call.
975 assert(*SlotI >= LiveI->start);
976 // Loop over all slots overlapping this segment.
977 while (*SlotI < LiveI->end) {
978 // *SlotI overlaps LI. Collect mask bits.
980 // This is the first overlap. Initialize UsableRegs to all ones.
982 UsableRegs.resize(TRI->getNumRegs(), true);
985 // Remove usable registers clobbered by this mask.
986 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
987 if (++SlotI == SlotE)
990 // *SlotI is beyond the current LI segment.
991 LiveI = LI.advanceTo(LiveI, *SlotI);
994 // Advance SlotI until it overlaps.
995 while (*SlotI < LiveI->start)
996 if (++SlotI == SlotE)
1001 //===----------------------------------------------------------------------===//
1002 // IntervalUpdate class.
1003 //===----------------------------------------------------------------------===//
1005 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1006 class LiveIntervals::HMEditor {
1009 const MachineRegisterInfo& MRI;
1010 const TargetRegisterInfo& TRI;
1013 SmallPtrSet<LiveInterval*, 8> Updated;
1016 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1017 const TargetRegisterInfo& TRI,
1018 SlotIndex OldIdx, SlotIndex NewIdx)
1019 : LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx) {}
1021 /// Update all live ranges touched by MI, assuming a move from OldIdx to
1023 void updateAllRanges(MachineInstr *MI) {
1024 DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
1025 bool hasRegMask = false;
1026 for (MIOperands MO(MI); MO.isValid(); ++MO) {
1027 if (MO->isRegMask())
1031 // Aggressively clear all kill flags.
1032 // They are reinserted by VirtRegRewriter.
1034 MO->setIsKill(false);
1036 unsigned Reg = MO->getReg();
1039 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1040 updateRange(LIS.getInterval(Reg));
1044 // For physregs, only update the regunits that actually have a
1045 // precomputed live range.
1046 for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
1047 if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
1051 updateRegMaskSlots();
1055 /// Update a single live range, assuming an instruction has been moved from
1056 /// OldIdx to NewIdx.
1057 void updateRange(LiveInterval &LI) {
1058 if (!Updated.insert(&LI))
1062 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
1063 dbgs() << PrintReg(LI.reg);
1065 dbgs() << PrintRegUnit(LI.reg, &TRI);
1066 dbgs() << ":\t" << LI << '\n';
1068 if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
1072 DEBUG(dbgs() << " -->\t" << LI << '\n');
1076 /// Update LI to reflect an instruction has been moved downwards from OldIdx
1079 /// 1. Live def at OldIdx:
1080 /// Move def to NewIdx, assert endpoint after NewIdx.
1082 /// 2. Live def at OldIdx, killed at NewIdx:
1083 /// Change to dead def at NewIdx.
1084 /// (Happens when bundling def+kill together).
1086 /// 3. Dead def at OldIdx:
1087 /// Move def to NewIdx, possibly across another live value.
1089 /// 4. Def at OldIdx AND at NewIdx:
1090 /// Remove live range [OldIdx;NewIdx) and value defined at OldIdx.
1091 /// (Happens when bundling multiple defs together).
1093 /// 5. Value read at OldIdx, killed before NewIdx:
1094 /// Extend kill to NewIdx.
1096 void handleMoveDown(LiveInterval &LI) {
1097 // First look for a kill at OldIdx.
1098 LiveInterval::iterator I = LI.find(OldIdx.getBaseIndex());
1099 LiveInterval::iterator E = LI.end();
1100 // Is LI even live at OldIdx?
1101 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1104 // Handle a live-in value.
1105 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1106 bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
1107 // If the live-in value already extends to NewIdx, there is nothing to do.
1108 if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
1110 // Aggressively remove all kill flags from the old kill point.
1111 // Kill flags shouldn't be used while live intervals exist, they will be
1112 // reinserted by VirtRegRewriter.
1113 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
1114 for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
1115 if (MO->isReg() && MO->isUse())
1116 MO->setIsKill(false);
1117 // Adjust I->end to reach NewIdx. This may temporarily make LI invalid by
1118 // overlapping ranges. Case 5 above.
1119 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1120 // If this was a kill, there may also be a def. Otherwise we're done.
1126 // Check for a def at OldIdx.
1127 if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
1129 // We have a def at OldIdx.
1130 VNInfo *DefVNI = I->valno;
1131 assert(DefVNI->def == I->start && "Inconsistent def");
1132 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1133 // If the defined value extends beyond NewIdx, just move the def down.
1134 // This is case 1 above.
1135 if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
1136 I->start = DefVNI->def;
1139 // The remaining possibilities are now:
1140 // 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
1141 // 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
1142 // In either case, it is possible that there is an existing def at NewIdx.
1143 assert((I->end == OldIdx.getDeadSlot() ||
1144 SlotIndex::isSameInstr(I->end, NewIdx)) &&
1145 "Cannot move def below kill");
1146 LiveInterval::iterator NewI = LI.advanceTo(I, NewIdx.getRegSlot());
1147 if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1148 // There is an existing def at NewIdx, case 4 above. The def at OldIdx is
1149 // coalesced into that value.
1150 assert(NewI->valno != DefVNI && "Multiple defs of value?");
1151 LI.removeValNo(DefVNI);
1154 // There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
1155 // If the def at OldIdx was dead, we allow it to be moved across other LI
1156 // values. The new range should be placed immediately before NewI, move any
1157 // intermediate ranges up.
1158 assert(NewI != I && "Inconsistent iterators");
1159 std::copy(llvm::next(I), NewI, I);
1160 *llvm::prior(NewI) = LiveRange(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1163 /// Update LI to reflect an instruction has been moved upwards from OldIdx
1166 /// 1. Live def at OldIdx:
1167 /// Hoist def to NewIdx.
1169 /// 2. Dead def at OldIdx:
1170 /// Hoist def+end to NewIdx, possibly move across other values.
1172 /// 3. Dead def at OldIdx AND existing def at NewIdx:
1173 /// Remove value defined at OldIdx, coalescing it with existing value.
1175 /// 4. Live def at OldIdx AND existing def at NewIdx:
1176 /// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
1177 /// (Happens when bundling multiple defs together).
1179 /// 5. Value killed at OldIdx:
1180 /// Hoist kill to NewIdx, then scan for last kill between NewIdx and
1183 void handleMoveUp(LiveInterval &LI) {
1184 // First look for a kill at OldIdx.
1185 LiveInterval::iterator I = LI.find(OldIdx.getBaseIndex());
1186 LiveInterval::iterator E = LI.end();
1187 // Is LI even live at OldIdx?
1188 if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
1191 // Handle a live-in value.
1192 if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
1193 // If the live-in value isn't killed here, there is nothing to do.
1194 if (!SlotIndex::isSameInstr(OldIdx, I->end))
1196 // Adjust I->end to end at NewIdx. If we are hoisting a kill above
1197 // another use, we need to search for that use. Case 5 above.
1198 I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
1200 // If OldIdx also defines a value, there couldn't have been another use.
1201 if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
1202 // No def, search for the new kill.
1203 // This can never be an early clobber kill since there is no def.
1204 llvm::prior(I)->end = findLastUseBefore(LI.reg).getRegSlot();
1209 // Now deal with the def at OldIdx.
1210 assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
1211 VNInfo *DefVNI = I->valno;
1212 assert(DefVNI->def == I->start && "Inconsistent def");
1213 DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
1215 // Check for an existing def at NewIdx.
1216 LiveInterval::iterator NewI = LI.find(NewIdx.getRegSlot());
1217 if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
1218 assert(NewI->valno != DefVNI && "Same value defined more than once?");
1219 // There is an existing def at NewIdx.
1220 if (I->end.isDead()) {
1221 // Case 3: Remove the dead def at OldIdx.
1222 LI.removeValNo(DefVNI);
1225 // Case 4: Replace def at NewIdx with live def at OldIdx.
1226 I->start = DefVNI->def;
1227 LI.removeValNo(NewI->valno);
1231 // There is no existing def at NewIdx. Hoist DefVNI.
1232 if (!I->end.isDead()) {
1233 // Leave the end point of a live def.
1234 I->start = DefVNI->def;
1238 // DefVNI is a dead def. It may have been moved across other values in LI,
1239 // so move I up to NewI. Slide [NewI;I) down one position.
1240 std::copy_backward(NewI, I, llvm::next(I));
1241 *NewI = LiveRange(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
1244 void updateRegMaskSlots() {
1245 SmallVectorImpl<SlotIndex>::iterator RI =
1246 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1248 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1250 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1251 "RegSlots out of order. Did you move one call across another?");
1254 // Return the last use of reg between NewIdx and OldIdx.
1255 SlotIndex findLastUseBefore(unsigned Reg) {
1256 SlotIndex LastUse = NewIdx;
1258 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1259 for (MachineRegisterInfo::use_nodbg_iterator
1260 UI = MRI.use_nodbg_begin(Reg),
1261 UE = MRI.use_nodbg_end();
1262 UI != UE; UI.skipInstruction()) {
1263 const MachineInstr* MI = &*UI;
1264 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1265 if (InstSlot > LastUse && InstSlot < OldIdx)
1269 MachineInstr* MI = LIS.getSlotIndexes()->getInstructionFromIndex(NewIdx);
1270 MachineBasicBlock::iterator MII(MI);
1272 MachineBasicBlock* MBB = MI->getParent();
1273 for (; MII != MBB->end() && LIS.getInstructionIndex(MII) < OldIdx; ++MII){
1274 for (MachineInstr::mop_iterator MOI = MII->operands_begin(),
1275 MOE = MII->operands_end();
1276 MOI != MOE; ++MOI) {
1277 const MachineOperand& mop = *MOI;
1278 if (!mop.isReg() || mop.getReg() == 0 ||
1279 TargetRegisterInfo::isVirtualRegister(mop.getReg()))
1282 if (TRI.hasRegUnit(mop.getReg(), Reg))
1283 LastUse = LIS.getInstructionIndex(MII);
1291 void LiveIntervals::handleMove(MachineInstr* MI) {
1292 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1293 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1294 Indexes->removeMachineInstrFromMaps(MI);
1295 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1296 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1297 OldIndex < getMBBEndIdx(MI->getParent()) &&
1298 "Cannot handle moves across basic block boundaries.");
1300 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex);
1301 HME.updateAllRanges(MI);
1304 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
1305 MachineInstr* BundleStart) {
1306 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1307 SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
1308 HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex);
1309 HME.updateAllRanges(MI);