1 //===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass which is used
11 // by the Linear Scan Register allocator. This pass linearizes the
12 // basic blocks of the function in DFS order and uses the
13 // LiveVariables pass to conservatively compute live intervals for
14 // each virtual and physical register.
16 //===----------------------------------------------------------------------===//
18 #define DEBUG_TYPE "regalloc"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/Value.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/CodeGen/LiveVariables.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/Target/TargetRegisterInfo.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/ADT/DenseSet.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
41 // Hidden options for help debugging.
42 static cl::opt<bool> DisableReMat("disable-rematerialization",
43 cl::init(false), cl::Hidden);
45 STATISTIC(numIntervals , "Number of original intervals");
47 char LiveIntervals::ID = 0;
48 INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals",
49 "Live Interval Analysis", false, false)
50 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
51 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
52 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
53 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
54 INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
55 "Live Interval Analysis", false, false)
57 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
59 AU.addRequired<AliasAnalysis>();
60 AU.addPreserved<AliasAnalysis>();
61 AU.addRequired<LiveVariables>();
62 AU.addPreserved<LiveVariables>();
63 AU.addPreservedID(MachineLoopInfoID);
64 AU.addPreservedID(MachineDominatorsID);
65 AU.addPreserved<SlotIndexes>();
66 AU.addRequiredTransitive<SlotIndexes>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 void LiveIntervals::releaseMemory() {
71 // Free the live intervals themselves.
72 for (DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(),
73 E = r2iMap_.end(); I != E; ++I)
79 RegMaskBlocks.clear();
81 // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
82 VNInfoAllocator.Reset();
85 /// runOnMachineFunction - Register allocate the whole function
87 bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
89 mri_ = &mf_->getRegInfo();
90 tm_ = &fn.getTarget();
91 tri_ = tm_->getRegisterInfo();
92 tii_ = tm_->getInstrInfo();
93 aa_ = &getAnalysis<AliasAnalysis>();
94 lv_ = &getAnalysis<LiveVariables>();
95 indexes_ = &getAnalysis<SlotIndexes>();
96 allocatableRegs_ = tri_->getAllocatableSet(fn);
97 reservedRegs_ = tri_->getReservedRegs(fn);
101 numIntervals += getNumIntervals();
107 /// print - Implement the dump method.
108 void LiveIntervals::print(raw_ostream &OS, const Module* ) const {
109 OS << "********** INTERVALS **********\n";
111 // Dump the physregs.
112 for (unsigned Reg = 1, RegE = tri_->getNumRegs(); Reg != RegE; ++Reg)
113 if (const LiveInterval *LI = r2iMap_.lookup(Reg)) {
118 // Dump the virtregs.
119 for (unsigned Reg = 0, RegE = mri_->getNumVirtRegs(); Reg != RegE; ++Reg)
120 if (const LiveInterval *LI =
121 r2iMap_.lookup(TargetRegisterInfo::index2VirtReg(Reg))) {
129 void LiveIntervals::printInstrs(raw_ostream &OS) const {
130 OS << "********** MACHINEINSTRS **********\n";
131 mf_->print(OS, indexes_);
134 void LiveIntervals::dumpInstrs() const {
139 bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
140 unsigned Reg = MI.getOperand(MOIdx).getReg();
141 for (unsigned i = MOIdx+1, e = MI.getNumOperands(); i < e; ++i) {
142 const MachineOperand &MO = MI.getOperand(i);
145 if (MO.getReg() == Reg && MO.isDef()) {
146 assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
147 MI.getOperand(MOIdx).getSubReg() &&
148 (MO.getSubReg() || MO.isImplicit()));
155 /// isPartialRedef - Return true if the specified def at the specific index is
156 /// partially re-defining the specified live interval. A common case of this is
157 /// a definition of the sub-register.
158 bool LiveIntervals::isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
159 LiveInterval &interval) {
160 if (!MO.getSubReg() || MO.isEarlyClobber())
163 SlotIndex RedefIndex = MIIdx.getRegSlot();
164 const LiveRange *OldLR =
165 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
166 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def);
168 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
173 void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
174 MachineBasicBlock::iterator mi,
178 LiveInterval &interval) {
179 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
181 // Virtual registers may be defined multiple times (due to phi
182 // elimination and 2-addr elimination). Much of what we do only has to be
183 // done once for the vreg. We use an empty interval to detect the first
184 // time we see a vreg.
185 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
186 if (interval.empty()) {
187 // Get the Idx of the defining instructions.
188 SlotIndex defIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
190 // Make sure the first definition is not a partial redefinition. Add an
191 // <imp-def> of the full register.
192 // FIXME: LiveIntervals shouldn't modify the code like this. Whoever
193 // created the machine instruction should annotate it with <undef> flags
194 // as needed. Then we can simply assert here. The REG_SEQUENCE lowering
195 // is the main suspect.
196 if (MO.getSubReg()) {
197 mi->addRegisterDefined(interval.reg);
198 // Mark all defs of interval.reg on this instruction as reading <undef>.
199 for (unsigned i = MOIdx, e = mi->getNumOperands(); i != e; ++i) {
200 MachineOperand &MO2 = mi->getOperand(i);
201 if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg())
206 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
207 assert(ValNo->id == 0 && "First value in interval is not 0?");
209 // Loop over all of the blocks that the vreg is defined in. There are
210 // two cases we have to handle here. The most common case is a vreg
211 // whose lifetime is contained within a basic block. In this case there
212 // will be a single kill, in MBB, which comes after the definition.
213 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) {
214 // FIXME: what about dead vars?
216 if (vi.Kills[0] != mi)
217 killIdx = getInstructionIndex(vi.Kills[0]).getRegSlot();
219 killIdx = defIndex.getDeadSlot();
221 // If the kill happens after the definition, we have an intra-block
223 if (killIdx > defIndex) {
224 assert(vi.AliveBlocks.empty() &&
225 "Shouldn't be alive across any blocks!");
226 LiveRange LR(defIndex, killIdx, ValNo);
227 interval.addRange(LR);
228 DEBUG(dbgs() << " +" << LR << "\n");
233 // The other case we handle is when a virtual register lives to the end
234 // of the defining block, potentially live across some blocks, then is
235 // live into some number of blocks, but gets killed. Start by adding a
236 // range that goes from this definition to the end of the defining block.
237 LiveRange NewLR(defIndex, getMBBEndIdx(mbb), ValNo);
238 DEBUG(dbgs() << " +" << NewLR);
239 interval.addRange(NewLR);
241 bool PHIJoin = lv_->isPHIJoin(interval.reg);
244 // A phi join register is killed at the end of the MBB and revived as a new
245 // valno in the killing blocks.
246 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
247 DEBUG(dbgs() << " phi-join");
248 ValNo->setHasPHIKill(true);
250 // Iterate over all of the blocks that the variable is completely
251 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
253 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
254 E = vi.AliveBlocks.end(); I != E; ++I) {
255 MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
256 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
257 interval.addRange(LR);
258 DEBUG(dbgs() << " +" << LR);
262 // Finally, this virtual register is live from the start of any killing
263 // block to the 'use' slot of the killing instruction.
264 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
265 MachineInstr *Kill = vi.Kills[i];
266 SlotIndex Start = getMBBStartIdx(Kill->getParent());
267 SlotIndex killIdx = getInstructionIndex(Kill).getRegSlot();
269 // Create interval with one of a NEW value number. Note that this value
270 // number isn't actually defined by an instruction, weird huh? :)
272 assert(getInstructionFromIndex(Start) == 0 &&
273 "PHI def index points at actual instruction.");
274 ValNo = interval.getNextValue(Start, VNInfoAllocator);
275 ValNo->setIsPHIDef(true);
277 LiveRange LR(Start, killIdx, ValNo);
278 interval.addRange(LR);
279 DEBUG(dbgs() << " +" << LR);
283 if (MultipleDefsBySameMI(*mi, MOIdx))
284 // Multiple defs of the same virtual register by the same instruction.
285 // e.g. %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
286 // This is likely due to elimination of REG_SEQUENCE instructions. Return
287 // here since there is nothing to do.
290 // If this is the second time we see a virtual register definition, it
291 // must be due to phi elimination or two addr elimination. If this is
292 // the result of two address elimination, then the vreg is one of the
293 // def-and-use register operand.
295 // It may also be partial redef like this:
296 // 80 %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
297 // 120 %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0
298 bool PartReDef = isPartialRedef(MIIdx, MO, interval);
299 if (PartReDef || mi->isRegTiedToUseOperand(MOIdx)) {
300 // If this is a two-address definition, then we have already processed
301 // the live range. The only problem is that we didn't realize there
302 // are actually two values in the live interval. Because of this we
303 // need to take the LiveRegion that defines this register and split it
305 SlotIndex RedefIndex = MIIdx.getRegSlot(MO.isEarlyClobber());
307 const LiveRange *OldLR =
308 interval.getLiveRangeContaining(RedefIndex.getRegSlot(true));
309 VNInfo *OldValNo = OldLR->valno;
310 SlotIndex DefIndex = OldValNo->def.getRegSlot();
312 // Delete the previous value, which should be short and continuous,
313 // because the 2-addr copy must be in the same MBB as the redef.
314 interval.removeRange(DefIndex, RedefIndex);
316 // The new value number (#1) is defined by the instruction we claimed
318 VNInfo *ValNo = interval.createValueCopy(OldValNo, VNInfoAllocator);
320 // Value#0 is now defined by the 2-addr instruction.
321 OldValNo->def = RedefIndex;
323 // Add the new live interval which replaces the range for the input copy.
324 LiveRange LR(DefIndex, RedefIndex, ValNo);
325 DEBUG(dbgs() << " replace range with " << LR);
326 interval.addRange(LR);
328 // If this redefinition is dead, we need to add a dummy unit live
329 // range covering the def slot.
331 interval.addRange(LiveRange(RedefIndex, RedefIndex.getDeadSlot(),
335 dbgs() << " RESULT: ";
336 interval.print(dbgs(), tri_);
338 } else if (lv_->isPHIJoin(interval.reg)) {
339 // In the case of PHI elimination, each variable definition is only
340 // live until the end of the block. We've already taken care of the
341 // rest of the live range.
343 SlotIndex defIndex = MIIdx.getRegSlot();
344 if (MO.isEarlyClobber())
345 defIndex = MIIdx.getRegSlot(true);
347 VNInfo *ValNo = interval.getNextValue(defIndex, VNInfoAllocator);
349 SlotIndex killIndex = getMBBEndIdx(mbb);
350 LiveRange LR(defIndex, killIndex, ValNo);
351 interval.addRange(LR);
352 ValNo->setHasPHIKill(true);
353 DEBUG(dbgs() << " phi-join +" << LR);
355 llvm_unreachable("Multiply defined register");
359 DEBUG(dbgs() << '\n');
362 static bool isRegLiveIntoSuccessor(const MachineBasicBlock *MBB, unsigned Reg) {
363 for (MachineBasicBlock::const_succ_iterator SI = MBB->succ_begin(),
364 SE = MBB->succ_end();
366 const MachineBasicBlock* succ = *SI;
367 if (succ->isLiveIn(Reg))
373 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
374 MachineBasicBlock::iterator mi,
377 LiveInterval &interval) {
378 DEBUG(dbgs() << "\t\tregister: " << PrintReg(interval.reg, tri_));
380 SlotIndex baseIndex = MIIdx;
381 SlotIndex start = baseIndex.getRegSlot(MO.isEarlyClobber());
382 SlotIndex end = start;
384 // If it is not used after definition, it is considered dead at
385 // the instruction defining it. Hence its interval is:
386 // [defSlot(def), defSlot(def)+1)
387 // For earlyclobbers, the defSlot was pushed back one; the extra
388 // advance below compensates.
390 DEBUG(dbgs() << " dead");
391 end = start.getDeadSlot();
395 // If it is not dead on definition, it must be killed by a
396 // subsequent instruction. Hence its interval is:
397 // [defSlot(def), useSlot(kill)+1)
398 baseIndex = baseIndex.getNextIndex();
399 while (++mi != MBB->end()) {
401 if (mi->isDebugValue())
403 if (getInstructionFromIndex(baseIndex) == 0)
404 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
406 if (mi->killsRegister(interval.reg, tri_)) {
407 DEBUG(dbgs() << " killed");
408 end = baseIndex.getRegSlot();
411 int DefIdx = mi->findRegisterDefOperandIdx(interval.reg,false,false,tri_);
413 if (mi->isRegTiedToUseOperand(DefIdx)) {
414 // Two-address instruction.
415 end = baseIndex.getRegSlot(mi->getOperand(DefIdx).isEarlyClobber());
417 // Another instruction redefines the register before it is ever read.
418 // Then the register is essentially dead at the instruction that
419 // defines it. Hence its interval is:
420 // [defSlot(def), defSlot(def)+1)
421 DEBUG(dbgs() << " dead");
422 end = start.getDeadSlot();
428 baseIndex = baseIndex.getNextIndex();
431 // If we get here the register *should* be live out.
432 assert(!isAllocatable(interval.reg) && "Physregs shouldn't be live out!");
434 // FIXME: We need saner rules for reserved regs.
435 if (isReserved(interval.reg)) {
436 end = start.getDeadSlot();
438 // Unreserved, unallocable registers like EFLAGS can be live across basic
440 assert(isRegLiveIntoSuccessor(MBB, interval.reg) &&
441 "Unreserved reg not live-out?");
442 end = getMBBEndIdx(MBB);
445 assert(start < end && "did not find end of interval?");
447 // Already exists? Extend old live interval.
448 VNInfo *ValNo = interval.getVNInfoAt(start);
449 bool Extend = ValNo != 0;
451 ValNo = interval.getNextValue(start, VNInfoAllocator);
452 LiveRange LR(start, end, ValNo);
453 interval.addRange(LR);
454 DEBUG(dbgs() << " +" << LR << '\n');
457 void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
458 MachineBasicBlock::iterator MI,
462 if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
463 handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
464 getOrCreateInterval(MO.getReg()));
466 handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
467 getOrCreateInterval(MO.getReg()));
470 void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB,
472 LiveInterval &interval) {
473 assert(TargetRegisterInfo::isPhysicalRegister(interval.reg) &&
474 "Only physical registers can be live in.");
475 assert((!isAllocatable(interval.reg) || MBB->getParent()->begin() ||
476 MBB->isLandingPad()) &&
477 "Allocatable live-ins only valid for entry blocks and landing pads.");
479 DEBUG(dbgs() << "\t\tlivein register: " << PrintReg(interval.reg, tri_));
481 // Look for kills, if it reaches a def before it's killed, then it shouldn't
482 // be considered a livein.
483 MachineBasicBlock::iterator mi = MBB->begin();
484 MachineBasicBlock::iterator E = MBB->end();
485 // Skip over DBG_VALUE at the start of the MBB.
486 if (mi != E && mi->isDebugValue()) {
487 while (++mi != E && mi->isDebugValue())
490 // MBB is empty except for DBG_VALUE's.
494 SlotIndex baseIndex = MIIdx;
495 SlotIndex start = baseIndex;
496 if (getInstructionFromIndex(baseIndex) == 0)
497 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
499 SlotIndex end = baseIndex;
500 bool SeenDefUse = false;
503 if (mi->killsRegister(interval.reg, tri_)) {
504 DEBUG(dbgs() << " killed");
505 end = baseIndex.getRegSlot();
508 } else if (mi->modifiesRegister(interval.reg, tri_)) {
509 // Another instruction redefines the register before it is ever read.
510 // Then the register is essentially dead at the instruction that defines
511 // it. Hence its interval is:
512 // [defSlot(def), defSlot(def)+1)
513 DEBUG(dbgs() << " dead");
514 end = start.getDeadSlot();
519 while (++mi != E && mi->isDebugValue())
520 // Skip over DBG_VALUE.
523 baseIndex = indexes_->getNextNonNullIndex(baseIndex);
526 // Live-in register might not be used at all.
528 if (isAllocatable(interval.reg) ||
529 !isRegLiveIntoSuccessor(MBB, interval.reg)) {
530 // Allocatable registers are never live through.
531 // Non-allocatable registers that aren't live into any successors also
532 // aren't live through.
533 DEBUG(dbgs() << " dead");
536 // If we get here the register is non-allocatable and live into some
537 // successor. We'll conservatively assume it's live-through.
538 DEBUG(dbgs() << " live through");
539 end = getMBBEndIdx(MBB);
543 SlotIndex defIdx = getMBBStartIdx(MBB);
544 assert(getInstructionFromIndex(defIdx) == 0 &&
545 "PHI def index points at actual instruction.");
546 VNInfo *vni = interval.getNextValue(defIdx, VNInfoAllocator);
547 vni->setIsPHIDef(true);
548 LiveRange LR(start, end, vni);
550 interval.addRange(LR);
551 DEBUG(dbgs() << " +" << LR << '\n');
554 /// computeIntervals - computes the live intervals for virtual
555 /// registers. for some ordering of the machine instructions [1,N] a
556 /// live interval is an interval [i, j) where 1 <= i <= j < N for
557 /// which a variable is live
558 void LiveIntervals::computeIntervals() {
559 DEBUG(dbgs() << "********** COMPUTING LIVE INTERVALS **********\n"
560 << "********** Function: "
561 << ((Value*)mf_->getFunction())->getName() << '\n');
563 RegMaskBlocks.resize(mf_->getNumBlockIDs());
565 SmallVector<unsigned, 8> UndefUses;
566 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
568 MachineBasicBlock *MBB = MBBI;
569 RegMaskBlocks[MBB->getNumber()].first = RegMaskSlots.size();
574 // Track the index of the current machine instr.
575 SlotIndex MIIndex = getMBBStartIdx(MBB);
576 DEBUG(dbgs() << "BB#" << MBB->getNumber()
577 << ":\t\t# derived from " << MBB->getName() << "\n");
579 // Create intervals for live-ins to this BB first.
580 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
581 LE = MBB->livein_end(); LI != LE; ++LI) {
582 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI));
585 // Skip over empty initial indices.
586 if (getInstructionFromIndex(MIIndex) == 0)
587 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
589 for (MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end();
591 DEBUG(dbgs() << MIIndex << "\t" << *MI);
592 if (MI->isDebugValue())
594 assert(indexes_->getInstructionFromIndex(MIIndex) == MI &&
595 "Lost SlotIndex synchronization");
598 for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
599 MachineOperand &MO = MI->getOperand(i);
601 // Collect register masks.
602 if (MO.isRegMask()) {
603 RegMaskSlots.push_back(MIIndex.getRegSlot());
604 RegMaskBits.push_back(MO.getRegMask());
608 if (!MO.isReg() || !MO.getReg())
611 // handle register defs - build intervals
613 handleRegisterDef(MBB, MI, MIIndex, MO, i);
614 else if (MO.isUndef())
615 UndefUses.push_back(MO.getReg());
618 // Move to the next instr slot.
619 MIIndex = indexes_->getNextNonNullIndex(MIIndex);
622 // Compute the number of register mask instructions in this block.
623 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB->getNumber()];
624 RMB.second = RegMaskSlots.size() - RMB.first;;
627 // Create empty intervals for registers defined by implicit_def's (except
628 // for those implicit_def that define values which are liveout of their
630 for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
631 unsigned UndefReg = UndefUses[i];
632 (void)getOrCreateInterval(UndefReg);
636 LiveInterval* LiveIntervals::createInterval(unsigned reg) {
637 float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F;
638 return new LiveInterval(reg, Weight);
641 /// dupInterval - Duplicate a live interval. The caller is responsible for
642 /// managing the allocated memory.
643 LiveInterval* LiveIntervals::dupInterval(LiveInterval *li) {
644 LiveInterval *NewLI = createInterval(li->reg);
645 NewLI->Copy(*li, mri_, getVNInfoAllocator());
649 /// shrinkToUses - After removing some uses of a register, shrink its live
650 /// range to just the remaining uses. This method does not compute reaching
651 /// defs for new uses, and it doesn't remove dead defs.
652 bool LiveIntervals::shrinkToUses(LiveInterval *li,
653 SmallVectorImpl<MachineInstr*> *dead) {
654 DEBUG(dbgs() << "Shrink: " << *li << '\n');
655 assert(TargetRegisterInfo::isVirtualRegister(li->reg)
656 && "Can only shrink virtual registers");
657 // Find all the values used, including PHI kills.
658 SmallVector<std::pair<SlotIndex, VNInfo*>, 16> WorkList;
660 // Blocks that have already been added to WorkList as live-out.
661 SmallPtrSet<MachineBasicBlock*, 16> LiveOut;
663 // Visit all instructions reading li->reg.
664 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(li->reg);
665 MachineInstr *UseMI = I.skipInstruction();) {
666 if (UseMI->isDebugValue() || !UseMI->readsVirtualRegister(li->reg))
668 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
669 // Note: This intentionally picks up the wrong VNI in case of an EC redef.
671 VNInfo *VNI = li->getVNInfoBefore(Idx);
673 // This shouldn't happen: readsVirtualRegister returns true, but there is
674 // no live value. It is likely caused by a target getting <undef> flags
676 DEBUG(dbgs() << Idx << '\t' << *UseMI
677 << "Warning: Instr claims to read non-existent value in "
681 // Special case: An early-clobber tied operand reads and writes the
682 // register one slot early. The getVNInfoBefore call above would have
683 // picked up the value defined by UseMI. Adjust the kill slot and value.
684 if (SlotIndex::isSameInstr(VNI->def, Idx)) {
686 VNI = li->getVNInfoBefore(Idx);
687 assert(VNI && "Early-clobber tied value not available");
689 WorkList.push_back(std::make_pair(Idx, VNI));
692 // Create a new live interval with only minimal live segments per def.
693 LiveInterval NewLI(li->reg, 0);
694 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
699 NewLI.addRange(LiveRange(VNI->def, VNI->def.getDeadSlot(), VNI));
702 // Keep track of the PHIs that are in use.
703 SmallPtrSet<VNInfo*, 8> UsedPHIs;
705 // Extend intervals to reach all uses in WorkList.
706 while (!WorkList.empty()) {
707 SlotIndex Idx = WorkList.back().first;
708 VNInfo *VNI = WorkList.back().second;
710 const MachineBasicBlock *MBB = getMBBFromIndex(Idx.getPrevSlot());
711 SlotIndex BlockStart = getMBBStartIdx(MBB);
713 // Extend the live range for VNI to be live at Idx.
714 if (VNInfo *ExtVNI = NewLI.extendInBlock(BlockStart, Idx)) {
716 assert(ExtVNI == VNI && "Unexpected existing value number");
717 // Is this a PHIDef we haven't seen before?
718 if (!VNI->isPHIDef() || VNI->def != BlockStart || !UsedPHIs.insert(VNI))
720 // The PHI is live, make sure the predecessors are live-out.
721 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
722 PE = MBB->pred_end(); PI != PE; ++PI) {
723 if (!LiveOut.insert(*PI))
725 SlotIndex Stop = getMBBEndIdx(*PI);
726 // A predecessor is not required to have a live-out value for a PHI.
727 if (VNInfo *PVNI = li->getVNInfoBefore(Stop))
728 WorkList.push_back(std::make_pair(Stop, PVNI));
733 // VNI is live-in to MBB.
734 DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
735 NewLI.addRange(LiveRange(BlockStart, Idx, VNI));
737 // Make sure VNI is live-out from the predecessors.
738 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
739 PE = MBB->pred_end(); PI != PE; ++PI) {
740 if (!LiveOut.insert(*PI))
742 SlotIndex Stop = getMBBEndIdx(*PI);
743 assert(li->getVNInfoBefore(Stop) == VNI &&
744 "Wrong value out of predecessor");
745 WorkList.push_back(std::make_pair(Stop, VNI));
749 // Handle dead values.
750 bool CanSeparate = false;
751 for (LiveInterval::vni_iterator I = li->vni_begin(), E = li->vni_end();
756 LiveInterval::iterator LII = NewLI.FindLiveRangeContaining(VNI->def);
757 assert(LII != NewLI.end() && "Missing live range for PHI");
758 if (LII->end != VNI->def.getDeadSlot())
760 if (VNI->isPHIDef()) {
761 // This is a dead PHI. Remove it.
762 VNI->setIsUnused(true);
763 NewLI.removeRange(*LII);
764 DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
767 // This is a dead def. Make sure the instruction knows.
768 MachineInstr *MI = getInstructionFromIndex(VNI->def);
769 assert(MI && "No instruction defining live value");
770 MI->addRegisterDead(li->reg, tri_);
771 if (dead && MI->allDefsAreDead()) {
772 DEBUG(dbgs() << "All defs dead: " << VNI->def << '\t' << *MI);
778 // Move the trimmed ranges back.
779 li->ranges.swap(NewLI.ranges);
780 DEBUG(dbgs() << "Shrunk: " << *li << '\n');
785 //===----------------------------------------------------------------------===//
786 // Register allocator hooks.
789 void LiveIntervals::addKillFlags() {
790 for (iterator I = begin(), E = end(); I != E; ++I) {
791 unsigned Reg = I->first;
792 if (TargetRegisterInfo::isPhysicalRegister(Reg))
794 if (mri_->reg_nodbg_empty(Reg))
796 LiveInterval *LI = I->second;
798 // Every instruction that kills Reg corresponds to a live range end point.
799 for (LiveInterval::iterator RI = LI->begin(), RE = LI->end(); RI != RE;
801 // A block index indicates an MBB edge.
802 if (RI->end.isBlock())
804 MachineInstr *MI = getInstructionFromIndex(RI->end);
807 MI->addRegisterKilled(Reg, NULL);
812 /// getReMatImplicitUse - If the remat definition MI has one (for now, we only
813 /// allow one) virtual register operand, then its uses are implicitly using
814 /// the register. Returns the virtual register.
815 unsigned LiveIntervals::getReMatImplicitUse(const LiveInterval &li,
816 MachineInstr *MI) const {
818 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
819 MachineOperand &MO = MI->getOperand(i);
820 if (!MO.isReg() || !MO.isUse())
822 unsigned Reg = MO.getReg();
823 if (Reg == 0 || Reg == li.reg)
826 if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isAllocatable(Reg))
829 break; // Found vreg operand - leave the loop.
834 /// isValNoAvailableAt - Return true if the val# of the specified interval
835 /// which reaches the given instruction also reaches the specified use index.
836 bool LiveIntervals::isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
837 SlotIndex UseIdx) const {
838 VNInfo *UValNo = li.getVNInfoAt(UseIdx);
839 return UValNo && UValNo == li.getVNInfoAt(getInstructionIndex(MI));
842 /// isReMaterializable - Returns true if the definition MI of the specified
843 /// val# of the specified interval is re-materializable.
845 LiveIntervals::isReMaterializable(const LiveInterval &li,
846 const VNInfo *ValNo, MachineInstr *MI,
847 const SmallVectorImpl<LiveInterval*> *SpillIs,
852 if (!tii_->isTriviallyReMaterializable(MI, aa_))
855 // Target-specific code can mark an instruction as being rematerializable
856 // if it has one virtual reg use, though it had better be something like
857 // a PIC base register which is likely to be live everywhere.
858 unsigned ImpUse = getReMatImplicitUse(li, MI);
860 const LiveInterval &ImpLi = getInterval(ImpUse);
861 for (MachineRegisterInfo::use_nodbg_iterator
862 ri = mri_->use_nodbg_begin(li.reg), re = mri_->use_nodbg_end();
864 MachineInstr *UseMI = &*ri;
865 SlotIndex UseIdx = getInstructionIndex(UseMI);
866 if (li.getVNInfoAt(UseIdx) != ValNo)
868 if (!isValNoAvailableAt(ImpLi, MI, UseIdx))
872 // If a register operand of the re-materialized instruction is going to
873 // be spilled next, then it's not legal to re-materialize this instruction.
875 for (unsigned i = 0, e = SpillIs->size(); i != e; ++i)
876 if (ImpUse == (*SpillIs)[i]->reg)
882 /// isReMaterializable - Returns true if every definition of MI of every
883 /// val# of the specified interval is re-materializable.
885 LiveIntervals::isReMaterializable(const LiveInterval &li,
886 const SmallVectorImpl<LiveInterval*> *SpillIs,
889 for (LiveInterval::const_vni_iterator i = li.vni_begin(), e = li.vni_end();
891 const VNInfo *VNI = *i;
893 continue; // Dead val#.
894 // Is the def for the val# rematerializable?
895 MachineInstr *ReMatDefMI = getInstructionFromIndex(VNI->def);
898 bool DefIsLoad = false;
900 !isReMaterializable(li, VNI, ReMatDefMI, SpillIs, DefIsLoad))
908 LiveIntervals::intervalIsInOneMBB(const LiveInterval &LI) const {
909 // A local live range must be fully contained inside the block, meaning it is
910 // defined and killed at instructions, not at block boundaries. It is not
911 // live in or or out of any block.
913 // It is technically possible to have a PHI-defined live range identical to a
914 // single block, but we are going to return false in that case.
916 SlotIndex Start = LI.beginIndex();
920 SlotIndex Stop = LI.endIndex();
924 // getMBBFromIndex doesn't need to search the MBB table when both indexes
925 // belong to proper instructions.
926 MachineBasicBlock *MBB1 = indexes_->getMBBFromIndex(Start);
927 MachineBasicBlock *MBB2 = indexes_->getMBBFromIndex(Stop);
928 return MBB1 == MBB2 ? MBB1 : NULL;
932 LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
933 // Limit the loop depth ridiculousness.
937 // The loop depth is used to roughly estimate the number of times the
938 // instruction is executed. Something like 10^d is simple, but will quickly
939 // overflow a float. This expression behaves like 10^d for small d, but is
940 // more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
941 // headroom before overflow.
942 // By the way, powf() might be unavailable here. For consistency,
943 // We may take pow(double,double).
944 float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
946 return (isDef + isUse) * lc;
949 LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,
950 MachineInstr* startInst) {
951 LiveInterval& Interval = getOrCreateInterval(reg);
952 VNInfo* VN = Interval.getNextValue(
953 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
954 getVNInfoAllocator());
955 VN->setHasPHIKill(true);
957 SlotIndex(getInstructionIndex(startInst).getRegSlot()),
958 getMBBEndIdx(startInst->getParent()), VN);
959 Interval.addRange(LR);
965 //===----------------------------------------------------------------------===//
966 // Register mask functions
967 //===----------------------------------------------------------------------===//
969 bool LiveIntervals::checkRegMaskInterference(LiveInterval &LI,
970 BitVector &UsableRegs) {
973 LiveInterval::iterator LiveI = LI.begin(), LiveE = LI.end();
975 // Use a smaller arrays for local live ranges.
976 ArrayRef<SlotIndex> Slots;
977 ArrayRef<const uint32_t*> Bits;
978 if (MachineBasicBlock *MBB = intervalIsInOneMBB(LI)) {
979 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
980 Bits = getRegMaskBitsInBlock(MBB->getNumber());
982 Slots = getRegMaskSlots();
983 Bits = getRegMaskBits();
986 // We are going to enumerate all the register mask slots contained in LI.
987 // Start with a binary search of RegMaskSlots to find a starting point.
988 ArrayRef<SlotIndex>::iterator SlotI =
989 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
990 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
992 // No slots in range, LI begins after the last call.
998 assert(*SlotI >= LiveI->start);
999 // Loop over all slots overlapping this segment.
1000 while (*SlotI < LiveI->end) {
1001 // *SlotI overlaps LI. Collect mask bits.
1003 // This is the first overlap. Initialize UsableRegs to all ones.
1005 UsableRegs.resize(tri_->getNumRegs(), true);
1008 // Remove usable registers clobbered by this mask.
1009 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()]);
1010 if (++SlotI == SlotE)
1013 // *SlotI is beyond the current LI segment.
1014 LiveI = LI.advanceTo(LiveI, *SlotI);
1017 // Advance SlotI until it overlaps.
1018 while (*SlotI < LiveI->start)
1019 if (++SlotI == SlotE)
1024 //===----------------------------------------------------------------------===//
1025 // IntervalUpdate class.
1026 //===----------------------------------------------------------------------===//
1028 // HMEditor is a toolkit used by handleMove to trim or extend live intervals.
1029 class LiveIntervals::HMEditor {
1032 const MachineRegisterInfo& MRI;
1033 const TargetRegisterInfo& TRI;
1036 typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
1037 typedef DenseSet<IntRangePair> RangeSet;
1044 RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
1046 typedef DenseMap<unsigned, RegRanges> BundleRanges;
1049 HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
1050 const TargetRegisterInfo& TRI, SlotIndex NewIdx)
1051 : LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
1053 // Update intervals for all operands of MI from OldIdx to NewIdx.
1054 // This assumes that MI used to be at OldIdx, and now resides at
1056 void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
1057 assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
1059 // Collect the operands.
1060 RangeSet Entering, Internal, Exiting;
1061 bool hasRegMaskOp = false;
1062 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1064 moveAllEnteringFrom(OldIdx, Entering);
1065 moveAllInternalFrom(OldIdx, Internal);
1066 moveAllExitingFrom(OldIdx, Exiting);
1069 updateRegMaskSlots(OldIdx);
1072 LIValidator validator;
1073 std::for_each(Entering.begin(), Entering.end(), validator);
1074 std::for_each(Internal.begin(), Internal.end(), validator);
1075 std::for_each(Exiting.begin(), Exiting.end(), validator);
1076 assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
1081 // Update intervals for all operands of MI to refer to BundleStart's
1083 void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
1084 if (MI == BundleStart)
1085 return; // Bundling instr with itself - nothing to do.
1087 SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
1088 assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
1089 "SlotIndex <-> Instruction mapping broken for MI");
1091 // Collect all ranges already in the bundle.
1092 MachineBasicBlock::instr_iterator BII(BundleStart);
1093 RangeSet Entering, Internal, Exiting;
1094 bool hasRegMaskOp = false;
1095 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1096 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1097 for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
1100 collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
1101 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1104 BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
1106 collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
1107 assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
1109 DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
1110 DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
1111 DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
1113 moveAllEnteringFromInto(OldIdx, Entering, BR);
1114 moveAllInternalFromInto(OldIdx, Internal, BR);
1115 moveAllExitingFromInto(OldIdx, Exiting, BR);
1119 LIValidator validator;
1120 std::for_each(Entering.begin(), Entering.end(), validator);
1121 std::for_each(Internal.begin(), Internal.end(), validator);
1122 std::for_each(Exiting.begin(), Exiting.end(), validator);
1123 assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
1132 DenseSet<const LiveInterval*> Checked, Bogus;
1134 void operator()(const IntRangePair& P) {
1135 const LiveInterval* LI = P.first;
1136 if (Checked.count(LI))
1141 SlotIndex LastEnd = LI->begin()->start;
1142 for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
1143 LRI != LRE; ++LRI) {
1144 const LiveRange& LR = *LRI;
1145 if (LastEnd > LR.start || LR.start >= LR.end)
1151 bool rangesOk() const {
1152 return Bogus.empty();
1157 // Collect IntRangePairs for all operands of MI that may need fixing.
1158 // Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
1160 void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
1161 RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
1162 hasRegMaskOp = false;
1163 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1164 MOE = MI->operands_end();
1165 MOI != MOE; ++MOI) {
1166 const MachineOperand& MO = *MOI;
1168 if (MO.isRegMask()) {
1169 hasRegMaskOp = true;
1173 if (!MO.isReg() || MO.getReg() == 0)
1176 unsigned Reg = MO.getReg();
1178 // TODO: Currently we're skipping uses that are reserved or have no
1179 // interval, but we're not updating their kills. This should be
1181 if (!LIS.hasInterval(Reg) ||
1182 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1185 LiveInterval* LI = &LIS.getInterval(Reg);
1187 if (MO.readsReg()) {
1188 LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
1190 Entering.insert(std::make_pair(LI, LR));
1193 if (MO.isEarlyClobber()) {
1194 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot(true));
1195 assert(LR != 0 && "No EC range?");
1196 if (LR->end > OldIdx.getDeadSlot())
1197 Exiting.insert(std::make_pair(LI, LR));
1199 Internal.insert(std::make_pair(LI, LR));
1200 } else if (MO.isDead()) {
1201 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
1202 assert(LR != 0 && "No dead-def range?");
1203 Internal.insert(std::make_pair(LI, LR));
1205 LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getDeadSlot());
1206 assert(LR && LR->end > OldIdx.getDeadSlot() &&
1207 "Non-dead-def should have live range exiting.");
1208 Exiting.insert(std::make_pair(LI, LR));
1214 // Collect IntRangePairs for all operands of MI that may need fixing.
1215 void collectRangesInBundle(MachineInstr* MI, RangeSet& Entering,
1216 RangeSet& Exiting, SlotIndex MIStartIdx,
1217 SlotIndex MIEndIdx) {
1218 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
1219 MOE = MI->operands_end();
1220 MOI != MOE; ++MOI) {
1221 const MachineOperand& MO = *MOI;
1222 assert(!MO.isRegMask() && "Can't have RegMasks in bundles.");
1223 if (!MO.isReg() || MO.getReg() == 0)
1226 unsigned Reg = MO.getReg();
1228 // TODO: Currently we're skipping uses that are reserved or have no
1229 // interval, but we're not updating their kills. This should be
1231 if (!LIS.hasInterval(Reg) ||
1232 (TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg)))
1235 LiveInterval* LI = &LIS.getInterval(Reg);
1237 if (MO.readsReg()) {
1238 LiveRange* LR = LI->getLiveRangeContaining(MIStartIdx);
1240 Entering.insert(std::make_pair(LI, LR));
1243 assert(!MO.isEarlyClobber() && "Early clobbers not allowed in bundles.");
1244 assert(!MO.isDead() && "Dead-defs not allowed in bundles.");
1245 LiveRange* LR = LI->getLiveRangeContaining(MIEndIdx.getDeadSlot());
1246 assert(LR != 0 && "Internal ranges not allowed in bundles.");
1247 Exiting.insert(std::make_pair(LI, LR));
1252 BundleRanges createBundleRanges(RangeSet& Entering, RangeSet& Internal, RangeSet& Exiting) {
1255 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1257 LiveInterval* LI = EI->first;
1258 LiveRange* LR = EI->second;
1259 BR[LI->reg].Use = LR;
1262 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1264 LiveInterval* LI = II->first;
1265 LiveRange* LR = II->second;
1266 if (LR->end.isDead()) {
1267 BR[LI->reg].Dead = LR;
1269 BR[LI->reg].EC = LR;
1273 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1275 LiveInterval* LI = EI->first;
1276 LiveRange* LR = EI->second;
1277 BR[LI->reg].Def = LR;
1283 void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
1284 MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
1285 if (!OldKillMI->killsRegister(reg))
1286 return; // Bail out if we don't have kill flags on the old register.
1287 MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
1288 assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
1289 assert(!NewKillMI->killsRegister(reg) && "New kill instr is already a kill.");
1290 OldKillMI->clearRegisterKills(reg, &TRI);
1291 NewKillMI->addRegisterKilled(reg, &TRI);
1294 void updateRegMaskSlots(SlotIndex OldIdx) {
1295 SmallVectorImpl<SlotIndex>::iterator RI =
1296 std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
1298 assert(*RI == OldIdx && "No RegMask at OldIdx.");
1300 assert(*prior(RI) < *RI && *RI < *next(RI) &&
1301 "RegSlots out of order. Did you move one call across another?");
1304 // Return the last use of reg between NewIdx and OldIdx.
1305 SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
1306 SlotIndex LastUse = NewIdx;
1307 for (MachineRegisterInfo::use_nodbg_iterator
1308 UI = MRI.use_nodbg_begin(Reg),
1309 UE = MRI.use_nodbg_end();
1310 UI != UE; UI.skipInstruction()) {
1311 const MachineInstr* MI = &*UI;
1312 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1313 if (InstSlot > LastUse && InstSlot < OldIdx)
1319 void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
1320 LiveInterval* LI = P.first;
1321 LiveRange* LR = P.second;
1322 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1325 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1326 if (LastUse != NewIdx)
1327 moveKillFlags(LI->reg, NewIdx, LastUse);
1328 LR->end = LastUse.getRegSlot();
1331 void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
1332 LiveInterval* LI = P.first;
1333 LiveRange* LR = P.second;
1334 if (NewIdx > LR->end) {
1335 moveKillFlags(LI->reg, LR->end, NewIdx);
1336 LR->end = NewIdx.getRegSlot();
1340 void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
1341 bool GoingUp = NewIdx < OldIdx;
1344 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1346 moveEnteringUpFrom(OldIdx, *EI);
1348 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1350 moveEnteringDownFrom(OldIdx, *EI);
1354 void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
1355 LiveInterval* LI = P.first;
1356 LiveRange* LR = P.second;
1357 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1358 LR->end <= OldIdx.getDeadSlot() &&
1359 "Range should be internal to OldIdx.");
1361 Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1362 Tmp.valno->def = Tmp.start;
1363 Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
1364 LI->removeRange(*LR);
1368 void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
1369 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1371 moveInternalFrom(OldIdx, *II);
1374 void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
1375 LiveRange* LR = P.second;
1376 assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
1377 "Range should start in OldIdx.");
1378 assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
1379 SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
1380 LR->start = NewStart;
1381 LR->valno->def = NewStart;
1384 void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
1385 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1387 moveExitingFrom(OldIdx, *EI);
1390 void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
1392 LiveInterval* LI = P.first;
1393 LiveRange* LR = P.second;
1394 bool LiveThrough = LR->end > OldIdx.getRegSlot();
1396 assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
1397 "Def in bundle should be def range.");
1398 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1399 "If bundle has use for this reg it should be LR.");
1400 BR[LI->reg].Use = LR;
1404 SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
1405 moveKillFlags(LI->reg, OldIdx, LastUse);
1407 if (LR->start < NewIdx) {
1408 // Becoming a new entering range.
1409 assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
1410 "Bundle shouldn't be re-defining reg mid-range.");
1411 assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
1412 "Bundle shouldn't have different use range for same reg.");
1413 LR->end = LastUse.getRegSlot();
1414 BR[LI->reg].Use = LR;
1416 // Becoming a new Dead-def.
1417 assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
1418 "Live range starting at unexpected slot.");
1419 assert(BR[LI->reg].Def == LR && "Reg should have def range.");
1420 assert(BR[LI->reg].Dead == 0 &&
1421 "Can't have def and dead def of same reg in a bundle.");
1422 LR->end = LastUse.getDeadSlot();
1423 BR[LI->reg].Dead = BR[LI->reg].Def;
1424 BR[LI->reg].Def = 0;
1428 void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
1430 LiveInterval* LI = P.first;
1431 LiveRange* LR = P.second;
1432 if (NewIdx > LR->end) {
1433 // Range extended to bundle. Add to bundle uses.
1434 // Note: Currently adds kill flags to bundle start.
1435 assert(BR[LI->reg].Use == 0 &&
1436 "Bundle already has use range for reg.");
1437 moveKillFlags(LI->reg, LR->end, NewIdx);
1438 LR->end = NewIdx.getRegSlot();
1439 BR[LI->reg].Use = LR;
1441 assert(BR[LI->reg].Use != 0 &&
1442 "Bundle should already have a use range for reg.");
1446 void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
1448 bool GoingUp = NewIdx < OldIdx;
1451 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1453 moveEnteringUpFromInto(OldIdx, *EI, BR);
1455 for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
1457 moveEnteringDownFromInto(OldIdx, *EI, BR);
1461 void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
1463 // TODO: Sane rules for moving ranges into bundles.
1466 void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
1468 for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
1470 moveInternalFromInto(OldIdx, *II, BR);
1473 void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
1475 LiveInterval* LI = P.first;
1476 LiveRange* LR = P.second;
1478 assert(LR->start.isRegister() &&
1479 "Don't know how to merge exiting ECs into bundles yet.");
1481 if (LR->end > NewIdx.getDeadSlot()) {
1482 // This range is becoming an exiting range on the bundle.
1483 // If there was an old dead-def of this reg, delete it.
1484 if (BR[LI->reg].Dead != 0) {
1485 LI->removeRange(*BR[LI->reg].Dead);
1486 BR[LI->reg].Dead = 0;
1488 assert(BR[LI->reg].Def == 0 &&
1489 "Can't have two defs for the same variable exiting a bundle.");
1490 LR->start = NewIdx.getRegSlot();
1491 LR->valno->def = LR->start;
1492 BR[LI->reg].Def = LR;
1494 // This range is becoming internal to the bundle.
1495 assert(LR->end == NewIdx.getRegSlot() &&
1496 "Can't bundle def whose kill is before the bundle");
1497 if (BR[LI->reg].Dead || BR[LI->reg].Def) {
1498 // Already have a def for this. Just delete range.
1499 LI->removeRange(*LR);
1501 // Make range dead, record.
1502 LR->end = NewIdx.getDeadSlot();
1503 BR[LI->reg].Dead = LR;
1504 assert(BR[LI->reg].Use == LR &&
1505 "Range becoming dead should currently be use.");
1507 // In both cases the range is no longer a use on the bundle.
1508 BR[LI->reg].Use = 0;
1512 void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
1514 for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
1516 moveExitingFromInto(OldIdx, *EI, BR);
1521 void LiveIntervals::handleMove(MachineInstr* MI) {
1522 SlotIndex OldIndex = indexes_->getInstructionIndex(MI);
1523 indexes_->removeMachineInstrFromMaps(MI);
1524 SlotIndex NewIndex = MI->isInsideBundle() ?
1525 indexes_->getInstructionIndex(MI->getBundleStart()) :
1526 indexes_->insertMachineInstrInMaps(MI);
1527 assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
1528 OldIndex < getMBBEndIdx(MI->getParent()) &&
1529 "Cannot handle moves across basic block boundaries.");
1530 assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
1532 HMEditor HME(*this, *mri_, *tri_, NewIndex);
1533 HME.moveAllRangesFrom(MI, OldIndex);
1536 void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart) {
1537 SlotIndex NewIndex = indexes_->getInstructionIndex(BundleStart);
1538 HMEditor HME(*this, *mri_, *tri_, NewIndex);
1539 HME.moveAllRangesInto(MI, BundleStart);