1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/GCStrategy.h"
21 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCContext.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetRegistry.h"
28 #include "llvm/Transforms/Scalar.h"
29 #include "llvm/ADT/OwningPtr.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/FormattedStream.h"
39 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
40 cl::desc("Disable Post Regalloc"));
41 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
42 cl::desc("Disable branch folding"));
43 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
44 cl::desc("Disable tail duplication"));
45 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
46 cl::desc("Disable pre-register allocation tail duplication"));
47 static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
48 cl::desc("Disable code placement"));
49 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
50 cl::desc("Disable Stack Slot Coloring"));
51 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52 cl::desc("Disable Machine LICM"));
53 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
54 cl::desc("Disable Machine Sinking"));
55 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
56 cl::desc("Disable Loop Strength Reduction Pass"));
57 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
58 cl::desc("Disable Codegen Prepare"));
59 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
60 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
61 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
62 cl::desc("Print LLVM IR input to isel pass"));
63 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
64 cl::desc("Dump garbage collector data"));
65 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
66 cl::desc("Verify generated machine code"),
67 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
69 static cl::opt<cl::boolOrDefault>
70 AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
71 cl::init(cl::BOU_UNSET));
73 static bool getVerboseAsm() {
76 case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
77 case cl::BOU_TRUE: return true;
78 case cl::BOU_FALSE: return false;
82 // Enable or disable FastISel. Both options are needed, because
83 // FastISel is enabled by default with -fast, and we wish to be
84 // able to enable or disable fast-isel independently from -O0.
85 static cl::opt<cl::boolOrDefault>
86 EnableFastISelOption("fast-isel", cl::Hidden,
87 cl::desc("Enable the \"fast\" instruction selector"));
89 // Enable or disable an experimental optimization to split GEPs
90 // and run a special GVN pass which does not examine loads, in
91 // an effort to factor out redundancy implicit in complex GEPs.
92 static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
93 cl::desc("Split GEPs and run no-load GVN"));
95 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
96 const std::string &TargetTriple)
98 AsmInfo = T.createAsmInfo(TargetTriple);
101 // Set the default code model for the JIT for a generic target.
102 // FIXME: Is small right here? or .is64Bit() ? Large : Small?
104 LLVMTargetMachine::setCodeModelForJIT() {
105 setCodeModel(CodeModel::Small);
108 // Set the default code model for static compilation for a generic target.
110 LLVMTargetMachine::setCodeModelForStatic() {
111 setCodeModel(CodeModel::Small);
114 TargetMachine::CodeGenFileType
115 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
116 formatted_raw_ostream &Out,
117 CodeGenFileType FileType,
118 CodeGenOpt::Level OptLevel) {
119 // Add common CodeGen passes.
120 if (addCommonCodeGenPasses(PM, OptLevel))
121 return CGFT_ErrorOccurred;
123 OwningPtr<MCContext> Context(new MCContext());
124 OwningPtr<MCStreamer> AsmStreamer;
126 formatted_raw_ostream *LegacyOutput;
128 default: return CGFT_ErrorOccurred;
129 case CGFT_AssemblyFile:
130 AsmStreamer.reset(createAsmStreamer(*Context, Out, *getMCAsmInfo(),
131 getTargetData()->isLittleEndian(),
132 getVerboseAsm(), /*instprinter*/0,
134 // Set the AsmPrinter's "O" to the output file.
137 case CGFT_ObjectFile: {
138 // Create the code emitter for the target if it exists. If not, .o file
140 MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this);
142 return CGFT_ErrorOccurred;
144 AsmStreamer.reset(createMachOStreamer(*Context, Out, MCE));
146 // Any output to the asmprinter's "O" stream is bad and needs to be fixed,
147 // force it to come out stderr.
148 // FIXME: this is horrible and leaks, eventually remove the raw_ostream from
150 LegacyOutput = new formatted_raw_ostream(errs());
155 // Create the AsmPrinter, which takes ownership of Context and AsmStreamer
157 FunctionPass *Printer =
158 getTarget().createAsmPrinter(*LegacyOutput, *this, *Context, *AsmStreamer,
161 return CGFT_ErrorOccurred;
163 // If successful, createAsmPrinter took ownership of AsmStreamer and Context.
164 Context.take(); AsmStreamer.take();
168 // Make sure the code model is set.
169 setCodeModelForStatic();
170 PM.add(createGCInfoDeleter());
174 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
175 /// get machine code emitted. This uses a JITCodeEmitter object to handle
176 /// actually outputting the machine code and resolving things like the address
177 /// of functions. This method should returns true if machine code emission is
180 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
182 CodeGenOpt::Level OptLevel) {
183 // Make sure the code model is set.
184 setCodeModelForJIT();
186 // Add common CodeGen passes.
187 if (addCommonCodeGenPasses(PM, OptLevel))
190 addCodeEmitter(PM, OptLevel, JCE);
191 PM.add(createGCInfoDeleter());
193 return false; // success!
196 static void printAndVerify(PassManagerBase &PM,
198 bool allowDoubleDefs = false) {
199 if (PrintMachineCode)
200 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
202 if (VerifyMachineCode)
203 PM.add(createMachineVerifierPass(allowDoubleDefs));
206 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
207 /// emitting to assembly files or machine code output.
209 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
210 CodeGenOpt::Level OptLevel) {
211 // Standard LLVM-Level Passes.
213 // Optionally, tun split-GEPs and no-load GVN.
214 if (EnableSplitGEPGVN) {
215 PM.add(createGEPSplitterPass());
216 PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true));
219 // Run loop strength reduction before anything else.
220 if (OptLevel != CodeGenOpt::None && !DisableLSR) {
221 PM.add(createLoopStrengthReducePass(getTargetLowering()));
223 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
226 // Turn exception handling constructs into something the code generators can
228 switch (getMCAsmInfo()->getExceptionHandlingType())
230 case ExceptionHandling::SjLj:
231 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
232 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
233 // catch info can get misplaced when a selector ends up more than one block
234 // removed from the parent invoke(s). This could happen when a landing
235 // pad is shared by multiple invokes and is also a target of a normal
236 // edge from elsewhere.
237 PM.add(createSjLjEHPass(getTargetLowering()));
238 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
240 case ExceptionHandling::Dwarf:
241 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
243 case ExceptionHandling::None:
244 PM.add(createLowerInvokePass(getTargetLowering()));
248 PM.add(createGCLoweringPass());
250 // Make sure that no unreachable blocks are instruction selected.
251 PM.add(createUnreachableBlockEliminationPass());
253 if (OptLevel != CodeGenOpt::None && !DisableCGP)
254 PM.add(createCodeGenPreparePass(getTargetLowering()));
256 PM.add(createStackProtectorPass(getTargetLowering()));
259 PM.add(createPrintFunctionPass("\n\n"
260 "*** Final LLVM Code input to ISel ***\n",
263 // Standard Lower-Level Passes.
265 // Set up a MachineFunction for the rest of CodeGen to work on.
266 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
268 // Enable FastISel with -fast, but allow that to be overridden.
269 if (EnableFastISelOption == cl::BOU_TRUE ||
270 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
271 EnableFastISel = true;
273 // Ask the target for an isel.
274 if (addInstSelector(PM, OptLevel))
277 // Print the instruction selected machine code...
278 printAndVerify(PM, "After Instruction Selection",
279 /* allowDoubleDefs= */ true);
281 if (OptLevel != CodeGenOpt::None) {
282 PM.add(createOptimizeExtsPass());
283 if (!DisableMachineLICM)
284 PM.add(createMachineLICMPass());
285 if (!DisableMachineSink)
286 PM.add(createMachineSinkingPass());
287 printAndVerify(PM, "After MachineLICM and MachineSinking",
288 /* allowDoubleDefs= */ true);
291 // Pre-ra tail duplication.
292 if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
293 PM.add(createTailDuplicatePass(true));
294 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
295 /* allowDoubleDefs= */ true);
298 // Run pre-ra passes.
299 if (addPreRegAlloc(PM, OptLevel))
300 printAndVerify(PM, "After PreRegAlloc passes",
301 /* allowDoubleDefs= */ true);
303 // Perform register allocation.
304 PM.add(createRegisterAllocator());
305 printAndVerify(PM, "After Register Allocation");
307 // Perform stack slot coloring.
308 if (OptLevel != CodeGenOpt::None && !DisableSSC) {
309 // FIXME: Re-enable coloring with register when it's capable of adding
311 PM.add(createStackSlotColoringPass(false));
312 printAndVerify(PM, "After StackSlotColoring");
315 // Run post-ra passes.
316 if (addPostRegAlloc(PM, OptLevel))
317 printAndVerify(PM, "After PostRegAlloc passes");
319 PM.add(createLowerSubregsPass());
320 printAndVerify(PM, "After LowerSubregs");
322 // Insert prolog/epilog code. Eliminate abstract frame index references...
323 PM.add(createPrologEpilogCodeInserter());
324 printAndVerify(PM, "After PrologEpilogCodeInserter");
326 // Run pre-sched2 passes.
327 if (addPreSched2(PM, OptLevel))
328 printAndVerify(PM, "After PreSched2 passes");
330 // Second pass scheduler.
331 if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
332 PM.add(createPostRAScheduler(OptLevel));
333 printAndVerify(PM, "After PostRAScheduler");
336 // Branch folding must be run after regalloc and prolog/epilog insertion.
337 if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
338 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
339 printAndVerify(PM, "After BranchFolding");
343 if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
344 PM.add(createTailDuplicatePass(false));
345 printAndVerify(PM, "After TailDuplicate");
348 PM.add(createGCMachineCodeAnalysisPass());
351 PM.add(createGCInfoPrinter(dbgs()));
353 if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
354 PM.add(createCodePlacementOptPass());
355 printAndVerify(PM, "After CodePlacementOpt");
358 if (addPreEmitPass(PM, OptLevel))
359 printAndVerify(PM, "After PreEmit passes");