lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/Collector.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Transforms/Scalar.h"
  23 #include "llvm/Support/CommandLine.h"
  24 using namespace llvm;
  25
  26 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  27     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  28 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  29     cl::desc("Print LLVM IR input to isel pass"));
  30 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  31     cl::desc("Dump emitter generated instructions as assembly"));
  32 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  33     cl::desc("Dump garbage collector data"));
  34
  35 // Hidden options to help debugging
  36 static cl::opt<bool>
  37 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
  38               cl::desc("Perform sinking on machine code"));
  39 static cl::opt<bool>
  40 AlignLoops("align-loops", cl::init(true), cl::Hidden,
  41               cl::desc("Align loop headers"));
  42 static cl::opt<bool>
  43 PerformLICM("machine-licm",
  44             cl::init(false), cl::Hidden,
  45             cl::desc("Perform loop-invariant code motion on machine code"));
  46
  47 // When this works it will be on by default.
  48 static cl::opt<bool>
  49 DisablePostRAScheduler("disable-post-RA-scheduler",
  50                        cl::desc("Disable scheduling after register allocation"),
  51                        cl::init(true));
  52
  53 FileModel::Model
  54 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  55                                        std::ostream &Out,
  56                                        CodeGenFileType FileType,
  57                                        bool Fast) {
  58   // Standard LLVM-Level Passes.
  59
  60   // Run loop strength reduction before anything else.
  61   if (!Fast) {
  62     PM.add(createLoopStrengthReducePass(getTargetLowering()));
  63     if (PrintLSR)
  64       PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
  65   }
  66
  67   PM.add(createGCLoweringPass());
  68
  69   if (!ExceptionHandling)
  70     PM.add(createLowerInvokePass(getTargetLowering()));
  71
  72   // Make sure that no unreachable blocks are instruction selected.
  73   PM.add(createUnreachableBlockEliminationPass());
  74
  75   if (!Fast)
  76     PM.add(createCodeGenPreparePass(getTargetLowering()));
  77
  78   if (PrintISelInput)
  79     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
  80                                  &cerr));
  81
  82   // Ask the target for an isel.
  83   if (addInstSelector(PM, Fast))
  84     return FileModel::Error;
  85
  86   // Print the instruction selected machine code...
  87   if (PrintMachineCode)
  88     PM.add(createMachineFunctionPrinterPass(cerr));
  89
  90   if (PerformLICM)
  91     PM.add(createMachineLICMPass());
  92
  93   if (EnableSinking)
  94     PM.add(createMachineSinkingPass());
  95
  96   // Perform register allocation to convert to a concrete x86 representation
  97   PM.add(createRegisterAllocator());
  98
  99   if (PrintMachineCode)
 100     PM.add(createMachineFunctionPrinterPass(cerr));
 101
 102   PM.add(createLowerSubregsPass());
 103
 104   if (PrintMachineCode)  // Print the subreg lowered code
 105     PM.add(createMachineFunctionPrinterPass(cerr));
 106
 107   // Run post-ra passes.
 108   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 109     PM.add(createMachineFunctionPrinterPass(cerr));
 110
 111   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 112   PM.add(createPrologEpilogCodeInserter());
 113
 114   // Second pass scheduler.
 115   if (!Fast && !DisablePostRAScheduler)
 116     PM.add(createPostRAScheduler());
 117
 118   // Branch folding must be run after regalloc and prolog/epilog insertion.
 119   if (!Fast)
 120     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 121
 122   PM.add(createGCMachineCodeAnalysisPass());
 123   if (PrintMachineCode)
 124     PM.add(createMachineFunctionPrinterPass(cerr));
 125
 126   if (PrintGCInfo)
 127     PM.add(createCollectorMetadataPrinter(*cerr));
 128
 129   // Fold redundant debug labels.
 130   PM.add(createDebugLabelFoldingPass());
 131
 132   if (PrintMachineCode)  // Print the register-allocated code
 133     PM.add(createMachineFunctionPrinterPass(cerr));
 134
 135   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 136     PM.add(createMachineFunctionPrinterPass(cerr));
 137
 138   if (AlignLoops && !OptimizeForSize)
 139     PM.add(createLoopAlignerPass());
 140
 141   switch (FileType) {
 142   default:
 143     break;
 144   case TargetMachine::AssemblyFile:
 145     if (addAssemblyEmitter(PM, Fast, Out))
 146       return FileModel::Error;
 147     return FileModel::AsmFile;
 148   case TargetMachine::ObjectFile:
 149     if (getMachOWriterInfo())
 150       return FileModel::MachOFile;
 151     else if (getELFWriterInfo())
 152       return FileModel::ElfFile;
 153   }
 154
 155   return FileModel::Error;
 156 }
 157
 158 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 159 /// be split up (e.g., to add an object writer pass), this method can be used to
 160 /// finish up adding passes to emit the file, if necessary.
 161 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 162                                                   MachineCodeEmitter *MCE,
 163                                                   bool Fast) {
 164   if (MCE)
 165     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 166
 167   PM.add(createCollectorMetadataDeleter());
 168
 169   // Delete machine code for this function
 170   PM.add(createMachineCodeDeleter());
 171
 172   return false; // success!
 173 }
 174
 175 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 176 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 177 /// actually outputting the machine code and resolving things like the address
 178 /// of functions.  This method should returns true if machine code emission is
 179 /// not supported.
 180 ///
 181 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 182                                                    MachineCodeEmitter &MCE,
 183                                                    bool Fast) {
 184   // Standard LLVM-Level Passes.
 185
 186   // Run loop strength reduction before anything else.
 187   if (!Fast) {
 188     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 189     if (PrintLSR)
 190       PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
 191   }
 192
 193   PM.add(createGCLoweringPass());
 194
 195   if (!ExceptionHandling)
 196     PM.add(createLowerInvokePass(getTargetLowering()));
 197
 198   // Make sure that no unreachable blocks are instruction selected.
 199   PM.add(createUnreachableBlockEliminationPass());
 200
 201   if (!Fast)
 202     PM.add(createCodeGenPreparePass(getTargetLowering()));
 203
 204   if (PrintISelInput)
 205     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
 206                                  &cerr));
 207
 208   // Ask the target for an isel.
 209   if (addInstSelector(PM, Fast))
 210     return true;
 211
 212   // Print the instruction selected machine code...
 213   if (PrintMachineCode)
 214     PM.add(createMachineFunctionPrinterPass(cerr));
 215
 216   if (PerformLICM)
 217     PM.add(createMachineLICMPass());
 218
 219   if (EnableSinking)
 220     PM.add(createMachineSinkingPass());
 221
 222   // Perform register allocation to convert to a concrete x86 representation
 223   PM.add(createRegisterAllocator());
 224
 225   if (PrintMachineCode)
 226     PM.add(createMachineFunctionPrinterPass(cerr));
 227
 228   PM.add(createLowerSubregsPass());
 229
 230   if (PrintMachineCode)  // Print the subreg lowered code
 231     PM.add(createMachineFunctionPrinterPass(cerr));
 232
 233   // Run post-ra passes.
 234   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 235     PM.add(createMachineFunctionPrinterPass(cerr));
 236
 237   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 238   PM.add(createPrologEpilogCodeInserter());
 239
 240   if (PrintMachineCode)  // Print the register-allocated code
 241     PM.add(createMachineFunctionPrinterPass(cerr));
 242
 243   // Second pass scheduler.
 244   if (!Fast)
 245     PM.add(createPostRAScheduler());
 246
 247   // Branch folding must be run after regalloc and prolog/epilog insertion.
 248   if (!Fast)
 249     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 250
 251   PM.add(createGCMachineCodeAnalysisPass());
 252   if (PrintMachineCode)
 253     PM.add(createMachineFunctionPrinterPass(cerr));
 254
 255   if (PrintGCInfo)
 256     PM.add(createCollectorMetadataPrinter(*cerr));
 257
 258   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 259     PM.add(createMachineFunctionPrinterPass(cerr));
 260
 261   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 262
 263   PM.add(createCollectorMetadataDeleter());
 264
 265   // Delete machine code for this function
 266   PM.add(createMachineCodeDeleter());
 267
 268   return false; // success!
 269 }