lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/Collector.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Transforms/Scalar.h"
  23 #include "llvm/Support/CommandLine.h"
  24 using namespace llvm;
  25
  26 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  27     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  28 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  29     cl::desc("Print LLVM IR input to isel pass"));
  30 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  31     cl::desc("Dump emitter generated instructions as assembly"));
  32 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  33     cl::desc("Dump garbage collector data"));
  34
  35 // Hidden options to help debugging
  36 static cl::opt<bool>
  37 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
  38               cl::desc("Perform sinking on machine code"));
  39 static cl::opt<bool>
  40 AlignLoops("align-loops", cl::init(true), cl::Hidden,
  41               cl::desc("Align loop headers"));
  42 static cl::opt<bool>
  43 PerformLICM("machine-licm",
  44             cl::init(false), cl::Hidden,
  45             cl::desc("Perform loop-invariant code motion on machine code"));
  46
  47 // When this works it will be on by default.
  48 static cl::opt<bool>
  49 DisablePostRAScheduler("disable-post-RA-scheduler",
  50                        cl::desc("Disable scheduling after register allocation"),
  51                        cl::init(true));
  52
  53 FileModel::Model
  54 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  55                                        std::ostream &Out,
  56                                        CodeGenFileType FileType,
  57                                        bool Fast) {
  58   // Standard LLVM-Level Passes.
  59
  60   // Run loop strength reduction before anything else.
  61   if (!Fast) {
  62     PM.add(createLoopStrengthReducePass(getTargetLowering()));
  63     if (PrintLSR)
  64       PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
  65   }
  66
  67   PM.add(createGCLoweringPass());
  68
  69   PM.add(createLowerInvokePass(getTargetLowering()));
  70
  71   // Make sure that no unreachable blocks are instruction selected.
  72   PM.add(createUnreachableBlockEliminationPass());
  73
  74   if (!Fast)
  75     PM.add(createCodeGenPreparePass(getTargetLowering()));
  76
  77   if (PrintISelInput)
  78     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
  79                                  &cerr));
  80
  81   // Ask the target for an isel.
  82   if (addInstSelector(PM, Fast))
  83     return FileModel::Error;
  84
  85   // Print the instruction selected machine code...
  86   if (PrintMachineCode)
  87     PM.add(createMachineFunctionPrinterPass(cerr));
  88
  89   if (PerformLICM)
  90     PM.add(createMachineLICMPass());
  91
  92   if (EnableSinking)
  93     PM.add(createMachineSinkingPass());
  94
  95   // Perform register allocation to convert to a concrete x86 representation
  96   PM.add(createRegisterAllocator());
  97
  98   if (PrintMachineCode)
  99     PM.add(createMachineFunctionPrinterPass(cerr));
 100
 101   PM.add(createLowerSubregsPass());
 102
 103   if (PrintMachineCode)  // Print the subreg lowered code
 104     PM.add(createMachineFunctionPrinterPass(cerr));
 105
 106   // Run post-ra passes.
 107   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 108     PM.add(createMachineFunctionPrinterPass(cerr));
 109
 110   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 111   PM.add(createPrologEpilogCodeInserter());
 112
 113   // Second pass scheduler.
 114   if (!Fast && !DisablePostRAScheduler)
 115     PM.add(createPostRAScheduler());
 116
 117   // Branch folding must be run after regalloc and prolog/epilog insertion.
 118   if (!Fast)
 119     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 120
 121   PM.add(createGCMachineCodeAnalysisPass());
 122   if (PrintMachineCode)
 123     PM.add(createMachineFunctionPrinterPass(cerr));
 124
 125   if (PrintGCInfo)
 126     PM.add(createCollectorMetadataPrinter(*cerr));
 127
 128   // Fold redundant debug labels.
 129   PM.add(createDebugLabelFoldingPass());
 130
 131   if (PrintMachineCode)  // Print the register-allocated code
 132     PM.add(createMachineFunctionPrinterPass(cerr));
 133
 134   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 135     PM.add(createMachineFunctionPrinterPass(cerr));
 136
 137   if (AlignLoops && !OptimizeForSize)
 138     PM.add(createLoopAlignerPass());
 139
 140   switch (FileType) {
 141   default:
 142     break;
 143   case TargetMachine::AssemblyFile:
 144     if (addAssemblyEmitter(PM, Fast, Out))
 145       return FileModel::Error;
 146     return FileModel::AsmFile;
 147   case TargetMachine::ObjectFile:
 148     if (getMachOWriterInfo())
 149       return FileModel::MachOFile;
 150     else if (getELFWriterInfo())
 151       return FileModel::ElfFile;
 152   }
 153
 154   return FileModel::Error;
 155 }
 156
 157 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 158 /// be split up (e.g., to add an object writer pass), this method can be used to
 159 /// finish up adding passes to emit the file, if necessary.
 160 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 161                                                   MachineCodeEmitter *MCE,
 162                                                   bool Fast) {
 163   if (MCE)
 164     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 165
 166   PM.add(createCollectorMetadataDeleter());
 167
 168   // Delete machine code for this function
 169   PM.add(createMachineCodeDeleter());
 170
 171   return false; // success!
 172 }
 173
 174 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 175 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 176 /// actually outputting the machine code and resolving things like the address
 177 /// of functions.  This method should returns true if machine code emission is
 178 /// not supported.
 179 ///
 180 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 181                                                    MachineCodeEmitter &MCE,
 182                                                    bool Fast) {
 183   // Standard LLVM-Level Passes.
 184
 185   // Run loop strength reduction before anything else.
 186   if (!Fast) {
 187     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 188     if (PrintLSR)
 189       PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
 190   }
 191
 192   PM.add(createGCLoweringPass());
 193
 194   PM.add(createLowerInvokePass(getTargetLowering()));
 195
 196   // Make sure that no unreachable blocks are instruction selected.
 197   PM.add(createUnreachableBlockEliminationPass());
 198
 199   if (!Fast)
 200     PM.add(createCodeGenPreparePass(getTargetLowering()));
 201
 202   if (PrintISelInput)
 203     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
 204                                  &cerr));
 205
 206   // Ask the target for an isel.
 207   if (addInstSelector(PM, Fast))
 208     return true;
 209
 210   // Print the instruction selected machine code...
 211   if (PrintMachineCode)
 212     PM.add(createMachineFunctionPrinterPass(cerr));
 213
 214   if (PerformLICM)
 215     PM.add(createMachineLICMPass());
 216
 217   if (EnableSinking)
 218     PM.add(createMachineSinkingPass());
 219
 220   // Perform register allocation to convert to a concrete x86 representation
 221   PM.add(createRegisterAllocator());
 222
 223   if (PrintMachineCode)
 224     PM.add(createMachineFunctionPrinterPass(cerr));
 225
 226   PM.add(createLowerSubregsPass());
 227
 228   if (PrintMachineCode)  // Print the subreg lowered code
 229     PM.add(createMachineFunctionPrinterPass(cerr));
 230
 231   // Run post-ra passes.
 232   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 233     PM.add(createMachineFunctionPrinterPass(cerr));
 234
 235   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 236   PM.add(createPrologEpilogCodeInserter());
 237
 238   if (PrintMachineCode)  // Print the register-allocated code
 239     PM.add(createMachineFunctionPrinterPass(cerr));
 240
 241   // Second pass scheduler.
 242   if (!Fast)
 243     PM.add(createPostRAScheduler());
 244
 245   // Branch folding must be run after regalloc and prolog/epilog insertion.
 246   if (!Fast)
 247     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 248
 249   PM.add(createGCMachineCodeAnalysisPass());
 250   if (PrintMachineCode)
 251     PM.add(createMachineFunctionPrinterPass(cerr));
 252
 253   if (PrintGCInfo)
 254     PM.add(createCollectorMetadataPrinter(*cerr));
 255
 256   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 257     PM.add(createMachineFunctionPrinterPass(cerr));
 258
 259   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 260
 261   PM.add(createCollectorMetadataDeleter());
 262
 263   // Delete machine code for this function
 264   PM.add(createMachineCodeDeleter());
 265
 266   return false; // success!
 267 }