lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/Collector.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetAsmInfo.h"
  23 #include "llvm/Transforms/Scalar.h"
  24 #include "llvm/Support/CommandLine.h"
  25 using namespace llvm;
  26
  27 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  28     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  29 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  30     cl::desc("Print LLVM IR input to isel pass"));
  31 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  32     cl::desc("Dump emitter generated instructions as assembly"));
  33 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  34     cl::desc("Dump garbage collector data"));
  35
  36 // Hidden options to help debugging
  37 static cl::opt<bool>
  38 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
  39               cl::desc("Perform sinking on machine code"));
  40 static cl::opt<bool>
  41 AlignLoops("align-loops", cl::init(true), cl::Hidden,
  42               cl::desc("Align loop headers"));
  43 static cl::opt<bool>
  44 PerformLICM("machine-licm",
  45             cl::init(false), cl::Hidden,
  46             cl::desc("Perform loop-invariant code motion on machine code"));
  47
  48 // When this works it will be on by default.
  49 static cl::opt<bool>
  50 DisablePostRAScheduler("disable-post-RA-scheduler",
  51                        cl::desc("Disable scheduling after register allocation"),
  52                        cl::init(true));
  53
  54 FileModel::Model
  55 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
  56                                        std::ostream &Out,
  57                                        CodeGenFileType FileType,
  58                                        bool Fast) {
  59   // Standard LLVM-Level Passes.
  60
  61   // Run loop strength reduction before anything else.
  62   if (!Fast) {
  63     PM.add(createLoopStrengthReducePass(getTargetLowering()));
  64     if (PrintLSR)
  65       PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
  66   }
  67
  68   PM.add(createGCLoweringPass());
  69
  70   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
  71     PM.add(createLowerInvokePass(getTargetLowering()));
  72
  73   // Make sure that no unreachable blocks are instruction selected.
  74   PM.add(createUnreachableBlockEliminationPass());
  75
  76   if (!Fast)
  77     PM.add(createCodeGenPreparePass(getTargetLowering()));
  78
  79   if (PrintISelInput)
  80     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
  81                                  &cerr));
  82
  83   // Ask the target for an isel.
  84   if (addInstSelector(PM, Fast))
  85     return FileModel::Error;
  86
  87   // Print the instruction selected machine code...
  88   if (PrintMachineCode)
  89     PM.add(createMachineFunctionPrinterPass(cerr));
  90
  91   if (PerformLICM)
  92     PM.add(createMachineLICMPass());
  93
  94   if (EnableSinking)
  95     PM.add(createMachineSinkingPass());
  96
  97   // Perform register allocation to convert to a concrete x86 representation
  98   PM.add(createRegisterAllocator());
  99
 100   if (PrintMachineCode)
 101     PM.add(createMachineFunctionPrinterPass(cerr));
 102
 103   PM.add(createLowerSubregsPass());
 104
 105   if (PrintMachineCode)  // Print the subreg lowered code
 106     PM.add(createMachineFunctionPrinterPass(cerr));
 107
 108   // Run post-ra passes.
 109   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 110     PM.add(createMachineFunctionPrinterPass(cerr));
 111
 112   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 113   PM.add(createPrologEpilogCodeInserter());
 114
 115   // Second pass scheduler.
 116   if (!Fast && !DisablePostRAScheduler)
 117     PM.add(createPostRAScheduler());
 118
 119   // Branch folding must be run after regalloc and prolog/epilog insertion.
 120   if (!Fast)
 121     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 122
 123   PM.add(createGCMachineCodeAnalysisPass());
 124   if (PrintMachineCode)
 125     PM.add(createMachineFunctionPrinterPass(cerr));
 126
 127   if (PrintGCInfo)
 128     PM.add(createCollectorMetadataPrinter(*cerr));
 129
 130   // Fold redundant debug labels.
 131   PM.add(createDebugLabelFoldingPass());
 132
 133   if (PrintMachineCode)  // Print the register-allocated code
 134     PM.add(createMachineFunctionPrinterPass(cerr));
 135
 136   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 137     PM.add(createMachineFunctionPrinterPass(cerr));
 138
 139   if (AlignLoops && !OptimizeForSize)
 140     PM.add(createLoopAlignerPass());
 141
 142   switch (FileType) {
 143   default:
 144     break;
 145   case TargetMachine::AssemblyFile:
 146     if (addAssemblyEmitter(PM, Fast, Out))
 147       return FileModel::Error;
 148     return FileModel::AsmFile;
 149   case TargetMachine::ObjectFile:
 150     if (getMachOWriterInfo())
 151       return FileModel::MachOFile;
 152     else if (getELFWriterInfo())
 153       return FileModel::ElfFile;
 154   }
 155
 156   return FileModel::Error;
 157 }
 158
 159 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 160 /// be split up (e.g., to add an object writer pass), this method can be used to
 161 /// finish up adding passes to emit the file, if necessary.
 162 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
 163                                                   MachineCodeEmitter *MCE,
 164                                                   bool Fast) {
 165   if (MCE)
 166     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 167
 168   PM.add(createCollectorMetadataDeleter());
 169
 170   // Delete machine code for this function
 171   PM.add(createMachineCodeDeleter());
 172
 173   return false; // success!
 174 }
 175
 176 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 177 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 178 /// actually outputting the machine code and resolving things like the address
 179 /// of functions.  This method should returns true if machine code emission is
 180 /// not supported.
 181 ///
 182 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
 183                                                    MachineCodeEmitter &MCE,
 184                                                    bool Fast) {
 185   // Standard LLVM-Level Passes.
 186
 187   // Run loop strength reduction before anything else.
 188   if (!Fast) {
 189     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 190     if (PrintLSR)
 191       PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
 192   }
 193
 194   PM.add(createGCLoweringPass());
 195
 196   if (!getTargetAsmInfo()->doesSupportExceptionHandling())
 197     PM.add(createLowerInvokePass(getTargetLowering()));
 198
 199   // Make sure that no unreachable blocks are instruction selected.
 200   PM.add(createUnreachableBlockEliminationPass());
 201
 202   if (!Fast)
 203     PM.add(createCodeGenPreparePass(getTargetLowering()));
 204
 205   if (PrintISelInput)
 206     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
 207                                  &cerr));
 208
 209   // Ask the target for an isel.
 210   if (addInstSelector(PM, Fast))
 211     return true;
 212
 213   // Print the instruction selected machine code...
 214   if (PrintMachineCode)
 215     PM.add(createMachineFunctionPrinterPass(cerr));
 216
 217   if (PerformLICM)
 218     PM.add(createMachineLICMPass());
 219
 220   if (EnableSinking)
 221     PM.add(createMachineSinkingPass());
 222
 223   // Perform register allocation to convert to a concrete x86 representation
 224   PM.add(createRegisterAllocator());
 225
 226   if (PrintMachineCode)
 227     PM.add(createMachineFunctionPrinterPass(cerr));
 228
 229   PM.add(createLowerSubregsPass());
 230
 231   if (PrintMachineCode)  // Print the subreg lowered code
 232     PM.add(createMachineFunctionPrinterPass(cerr));
 233
 234   // Run post-ra passes.
 235   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 236     PM.add(createMachineFunctionPrinterPass(cerr));
 237
 238   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 239   PM.add(createPrologEpilogCodeInserter());
 240
 241   if (PrintMachineCode)  // Print the register-allocated code
 242     PM.add(createMachineFunctionPrinterPass(cerr));
 243
 244   // Second pass scheduler.
 245   if (!Fast)
 246     PM.add(createPostRAScheduler());
 247
 248   // Branch folding must be run after regalloc and prolog/epilog insertion.
 249   if (!Fast)
 250     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 251
 252   PM.add(createGCMachineCodeAnalysisPass());
 253   if (PrintMachineCode)
 254     PM.add(createMachineFunctionPrinterPass(cerr));
 255
 256   if (PrintGCInfo)
 257     PM.add(createCollectorMetadataPrinter(*cerr));
 258
 259   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 260     PM.add(createMachineFunctionPrinterPass(cerr));
 261
 262   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 263
 264   PM.add(createCollectorMetadataDeleter());
 265
 266   // Delete machine code for this function
 267   PM.add(createMachineCodeDeleter());
 268
 269   return false; // success!
 270 }