1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/Analysis/LoopPass.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/GCStrategy.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetAsmInfo.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/raw_ostream.h"
32 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
33 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
34 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
35 cl::desc("Print LLVM IR input to isel pass"));
36 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
37 cl::desc("Dump emitter generated instructions as assembly"));
38 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
39 cl::desc("Dump garbage collector data"));
41 // Hidden options to help debugging
43 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
44 cl::desc("Perform sinking on machine code"));
46 // When this works it will be on by default.
48 DisablePostRAScheduler("disable-post-RA-scheduler",
49 cl::desc("Disable scheduling after register allocation"),
52 // Enable or disable FastISel. Both options are needed, because
53 // FastISel is enabled by default with -fast, and we wish to be
54 // able to enable or disable fast-isel independently from -fast.
55 static cl::opt<cl::boolOrDefault>
56 EnableFastISelOption("fast-isel", cl::Hidden,
57 cl::desc("Enable the experimental \"fast\" instruction selector"));
60 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
62 CodeGenFileType FileType,
64 // Add common CodeGen passes.
65 if (addCommonCodeGenPasses(PM, Fast))
66 return FileModel::Error;
68 // Fold redundant debug labels.
69 PM.add(createDebugLabelFoldingPass());
72 PM.add(createMachineFunctionPrinterPass(cerr));
74 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
75 PM.add(createMachineFunctionPrinterPass(cerr));
78 PM.add(createLoopAlignerPass());
83 case TargetMachine::AssemblyFile:
84 if (addAssemblyEmitter(PM, Fast, Out))
85 return FileModel::Error;
86 return FileModel::AsmFile;
87 case TargetMachine::ObjectFile:
88 if (getMachOWriterInfo())
89 return FileModel::MachOFile;
90 else if (getELFWriterInfo())
91 return FileModel::ElfFile;
94 return FileModel::Error;
97 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
98 /// be split up (e.g., to add an object writer pass), this method can be used to
99 /// finish up adding passes to emit the file, if necessary.
100 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
101 MachineCodeEmitter *MCE,
104 addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
106 PM.add(createGCInfoDeleter());
108 // Delete machine code for this function
109 PM.add(createMachineCodeDeleter());
111 return false; // success!
114 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
115 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
116 /// actually outputting the machine code and resolving things like the address
117 /// of functions. This method should returns true if machine code emission is
120 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
121 MachineCodeEmitter &MCE,
123 // Add common CodeGen passes.
124 if (addCommonCodeGenPasses(PM, Fast))
127 if (addPreEmitPass(PM, Fast) && PrintMachineCode)
128 PM.add(createMachineFunctionPrinterPass(cerr));
130 addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
132 PM.add(createGCInfoDeleter());
134 // Delete machine code for this function
135 PM.add(createMachineCodeDeleter());
137 return false; // success!
140 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
141 /// both emitting to assembly files or machine code output.
143 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
144 // Standard LLVM-Level Passes.
146 // Run loop strength reduction before anything else.
148 PM.add(createLoopStrengthReducePass(getTargetLowering()));
150 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
153 PM.add(createGCLoweringPass());
155 if (!getTargetAsmInfo()->doesSupportExceptionHandling())
156 PM.add(createLowerInvokePass(getTargetLowering()));
158 // Make sure that no unreachable blocks are instruction selected.
159 PM.add(createUnreachableBlockEliminationPass());
162 PM.add(createCodeGenPreparePass(getTargetLowering()));
164 PM.add(createStackProtectorPass(getTargetLowering()));
167 PM.add(createPrintFunctionPass("\n\n"
168 "*** Final LLVM Code input to ISel ***\n",
171 // Standard Lower-Level Passes.
173 // Enable FastISel with -fast, but allow that to be overridden.
174 if (EnableFastISelOption == cl::BOU_TRUE ||
175 (Fast && EnableFastISelOption != cl::BOU_FALSE))
176 EnableFastISel = true;
178 // Ask the target for an isel.
179 if (addInstSelector(PM, Fast))
182 // Print the instruction selected machine code...
183 if (PrintMachineCode)
184 PM.add(createMachineFunctionPrinterPass(cerr));
187 PM.add(createMachineLICMPass());
190 PM.add(createMachineSinkingPass());
192 // Run pre-ra passes.
193 if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
194 PM.add(createMachineFunctionPrinterPass(cerr));
196 // Perform register allocation.
197 PM.add(createRegisterAllocator());
199 // Perform stack slot coloring.
201 PM.add(createStackSlotColoringPass());
203 if (PrintMachineCode) // Print the register-allocated code
204 PM.add(createMachineFunctionPrinterPass(cerr));
206 // Run post-ra passes.
207 if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
208 PM.add(createMachineFunctionPrinterPass(cerr));
210 if (PrintMachineCode)
211 PM.add(createMachineFunctionPrinterPass(cerr));
213 PM.add(createLowerSubregsPass());
215 if (PrintMachineCode) // Print the subreg lowered code
216 PM.add(createMachineFunctionPrinterPass(cerr));
218 // Insert prolog/epilog code. Eliminate abstract frame index references...
219 PM.add(createPrologEpilogCodeInserter());
221 if (PrintMachineCode)
222 PM.add(createMachineFunctionPrinterPass(cerr));
224 // Second pass scheduler.
225 if (!Fast && !DisablePostRAScheduler) {
226 PM.add(createPostRAScheduler());
228 if (PrintMachineCode)
229 PM.add(createMachineFunctionPrinterPass(cerr));
232 // Branch folding must be run after regalloc and prolog/epilog insertion.
234 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
236 if (PrintMachineCode)
237 PM.add(createMachineFunctionPrinterPass(cerr));
239 PM.add(createGCMachineCodeAnalysisPass());
241 if (PrintMachineCode)
242 PM.add(createMachineFunctionPrinterPass(cerr));
245 PM.add(createGCInfoPrinter(*cerr));