1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LLVMTargetMachine class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Pass.h"
17 #include "llvm/Assembly/PrintModulePass.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/GCStrategy.h"
21 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/FormattedStream.h"
34 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
35 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
36 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
37 cl::desc("Print LLVM IR input to isel pass"));
38 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
39 cl::desc("Dump emitter generated instructions as assembly"));
40 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
41 cl::desc("Dump garbage collector data"));
42 static cl::opt<bool> HoistConstants("hoist-constants", cl::Hidden,
43 cl::desc("Hoist constants out of loops"));
44 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
45 cl::desc("Verify generated machine code"),
46 cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
48 // This is not enabled by default due to 1) high compile time cost, 2) it's not
49 // beneficial to all targets. The plan is to let targets decide whether this
52 EnablePostRAScheduler("post-RA-scheduler",
53 cl::desc("Enable scheduling after register allocation"),
56 // Enable or disable FastISel. Both options are needed, because
57 // FastISel is enabled by default with -fast, and we wish to be
58 // able to enable or disable fast-isel independently from -O0.
59 static cl::opt<cl::boolOrDefault>
60 EnableFastISelOption("fast-isel", cl::Hidden,
61 cl::desc("Enable the \"fast\" instruction selector"));
64 LLVMTargetMachine::LLVMTargetMachine(const Target &T,
65 const std::string &TargetTriple)
67 AsmInfo = T.createAsmInfo(TargetTriple);
73 LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
74 formatted_raw_ostream &Out,
75 CodeGenFileType FileType,
76 CodeGenOpt::Level OptLevel) {
77 // Add common CodeGen passes.
78 if (addCommonCodeGenPasses(PM, OptLevel))
79 return FileModel::Error;
81 // Fold redundant debug labels.
82 PM.add(createDebugLabelFoldingPass());
85 PM.add(createMachineFunctionPrinterPass(errs()));
87 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
88 PM.add(createMachineFunctionPrinterPass(errs()));
90 if (OptLevel != CodeGenOpt::None)
91 PM.add(createCodePlacementOptPass());
96 case TargetMachine::AssemblyFile:
97 if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
98 return FileModel::Error;
99 return FileModel::AsmFile;
100 case TargetMachine::ObjectFile:
101 if (getMachOWriterInfo())
102 return FileModel::MachOFile;
103 else if (getELFWriterInfo())
104 return FileModel::ElfFile;
107 return FileModel::Error;
110 bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
111 CodeGenOpt::Level OptLevel,
113 formatted_raw_ostream &Out) {
114 FunctionPass *Printer =
115 getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
123 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
124 /// be split up (e.g., to add an object writer pass), this method can be used to
125 /// finish up adding passes to emit the file, if necessary.
126 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
127 MachineCodeEmitter *MCE,
128 CodeGenOpt::Level OptLevel) {
130 addSimpleCodeEmitter(PM, OptLevel, *MCE);
132 addAssemblyEmitter(PM, OptLevel, true, ferrs());
134 PM.add(createGCInfoDeleter());
136 return false; // success!
139 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
140 /// be split up (e.g., to add an object writer pass), this method can be used to
141 /// finish up adding passes to emit the file, if necessary.
142 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
144 CodeGenOpt::Level OptLevel) {
146 addSimpleCodeEmitter(PM, OptLevel, *JCE);
148 addAssemblyEmitter(PM, OptLevel, true, ferrs());
150 PM.add(createGCInfoDeleter());
152 return false; // success!
155 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
156 /// be split up (e.g., to add an object writer pass), this method can be used to
157 /// finish up adding passes to emit the file, if necessary.
158 bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
159 ObjectCodeEmitter *OCE,
160 CodeGenOpt::Level OptLevel) {
162 addSimpleCodeEmitter(PM, OptLevel, *OCE);
164 addAssemblyEmitter(PM, OptLevel, true, ferrs());
166 PM.add(createGCInfoDeleter());
168 return false; // success!
171 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
172 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
173 /// actually outputting the machine code and resolving things like the address
174 /// of functions. This method should returns true if machine code emission is
177 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
178 MachineCodeEmitter &MCE,
179 CodeGenOpt::Level OptLevel) {
180 // Add common CodeGen passes.
181 if (addCommonCodeGenPasses(PM, OptLevel))
184 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
185 PM.add(createMachineFunctionPrinterPass(errs()));
187 addCodeEmitter(PM, OptLevel, MCE);
189 addAssemblyEmitter(PM, OptLevel, true, ferrs());
191 PM.add(createGCInfoDeleter());
193 return false; // success!
196 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
197 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
198 /// actually outputting the machine code and resolving things like the address
199 /// of functions. This method should returns true if machine code emission is
202 bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
204 CodeGenOpt::Level OptLevel) {
205 // Add common CodeGen passes.
206 if (addCommonCodeGenPasses(PM, OptLevel))
209 if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
210 PM.add(createMachineFunctionPrinterPass(errs()));
212 addCodeEmitter(PM, OptLevel, JCE);
214 addAssemblyEmitter(PM, OptLevel, true, ferrs());
216 PM.add(createGCInfoDeleter());
218 return false; // success!
221 static void printAndVerify(PassManagerBase &PM,
222 bool allowDoubleDefs = false) {
223 if (PrintMachineCode)
224 PM.add(createMachineFunctionPrinterPass(errs()));
226 if (VerifyMachineCode)
227 PM.add(createMachineVerifierPass(allowDoubleDefs));
230 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
231 /// emitting to assembly files or machine code output.
233 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
234 CodeGenOpt::Level OptLevel) {
235 // Standard LLVM-Level Passes.
237 // Run loop strength reduction before anything else.
238 if (OptLevel != CodeGenOpt::None) {
239 PM.add(createLoopStrengthReducePass(getTargetLowering()));
241 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
244 // Turn exception handling constructs into something the code generators can
246 switch (getMCAsmInfo()->getExceptionHandlingType())
248 case ExceptionHandling::SjLj:
249 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
250 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
251 PM.add(createSjLjEHPass(getTargetLowering()));
253 case ExceptionHandling::Dwarf:
254 PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
256 case ExceptionHandling::None:
257 PM.add(createLowerInvokePass(getTargetLowering()));
261 PM.add(createGCLoweringPass());
263 // Make sure that no unreachable blocks are instruction selected.
264 PM.add(createUnreachableBlockEliminationPass());
266 if (OptLevel != CodeGenOpt::None) {
268 PM.add(createCodeGenLICMPass());
269 PM.add(createCodeGenPreparePass(getTargetLowering()));
272 PM.add(createStackProtectorPass(getTargetLowering()));
275 PM.add(createPrintFunctionPass("\n\n"
276 "*** Final LLVM Code input to ISel ***\n",
279 // Standard Lower-Level Passes.
281 // Set up a MachineFunction for the rest of CodeGen to work on.
282 PM.add(new MachineFunctionAnalysis(*this, OptLevel));
284 // Enable FastISel with -fast, but allow that to be overridden.
285 if (EnableFastISelOption == cl::BOU_TRUE ||
286 (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
287 EnableFastISel = true;
289 // Ask the target for an isel.
290 if (addInstSelector(PM, OptLevel))
293 // Print the instruction selected machine code...
294 printAndVerify(PM, /* allowDoubleDefs= */ true);
296 if (OptLevel != CodeGenOpt::None) {
297 PM.add(createMachineLICMPass());
298 PM.add(createMachineSinkingPass());
299 printAndVerify(PM, /* allowDoubleDefs= */ true);
302 // Run pre-ra passes.
303 if (addPreRegAlloc(PM, OptLevel))
304 printAndVerify(PM, /* allowDoubleDefs= */ true);
306 // Perform register allocation.
307 PM.add(createRegisterAllocator());
309 // Perform stack slot coloring.
310 if (OptLevel != CodeGenOpt::None)
311 // FIXME: Re-enable coloring with register when it's capable of adding
313 PM.add(createStackSlotColoringPass(false));
315 printAndVerify(PM); // Print the register-allocated code
317 // Run post-ra passes.
318 if (addPostRegAlloc(PM, OptLevel))
321 PM.add(createLowerSubregsPass());
324 // Insert prolog/epilog code. Eliminate abstract frame index references...
325 PM.add(createPrologEpilogCodeInserter());
328 // Second pass scheduler.
329 if (OptLevel != CodeGenOpt::None && EnablePostRAScheduler) {
330 PM.add(createPostRAScheduler());
334 // Branch folding must be run after regalloc and prolog/epilog insertion.
335 if (OptLevel != CodeGenOpt::None) {
336 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
340 PM.add(createGCMachineCodeAnalysisPass());
344 PM.add(createGCInfoPrinter(errs()));