lib/CodeGen/LLVMTargetMachine.cpp

   1 //===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the LLVMTargetMachine class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/Target/TargetMachine.h"
  15 #include "llvm/PassManager.h"
  16 #include "llvm/Pass.h"
  17 #include "llvm/Assembly/PrintModulePass.h"
  18 #include "llvm/Analysis/LoopPass.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/CodeGen/Collector.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Transforms/Scalar.h"
  23 #include "llvm/Support/CommandLine.h"
  24 using namespace llvm;
  25
  26 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
  27     cl::desc("Print LLVM IR produced by the loop-reduce pass"));
  28 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
  29     cl::desc("Print LLVM IR input to isel pass"));
  30 static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
  31     cl::desc("Dump emitter generated instructions as assembly"));
  32 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
  33     cl::desc("Dump garbage collector data"));
  34
  35 // Hidden options to help debugging
  36 static cl::opt<bool>
  37 EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
  38               cl::desc("Perform sinking on machine code"));
  39 static cl::opt<bool>
  40 PerformLICM("machine-licm",
  41             cl::init(false), cl::Hidden,
  42             cl::desc("Perform loop-invariant code motion on machine code"));
  43
  44 // When this works it will be on by default.
  45 static cl::opt<bool>
  46 DisablePostRAScheduler("disable-post-RA-scheduler",
  47                        cl::desc("Disable scheduling after register allocation"),
  48                        cl::init(true));
  49
  50 FileModel::Model
  51 LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM,
  52                                        std::ostream &Out,
  53                                        CodeGenFileType FileType,
  54                                        bool Fast) {
  55   // Standard LLVM-Level Passes.
  56
  57   // Run loop strength reduction before anything else.
  58   if (!Fast) {
  59     PM.add(createLoopStrengthReducePass(getTargetLowering()));
  60     if (PrintLSR)
  61       PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
  62   }
  63
  64   PM.add(createGCLoweringPass());
  65
  66   if (!ExceptionHandling)
  67     PM.add(createLowerInvokePass(getTargetLowering()));
  68
  69   // Make sure that no unreachable blocks are instruction selected.
  70   PM.add(createUnreachableBlockEliminationPass());
  71
  72   if (!Fast)
  73     PM.add(createCodeGenPreparePass(getTargetLowering()));
  74
  75   if (PrintISelInput)
  76     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
  77                                  &cerr));
  78
  79   // Ask the target for an isel.
  80   if (addInstSelector(PM, Fast))
  81     return FileModel::Error;
  82
  83   // Print the instruction selected machine code...
  84   if (PrintMachineCode)
  85     PM.add(createMachineFunctionPrinterPass(cerr));
  86
  87   if (PerformLICM)
  88     PM.add(createMachineLICMPass());
  89
  90   if (EnableSinking)
  91     PM.add(createMachineSinkingPass());
  92
  93   // Perform register allocation to convert to a concrete x86 representation
  94   PM.add(createRegisterAllocator());
  95
  96   if (PrintMachineCode)
  97     PM.add(createMachineFunctionPrinterPass(cerr));
  98
  99   PM.add(createLowerSubregsPass());
 100
 101   if (PrintMachineCode)  // Print the subreg lowered code
 102     PM.add(createMachineFunctionPrinterPass(cerr));
 103
 104   // Run post-ra passes.
 105   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 106     PM.add(createMachineFunctionPrinterPass(cerr));
 107
 108   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 109   PM.add(createPrologEpilogCodeInserter());
 110
 111   // Second pass scheduler.
 112   if (!Fast && !DisablePostRAScheduler)
 113     PM.add(createPostRAScheduler());
 114
 115   // Branch folding must be run after regalloc and prolog/epilog insertion.
 116   if (!Fast)
 117     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 118
 119   PM.add(createGCMachineCodeAnalysisPass());
 120   if (PrintMachineCode)
 121     PM.add(createMachineFunctionPrinterPass(cerr));
 122
 123   if (PrintGCInfo)
 124     PM.add(createCollectorMetadataPrinter(*cerr));
 125
 126   // Fold redundant debug labels.
 127   PM.add(createDebugLabelFoldingPass());
 128
 129   if (PrintMachineCode)  // Print the register-allocated code
 130     PM.add(createMachineFunctionPrinterPass(cerr));
 131
 132   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 133     PM.add(createMachineFunctionPrinterPass(cerr));
 134
 135   switch (FileType) {
 136   default:
 137     break;
 138   case TargetMachine::AssemblyFile:
 139     if (addAssemblyEmitter(PM, Fast, Out))
 140       return FileModel::Error;
 141     return FileModel::AsmFile;
 142   case TargetMachine::ObjectFile:
 143     if (getMachOWriterInfo())
 144       return FileModel::MachOFile;
 145     else if (getELFWriterInfo())
 146       return FileModel::ElfFile;
 147   }
 148
 149   return FileModel::Error;
 150 }
 151
 152 /// addPassesToEmitFileFinish - If the passes to emit the specified file had to
 153 /// be split up (e.g., to add an object writer pass), this method can be used to
 154 /// finish up adding passes to emit the file, if necessary.
 155 bool LLVMTargetMachine::addPassesToEmitFileFinish(FunctionPassManager &PM,
 156                                                   MachineCodeEmitter *MCE,
 157                                                   bool Fast) {
 158   if (MCE)
 159     addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
 160
 161   PM.add(createCollectorMetadataDeleter());
 162
 163   // Delete machine code for this function
 164   PM.add(createMachineCodeDeleter());
 165
 166   return false; // success!
 167 }
 168
 169 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
 170 /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
 171 /// actually outputting the machine code and resolving things like the address
 172 /// of functions.  This method should returns true if machine code emission is
 173 /// not supported.
 174 ///
 175 bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
 176                                                    MachineCodeEmitter &MCE,
 177                                                    bool Fast) {
 178   // Standard LLVM-Level Passes.
 179
 180   // Run loop strength reduction before anything else.
 181   if (!Fast) {
 182     PM.add(createLoopStrengthReducePass(getTargetLowering()));
 183     if (PrintLSR)
 184       PM.add(new PrintFunctionPass("\n\n*** Code after LSR *** \n", &cerr));
 185   }
 186
 187   PM.add(createGCLoweringPass());
 188
 189   if (!ExceptionHandling)
 190     PM.add(createLowerInvokePass(getTargetLowering()));
 191
 192   // Make sure that no unreachable blocks are instruction selected.
 193   PM.add(createUnreachableBlockEliminationPass());
 194
 195   if (!Fast)
 196     PM.add(createCodeGenPreparePass(getTargetLowering()));
 197
 198   if (PrintISelInput)
 199     PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel *** \n",
 200                                  &cerr));
 201
 202   // Ask the target for an isel.
 203   if (addInstSelector(PM, Fast))
 204     return true;
 205
 206   // Print the instruction selected machine code...
 207   if (PrintMachineCode)
 208     PM.add(createMachineFunctionPrinterPass(cerr));
 209
 210   if (PerformLICM)
 211     PM.add(createMachineLICMPass());
 212
 213   if (EnableSinking)
 214     PM.add(createMachineSinkingPass());
 215
 216   // Perform register allocation to convert to a concrete x86 representation
 217   PM.add(createRegisterAllocator());
 218
 219   if (PrintMachineCode)
 220     PM.add(createMachineFunctionPrinterPass(cerr));
 221
 222   PM.add(createLowerSubregsPass());
 223
 224   if (PrintMachineCode)  // Print the subreg lowered code
 225     PM.add(createMachineFunctionPrinterPass(cerr));
 226
 227   // Run post-ra passes.
 228   if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
 229     PM.add(createMachineFunctionPrinterPass(cerr));
 230
 231   // Insert prolog/epilog code.  Eliminate abstract frame index references...
 232   PM.add(createPrologEpilogCodeInserter());
 233
 234   if (PrintMachineCode)  // Print the register-allocated code
 235     PM.add(createMachineFunctionPrinterPass(cerr));
 236
 237   // Second pass scheduler.
 238   if (!Fast)
 239     PM.add(createPostRAScheduler());
 240
 241   // Branch folding must be run after regalloc and prolog/epilog insertion.
 242   if (!Fast)
 243     PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
 244
 245   PM.add(createGCMachineCodeAnalysisPass());
 246   if (PrintMachineCode)
 247     PM.add(createMachineFunctionPrinterPass(cerr));
 248
 249   if (PrintGCInfo)
 250     PM.add(createCollectorMetadataPrinter(*cerr));
 251
 252   if (addPreEmitPass(PM, Fast) && PrintMachineCode)
 253     PM.add(createMachineFunctionPrinterPass(cerr));
 254
 255   addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
 256
 257   PM.add(createCollectorMetadataDeleter());
 258
 259   // Delete machine code for this function
 260   PM.add(createMachineCodeDeleter());
 261
 262   return false; // success!
 263 }