1 //===-- InstrSelectionSupport.cpp -----------------------------------------===//
3 // Target-independent instruction selection code. See SparcInstrSelection.cpp
6 //===----------------------------------------------------------------------===//
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/InstrSelection.h"
10 #include "llvm/CodeGen/MachineInstrAnnot.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/InstrForest.h"
13 #include "llvm/Target/TargetMachine.h"
14 #include "llvm/Target/TargetRegInfo.h"
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Constants.h"
17 #include "llvm/BasicBlock.h"
18 #include "llvm/DerivedTypes.h"
19 #include "../../Target/Sparc/SparcInstrSelectionSupport.h" // FIXME!
22 // Generate code to load the constant into a TmpInstruction (virtual reg) and
23 // returns the virtual register.
25 static TmpInstruction*
26 InsertCodeToLoadConstant(Function *F,
29 std::vector<MachineInstr*>& loadConstVec,
30 TargetMachine& target)
32 // Create a tmp virtual register to hold the constant.
33 MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
34 TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
36 target.getInstrInfo().CreateCodeToLoadConst(target, F, opValue, tmpReg,
39 // Record the mapping from the tmp VM instruction to machine instruction.
40 // Do this for all machine instructions that were not mapped to any
41 // other temp values created by
42 // tmpReg->addMachineInstruction(loadConstVec.back());
48 MachineOperand::MachineOperandType
49 ChooseRegOrImmed(int64_t intValue,
52 const TargetMachine& target,
54 unsigned int& getMachineRegNum,
55 int64_t& getImmedValue)
57 MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
62 target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
64 opType = isSigned? MachineOperand::MO_SignExtendedImmed
65 : MachineOperand::MO_UnextendedImmed;
66 getImmedValue = intValue;
68 else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
70 opType = MachineOperand::MO_MachineRegister;
71 getMachineRegNum = target.getRegInfo().getZeroRegNum();
78 MachineOperand::MachineOperandType
79 ChooseRegOrImmed(Value* val,
81 const TargetMachine& target,
83 unsigned int& getMachineRegNum,
84 int64_t& getImmedValue)
89 // To use reg or immed, constant needs to be integer, bool, or a NULL pointer
90 Constant *CPV = dyn_cast<Constant>(val);
92 || CPV->isConstantExpr()
93 || (! CPV->getType()->isIntegral() &&
94 ! (isa<PointerType>(CPV->getType()) && CPV->isNullValue())))
95 return MachineOperand::MO_VirtualRegister;
97 // Now get the constant value and check if it fits in the IMMED field.
98 // Take advantage of the fact that the max unsigned value will rarely
99 // fit into any IMMED field and ignore that case (i.e., cast smaller
100 // unsigned constants to signed).
103 if (isa<PointerType>(CPV->getType()))
104 intValue = 0; // We checked above that it is NULL
105 else if (ConstantBool* CB = dyn_cast<ConstantBool>(CPV))
106 intValue = (int64_t) CB->getValue();
107 else if (CPV->getType()->isSigned())
108 intValue = cast<ConstantSInt>(CPV)->getValue();
110 { // get the int value and sign-extend if original was less than 64 bits
111 intValue = (int64_t) cast<ConstantUInt>(CPV)->getValue();
112 switch(CPV->getType()->getPrimitiveID())
114 case Type::UByteTyID: intValue = (int64_t) (int8_t) intValue; break;
115 case Type::UShortTyID: intValue = (int64_t) (short) intValue; break;
116 case Type::UIntTyID: intValue = (int64_t) (int) intValue; break;
121 return ChooseRegOrImmed(intValue, CPV->getType()->isSigned(),
122 opCode, target, canUseImmed,
123 getMachineRegNum, getImmedValue);
128 //---------------------------------------------------------------------------
129 // Function: FixConstantOperandsForInstr
132 // Special handling for constant operands of a machine instruction
133 // -- if the constant is 0, use the hardwired 0 register, if any;
134 // -- if the constant fits in the IMMEDIATE field, use that field;
135 // -- else create instructions to put the constant into a register, either
136 // directly or by loading explicitly from the constant pool.
138 // In the first 2 cases, the operand of `minstr' is modified in place.
139 // Returns a vector of machine instructions generated for operands that
140 // fall under case 3; these must be inserted before `minstr'.
141 //---------------------------------------------------------------------------
143 std::vector<MachineInstr*>
144 FixConstantOperandsForInstr(Instruction* vmInstr,
145 MachineInstr* minstr,
146 TargetMachine& target)
148 std::vector<MachineInstr*> MVec;
150 MachineOpCode opCode = minstr->getOpCode();
151 const TargetInstrInfo& instrInfo = target.getInstrInfo();
152 int resultPos = instrInfo.getResultPos(opCode);
153 int immedPos = instrInfo.getImmedConstantPos(opCode);
155 Function *F = vmInstr->getParent()->getParent();
157 for (unsigned op=0; op < minstr->getNumOperands(); op++)
159 const MachineOperand& mop = minstr->getOperand(op);
161 // Skip the result position, preallocated machine registers, or operands
162 // that cannot be constants (CC regs or PC-relative displacements)
163 if (resultPos == (int)op ||
164 mop.getType() == MachineOperand::MO_MachineRegister ||
165 mop.getType() == MachineOperand::MO_CCRegister ||
166 mop.getType() == MachineOperand::MO_PCRelativeDisp)
169 bool constantThatMustBeLoaded = false;
170 unsigned int machineRegNum = 0;
171 int64_t immedValue = 0;
172 Value* opValue = NULL;
173 MachineOperand::MachineOperandType opType =
174 MachineOperand::MO_VirtualRegister;
176 // Operand may be a virtual register or a compile-time constant
177 if (mop.getType() == MachineOperand::MO_VirtualRegister)
179 assert(mop.getVRegValue() != NULL);
180 opValue = mop.getVRegValue();
181 if (Constant *opConst = dyn_cast<Constant>(opValue)) {
182 opType = ChooseRegOrImmed(opConst, opCode, target,
183 (immedPos == (int)op), machineRegNum,
185 if (opType == MachineOperand::MO_VirtualRegister)
186 constantThatMustBeLoaded = true;
191 assert(mop.isImmediate());
192 bool isSigned = mop.getType() == MachineOperand::MO_SignExtendedImmed;
194 // Bit-selection flags indicate an instruction that is extracting
195 // bits from its operand so ignore this even if it is a big constant.
196 if (mop.opHiBits32() || mop.opLoBits32() ||
197 mop.opHiBits64() || mop.opLoBits64())
200 opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
201 opCode, target, (immedPos == (int)op),
202 machineRegNum, immedValue);
204 if (opType == MachineOperand::MO_SignExtendedImmed ||
205 opType == MachineOperand::MO_UnextendedImmed) {
206 // The optype is an immediate value
207 // This means we need to change the opcode, e.g. ADDr -> ADDi
208 unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
209 minstr->setOpcode(newOpcode);
212 if (opType == mop.getType())
213 continue; // no change: this is the most common case
215 if (opType == MachineOperand::MO_VirtualRegister)
217 constantThatMustBeLoaded = true;
219 ? (Value*)ConstantSInt::get(Type::LongTy, immedValue)
220 : (Value*)ConstantUInt::get(Type::ULongTy,(uint64_t)immedValue);
224 if (opType == MachineOperand::MO_MachineRegister)
225 minstr->SetMachineOperandReg(op, machineRegNum);
226 else if (opType == MachineOperand::MO_SignExtendedImmed ||
227 opType == MachineOperand::MO_UnextendedImmed) {
228 minstr->SetMachineOperandConst(op, opType, immedValue);
229 // The optype is or has become an immediate
230 // This means we need to change the opcode, e.g. ADDr -> ADDi
231 unsigned newOpcode = convertOpcodeFromRegToImm(opCode);
232 minstr->setOpcode(newOpcode);
233 } else if (constantThatMustBeLoaded ||
234 (opValue && isa<GlobalValue>(opValue)))
235 { // opValue is a constant that must be explicitly loaded into a reg
237 TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
239 minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
244 // Also, check for implicit operands used by the machine instruction
245 // (no need to check those defined since they cannot be constants).
247 // -- arguments to a Call
248 // -- return value of a Return
249 // Any such operand that is a constant value needs to be fixed also.
250 // The current instructions with implicit refs (viz., Call and Return)
251 // have no immediate fields, so the constant always needs to be loaded
254 bool isCall = instrInfo.isCall(opCode);
255 unsigned lastCallArgNum = 0; // unused if not a call
256 CallArgsDescriptor* argDesc = NULL; // unused if not a call
258 argDesc = CallArgsDescriptor::get(minstr);
260 for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
261 if (isa<Constant>(minstr->getImplicitRef(i)) ||
262 isa<GlobalValue>(minstr->getImplicitRef(i)))
264 Value* oldVal = minstr->getImplicitRef(i);
265 TmpInstruction* tmpReg =
266 InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
267 minstr->setImplicitRef(i, tmpReg);
270 { // find and replace the argument in the CallArgsDescriptor
271 unsigned i=lastCallArgNum;
272 while (argDesc->getArgInfo(i).getArgVal() != oldVal)
274 assert(i < argDesc->getNumArgs() &&
275 "Constant operands to a call *must* be in the arg list");
277 argDesc->getArgInfo(i).replaceArgVal(tmpReg);