1 //===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
3 // Scheduling graph based on SSA graph plus extra dependence edges capturing
4 // dependences due to machine resources (machine registers, CC registers, and
7 //===----------------------------------------------------------------------===//
9 #include "SchedGraph.h"
10 #include "llvm/CodeGen/InstrSelection.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/MachineFunction.h"
13 #include "llvm/Target/TargetRegInfo.h"
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetInstrInfo.h"
16 #include "llvm/Function.h"
17 #include "llvm/iOther.h"
18 #include "Support/StringExtras.h"
19 #include "Support/STLExtras.h"
21 //*********************** Internal Data Structures *************************/
23 // The following two types need to be classes, not typedefs, so we can use
24 // opaque declarations in SchedGraph.h
26 struct RefVec: public std::vector<std::pair<SchedGraphNode*, int> > {
27 typedef std::vector<std::pair<SchedGraphNode*,int> >::iterator iterator;
29 std::vector<std::pair<SchedGraphNode*,int> >::const_iterator const_iterator;
32 struct RegToRefVecMap: public hash_map<int, RefVec> {
33 typedef hash_map<int, RefVec>:: iterator iterator;
34 typedef hash_map<int, RefVec>::const_iterator const_iterator;
37 struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
38 typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
39 typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
43 // class SchedGraphEdge
47 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
48 SchedGraphNode* _sink,
49 SchedGraphEdgeDepType _depType,
50 unsigned int _depOrderType,
55 depOrderType(_depOrderType),
56 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
59 assert(src != sink && "Self-loop in scheduling graph!");
60 src->addOutEdge(this);
61 sink->addInEdge(this);
66 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
67 SchedGraphNode* _sink,
69 unsigned int _depOrderType,
74 depOrderType(_depOrderType),
75 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
78 assert(src != sink && "Self-loop in scheduling graph!");
79 src->addOutEdge(this);
80 sink->addInEdge(this);
85 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
86 SchedGraphNode* _sink,
88 unsigned int _depOrderType,
92 depType(MachineRegister),
93 depOrderType(_depOrderType),
94 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
95 machineRegNum(_regNum)
97 assert(src != sink && "Self-loop in scheduling graph!");
98 src->addOutEdge(this);
99 sink->addInEdge(this);
104 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
105 SchedGraphNode* _sink,
106 ResourceId _resourceId,
110 depType(MachineResource),
111 depOrderType(NonDataDep),
112 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
113 resourceId(_resourceId)
115 assert(src != sink && "Self-loop in scheduling graph!");
116 src->addOutEdge(this);
117 sink->addInEdge(this);
121 SchedGraphEdge::~SchedGraphEdge()
125 void SchedGraphEdge::dump(int indent) const {
126 std::cerr << std::string(indent*2, ' ') << *this;
131 // class SchedGraphNode
135 SchedGraphNode::SchedGraphNode(unsigned NID,
136 MachineBasicBlock *mbb,
138 const TargetMachine& Target)
139 : nodeId(NID), MBB(mbb), minstr(mbb ? (*mbb)[indexInBB] : 0),
140 origIndexInBB(indexInBB), latency(0) {
143 MachineOpCode mopCode = minstr->getOpCode();
144 latency = Target.getInstrInfo().hasResultInterlock(mopCode)
145 ? Target.getInstrInfo().minLatency(mopCode)
146 : Target.getInstrInfo().maxLatency(mopCode);
152 SchedGraphNode::~SchedGraphNode()
154 // for each node, delete its out-edges
155 std::for_each(beginOutEdges(), endOutEdges(),
156 deleter<SchedGraphEdge>);
159 void SchedGraphNode::dump(int indent) const {
160 std::cerr << std::string(indent*2, ' ') << *this;
165 SchedGraphNode::addInEdge(SchedGraphEdge* edge)
167 inEdges.push_back(edge);
172 SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
174 outEdges.push_back(edge);
178 SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
180 assert(edge->getSink() == this);
182 for (iterator I = beginInEdges(); I != endInEdges(); ++I)
191 SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
193 assert(edge->getSrc() == this);
195 for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
210 SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
217 SchedGraph::~SchedGraph()
219 for (const_iterator I = begin(); I != end(); ++I)
227 SchedGraph::dump() const
229 std::cerr << " Sched Graph for Basic Block: ";
230 std::cerr << MBB.getBasicBlock()->getName()
231 << " (" << MBB.getBasicBlock() << ")";
233 std::cerr << "\n\n Actual Root nodes : ";
234 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
235 std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
236 << ((i == N-1)? "" : ", ");
238 std::cerr << "\n Graph Nodes:\n";
239 for (const_iterator I=begin(); I != end(); ++I)
240 std::cerr << "\n" << *I->second;
247 SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
249 // Delete and disconnect all in-edges for the node
250 for (SchedGraphNode::iterator I = node->beginInEdges();
251 I != node->endInEdges(); ++I)
253 SchedGraphNode* srcNode = (*I)->getSrc();
254 srcNode->removeOutEdge(*I);
258 srcNode != getRoot() &&
259 srcNode->beginOutEdges() == srcNode->endOutEdges())
260 { // srcNode has no more out edges, so add an edge to dummy EXIT node
261 assert(node != getLeaf() && "Adding edge that was just removed?");
262 (void) new SchedGraphEdge(srcNode, getLeaf(),
263 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
267 node->inEdges.clear();
271 SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
273 // Delete and disconnect all out-edges for the node
274 for (SchedGraphNode::iterator I = node->beginOutEdges();
275 I != node->endOutEdges(); ++I)
277 SchedGraphNode* sinkNode = (*I)->getSink();
278 sinkNode->removeInEdge(*I);
282 sinkNode != getLeaf() &&
283 sinkNode->beginInEdges() == sinkNode->endInEdges())
284 { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
285 assert(node != getRoot() && "Adding edge that was just removed?");
286 (void) new SchedGraphEdge(getRoot(), sinkNode,
287 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
291 node->outEdges.clear();
295 SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
297 this->eraseIncomingEdges(node, addDummyEdges);
298 this->eraseOutgoingEdges(node, addDummyEdges);
303 SchedGraph::addDummyEdges()
305 assert(graphRoot->outEdges.size() == 0);
307 for (const_iterator I=begin(); I != end(); ++I)
309 SchedGraphNode* node = (*I).second;
310 assert(node != graphRoot && node != graphLeaf);
311 if (node->beginInEdges() == node->endInEdges())
312 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
313 SchedGraphEdge::NonDataDep, 0);
314 if (node->beginOutEdges() == node->endOutEdges())
315 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
316 SchedGraphEdge::NonDataDep, 0);
322 SchedGraph::addCDEdges(const TerminatorInst* term,
323 const TargetMachine& target)
325 const TargetInstrInfo& mii = target.getInstrInfo();
326 MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
328 // Find the first branch instr in the sequence of machine instrs for term
331 while (! mii.isBranch(termMvec[first]->getOpCode()) &&
332 ! mii.isReturn(termMvec[first]->getOpCode()))
334 assert(first < termMvec.size() &&
335 "No branch instructions for terminator? Ok, but weird!");
336 if (first == termMvec.size())
339 SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
341 // Add CD edges from each instruction in the sequence to the
342 // *last preceding* branch instr. in the sequence
343 // Use a latency of 0 because we only need to prevent out-of-order issue.
345 for (unsigned i = termMvec.size(); i > first+1; --i)
347 SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
348 assert(toNode && "No node for instr generated for branch/ret?");
350 for (unsigned j = i-1; j != 0; --j)
351 if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
352 mii.isReturn(termMvec[j-1]->getOpCode()))
354 SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
355 assert(brNode && "No node for instr generated for branch/ret?");
356 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
357 SchedGraphEdge::NonDataDep, 0);
358 break; // only one incoming edge is enough
362 // Add CD edges from each instruction preceding the first branch
363 // to the first branch. Use a latency of 0 as above.
365 for (unsigned i = first; i != 0; --i)
367 SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
368 assert(fromNode && "No node for instr generated for branch?");
369 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
370 SchedGraphEdge::NonDataDep, 0);
373 // Now add CD edges to the first branch instruction in the sequence from
374 // all preceding instructions in the basic block. Use 0 latency again.
376 for (unsigned i=0, N=MBB.size(); i < N; i++)
378 if (MBB[i] == termMvec[first]) // reached the first branch
381 SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
382 if (fromNode == NULL)
383 continue; // dummy instruction, e.g., PHI
385 (void) new SchedGraphEdge(fromNode, firstBrNode,
386 SchedGraphEdge::CtrlDep,
387 SchedGraphEdge::NonDataDep, 0);
389 // If we find any other machine instructions (other than due to
390 // the terminator) that also have delay slots, add an outgoing edge
391 // from the instruction to the instructions in the delay slots.
393 unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
394 assert(i+d < N && "Insufficient delay slots for instruction?");
396 for (unsigned j=1; j <= d; j++)
398 SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
399 assert(toNode && "No node for machine instr in delay slot?");
400 (void) new SchedGraphEdge(fromNode, toNode,
401 SchedGraphEdge::CtrlDep,
402 SchedGraphEdge::NonDataDep, 0);
407 static const int SG_LOAD_REF = 0;
408 static const int SG_STORE_REF = 1;
409 static const int SG_CALL_REF = 2;
411 static const unsigned int SG_DepOrderArray[][3] = {
412 { SchedGraphEdge::NonDataDep,
413 SchedGraphEdge::AntiDep,
414 SchedGraphEdge::AntiDep },
415 { SchedGraphEdge::TrueDep,
416 SchedGraphEdge::OutputDep,
417 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
418 { SchedGraphEdge::TrueDep,
419 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
420 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
421 | SchedGraphEdge::OutputDep }
425 // Add a dependence edge between every pair of machine load/store/call
426 // instructions, where at least one is a store or a call.
427 // Use latency 1 just to ensure that memory operations are ordered;
428 // latency does not otherwise matter (true dependences enforce that).
431 SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
432 const TargetMachine& target)
434 const TargetInstrInfo& mii = target.getInstrInfo();
436 // Instructions in memNodeVec are in execution order within the basic block,
437 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
439 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
441 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
442 int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
443 : mii.isLoad(fromOpCode)? SG_LOAD_REF
445 for (unsigned jm=im+1; jm < NM; jm++)
447 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
448 int toType = mii.isCall(toOpCode)? SG_CALL_REF
449 : mii.isLoad(toOpCode)? SG_LOAD_REF
452 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
453 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
454 SchedGraphEdge::MemoryDep,
455 SG_DepOrderArray[fromType][toType], 1);
460 // Add edges from/to CC reg instrs to/from call instrs.
461 // Essentially this prevents anything that sets or uses a CC reg from being
462 // reordered w.r.t. a call.
463 // Use a latency of 0 because we only need to prevent out-of-order issue,
464 // like with control dependences.
467 SchedGraph::addCallCCEdges(const std::vector<SchedGraphNode*>& memNodeVec,
468 MachineBasicBlock& bbMvec,
469 const TargetMachine& target)
471 const TargetInstrInfo& mii = target.getInstrInfo();
472 std::vector<SchedGraphNode*> callNodeVec;
474 // Find the call instruction nodes and put them in a vector.
475 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
476 if (mii.isCall(memNodeVec[im]->getOpCode()))
477 callNodeVec.push_back(memNodeVec[im]);
479 // Now walk the entire basic block, looking for CC instructions *and*
480 // call instructions, and keep track of the order of the instructions.
481 // Use the call node vec to quickly find earlier and later call nodes
482 // relative to the current CC instruction.
484 int lastCallNodeIdx = -1;
485 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
486 if (mii.isCall(bbMvec[i]->getOpCode()))
489 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
490 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
492 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
494 else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
495 { // Add incoming/outgoing edges from/to preceding/later calls
496 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
498 for ( ; j <= lastCallNodeIdx; j++)
499 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
500 MachineCCRegsRID, 0);
501 for ( ; j < (int) callNodeVec.size(); j++)
502 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
503 MachineCCRegsRID, 0);
509 SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
510 const TargetMachine& target)
512 // This assumes that such hardwired registers are never allocated
513 // to any LLVM value (since register allocation happens later), i.e.,
514 // any uses or defs of this register have been made explicit!
515 // Also assumes that two registers with different numbers are
518 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
519 I != regToRefVecMap.end(); ++I)
521 int regNum = (*I).first;
522 RefVec& regRefVec = (*I).second;
524 // regRefVec is ordered by control flow order in the basic block
525 for (unsigned i=0; i < regRefVec.size(); ++i)
527 SchedGraphNode* node = regRefVec[i].first;
528 unsigned int opNum = regRefVec[i].second;
529 bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
531 node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
533 for (unsigned p=0; p < i; ++p)
535 SchedGraphNode* prevNode = regRefVec[p].first;
536 if (prevNode != node)
538 unsigned int prevOpNum = regRefVec[p].second;
540 prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
541 bool prevIsDefAndUse =
542 prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
546 new SchedGraphEdge(prevNode, node, regNum,
547 SchedGraphEdge::OutputDep);
548 if (!prevIsDef || prevIsDefAndUse)
549 new SchedGraphEdge(prevNode, node, regNum,
550 SchedGraphEdge::AntiDep);
554 if (!isDef || isDefAndUse)
555 new SchedGraphEdge(prevNode, node, regNum,
556 SchedGraphEdge::TrueDep);
564 // Adds dependences to/from refNode from/to all other defs
565 // in the basic block. refNode may be a use, a def, or both.
566 // We do not consider other uses because we are not building use-use deps.
569 SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
570 const RefVec& defVec,
571 const Value* defValue,
573 bool refNodeIsDefAndUse,
574 const TargetMachine& target)
576 bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
578 // Add true or output dep edges from all def nodes before refNode in BB.
579 // Add anti or output dep edges to all def nodes after refNode.
580 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
582 if ((*I).first == refNode)
583 continue; // Dont add any self-loops
585 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
586 { // (*).first is before refNode
588 (void) new SchedGraphEdge((*I).first, refNode, defValue,
589 SchedGraphEdge::OutputDep);
591 (void) new SchedGraphEdge((*I).first, refNode, defValue,
592 SchedGraphEdge::TrueDep);
595 { // (*).first is after refNode
597 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
598 SchedGraphEdge::OutputDep);
600 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
601 SchedGraphEdge::AntiDep);
608 SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
609 const ValueToDefVecMap& valueToDefVecMap,
610 const TargetMachine& target)
612 SchedGraphNode* node = getGraphNodeForInstr(&MI);
616 // Add edges for all operands of the machine instruction.
618 for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
620 switch (MI.getOperandType(i))
622 case MachineOperand::MO_VirtualRegister:
623 case MachineOperand::MO_CCRegister:
624 if (const Instruction* srcI =
625 dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
627 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
628 if (I != valueToDefVecMap.end())
629 addEdgesForValue(node, I->second, srcI,
630 MI.operandIsDefined(i),
631 MI.operandIsDefinedAndUsed(i), target);
635 case MachineOperand::MO_MachineRegister:
638 case MachineOperand::MO_SignExtendedImmed:
639 case MachineOperand::MO_UnextendedImmed:
640 case MachineOperand::MO_PCRelativeDisp:
641 break; // nothing to do for immediate fields
644 assert(0 && "Unknown machine operand type in SchedGraph builder");
649 // Add edges for values implicitly used by the machine instruction.
650 // Examples include function arguments to a Call instructions or the return
651 // value of a Ret instruction.
653 for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
654 if (! MI.implicitRefIsDefined(i) ||
655 MI.implicitRefIsDefinedAndUsed(i))
656 if (const Instruction *srcI =
657 dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
659 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
660 if (I != valueToDefVecMap.end())
661 addEdgesForValue(node, I->second, srcI,
662 MI.implicitRefIsDefined(i),
663 MI.implicitRefIsDefinedAndUsed(i), target);
669 SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
670 SchedGraphNode* node,
671 std::vector<SchedGraphNode*>& memNodeVec,
672 RegToRefVecMap& regToRefVecMap,
673 ValueToDefVecMap& valueToDefVecMap)
675 const TargetInstrInfo& mii = target.getInstrInfo();
678 MachineOpCode opCode = node->getOpCode();
679 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
680 memNodeVec.push_back(node);
682 // Collect the register references and value defs. for explicit operands
684 const MachineInstr& minstr = *node->getMachineInstr();
685 for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
687 const MachineOperand& mop = minstr.getOperand(i);
689 // if this references a register other than the hardwired
690 // "zero" register, record the reference.
691 if (mop.getType() == MachineOperand::MO_MachineRegister)
693 int regNum = mop.getMachineRegNum();
694 if (regNum != target.getRegInfo().getZeroRegNum())
695 regToRefVecMap[mop.getMachineRegNum()].push_back(
696 std::make_pair(node, i));
697 continue; // nothing more to do
700 // ignore all other non-def operands
701 if (! minstr.operandIsDefined(i))
704 // We must be defining a value.
705 assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
706 mop.getType() == MachineOperand::MO_CCRegister)
707 && "Do not expect any other kind of operand to be defined!");
709 const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
710 valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
714 // Collect value defs. for implicit operands. The interface to extract
715 // them assumes they must be virtual registers!
717 for (unsigned i=0, N = minstr.getNumImplicitRefs(); i != N; ++i)
718 if (minstr.implicitRefIsDefined(i))
719 if (const Instruction* defInstr =
720 dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
721 valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
726 SchedGraph::buildNodesForBB(const TargetMachine& target,
727 MachineBasicBlock& MBB,
728 std::vector<SchedGraphNode*>& memNodeVec,
729 RegToRefVecMap& regToRefVecMap,
730 ValueToDefVecMap& valueToDefVecMap)
732 const TargetInstrInfo& mii = target.getInstrInfo();
734 // Build graph nodes for each VM instruction and gather def/use info.
735 // Do both those together in a single pass over all machine instructions.
736 for (unsigned i=0; i < MBB.size(); i++)
737 if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
738 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
739 noteGraphNodeForInstr(MBB[i], node);
741 // Remember all register references and value defs
742 findDefUseInfoAtInstr(target, node, memNodeVec, regToRefVecMap,
749 SchedGraph::buildGraph(const TargetMachine& target)
751 // Use this data structure to note all machine operands that compute
752 // ordinary LLVM values. These must be computed defs (i.e., instructions).
753 // Note that there may be multiple machine instructions that define
755 ValueToDefVecMap valueToDefVecMap;
757 // Use this data structure to note all memory instructions.
758 // We use this to add memory dependence edges without a second full walk.
760 // vector<const Instruction*> memVec;
761 std::vector<SchedGraphNode*> memNodeVec;
763 // Use this data structure to note any uses or definitions of
764 // machine registers so we can add edges for those later without
765 // extra passes over the nodes.
766 // The vector holds an ordered list of references to the machine reg,
767 // ordered according to control-flow order. This only works for a
768 // single basic block, hence the assertion. Each reference is identified
769 // by the pair: <node, operand-number>.
771 RegToRefVecMap regToRefVecMap;
773 // Make a dummy root node. We'll add edges to the real roots later.
774 graphRoot = new SchedGraphNode(0, NULL, -1, target);
775 graphLeaf = new SchedGraphNode(1, NULL, -1, target);
777 //----------------------------------------------------------------
778 // First add nodes for all the machine instructions in the basic block
779 // because this greatly simplifies identifying which edges to add.
780 // Do this one VM instruction at a time since the SchedGraphNode needs that.
781 // Also, remember the load/store instructions to add memory deps later.
782 //----------------------------------------------------------------
784 buildNodesForBB(target, MBB, memNodeVec, regToRefVecMap, valueToDefVecMap);
786 //----------------------------------------------------------------
787 // Now add edges for the following (all are incoming edges except (4)):
788 // (1) operands of the machine instruction, including hidden operands
789 // (2) machine register dependences
790 // (3) memory load/store dependences
791 // (3) other resource dependences for the machine instruction, if any
792 // (4) output dependences when multiple machine instructions define the
793 // same value; all must have been generated from a single VM instrn
794 // (5) control dependences to branch instructions generated for the
795 // terminator instruction of the BB. Because of delay slots and
796 // 2-way conditional branches, multiple CD edges are needed
797 // (see addCDEdges for details).
798 // Also, note any uses or defs of machine registers.
800 //----------------------------------------------------------------
802 // First, add edges to the terminator instruction of the basic block.
803 this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
805 // Then add memory dep edges: store->load, load->store, and store->store.
806 // Call instructions are treated as both load and store.
807 this->addMemEdges(memNodeVec, target);
809 // Then add edges between call instructions and CC set/use instructions
810 this->addCallCCEdges(memNodeVec, MBB, target);
812 // Then add incoming def-use (SSA) edges for each machine instruction.
813 for (unsigned i=0, N=MBB.size(); i < N; i++)
814 addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
816 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
817 // Then add non-SSA edges for all VM instructions in the block.
818 // We assume that all machine instructions that define a value are
819 // generated from the VM instruction corresponding to that value.
820 // TODO: This could probably be done much more efficiently.
821 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
822 this->addNonSSAEdgesForValue(*II, target);
823 #endif //NEED_SEPARATE_NONSSA_EDGES_CODE
825 // Then add edges for dependences on machine registers
826 this->addMachineRegEdges(regToRefVecMap, target);
828 // Finally, add edges from the dummy root and to dummy leaf
829 this->addDummyEdges();
834 // class SchedGraphSet
838 SchedGraphSet::SchedGraphSet(const Function* _function,
839 const TargetMachine& target) :
842 buildGraphsForMethod(method, target);
847 SchedGraphSet::~SchedGraphSet()
849 // delete all the graphs
850 for(iterator I = begin(), E = end(); I != E; ++I)
851 delete *I; // destructor is a friend
856 SchedGraphSet::dump() const
858 std::cerr << "======== Sched graphs for function `" << method->getName()
861 for (const_iterator I=begin(); I != end(); ++I)
864 std::cerr << "\n====== End graphs for function `" << method->getName()
870 SchedGraphSet::buildGraphsForMethod(const Function *F,
871 const TargetMachine& target)
873 MachineFunction &MF = MachineFunction::get(F);
874 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
875 addGraph(new SchedGraph(*I, target));
879 std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge)
881 os << "edge [" << edge.src->getNodeId() << "] -> ["
882 << edge.sink->getNodeId() << "] : ";
884 switch(edge.depType) {
885 case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
886 case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
887 case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
888 case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
889 case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
890 default: assert(0); break;
893 os << " : delay = " << edge.minDelay << "\n";
898 std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
900 os << std::string(8, ' ')
901 << "Node " << node.nodeId << " : "
902 << "latency = " << node.latency << "\n" << std::string(12, ' ');
904 if (node.getMachineInstr() == NULL)
905 os << "(Dummy node)\n";
908 os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
909 os << node.inEdges.size() << " Incoming Edges:\n";
910 for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
911 os << std::string(16, ' ') << *node.inEdges[i];
913 os << std::string(12, ' ') << node.outEdges.size()
914 << " Outgoing Edges:\n";
915 for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
916 os << std::string(16, ' ') << *node.outEdges[i];