1 //===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
3 // Scheduling graph based on SSA graph plus extra dependence edges capturing
4 // dependences due to machine resources (machine registers, CC registers, and
7 //===----------------------------------------------------------------------===//
9 #include "SchedGraph.h"
10 #include "llvm/CodeGen/InstrSelection.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/MachineBasicBlock.h"
13 #include "llvm/Target/MachineRegInfo.h"
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/MachineInstrInfo.h"
16 #include "llvm/Function.h"
17 #include "llvm/iOther.h"
18 #include "Support/StringExtras.h"
19 #include "Support/STLExtras.h"
25 //*********************** Internal Data Structures *************************/
27 // The following two types need to be classes, not typedefs, so we can use
28 // opaque declarations in SchedGraph.h
30 struct RefVec: public vector< pair<SchedGraphNode*, int> > {
31 typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
32 typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
35 struct RegToRefVecMap: public hash_map<int, RefVec> {
36 typedef hash_map<int, RefVec>:: iterator iterator;
37 typedef hash_map<int, RefVec>::const_iterator const_iterator;
40 struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
41 typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
42 typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
46 // class SchedGraphEdge
50 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
51 SchedGraphNode* _sink,
52 SchedGraphEdgeDepType _depType,
53 unsigned int _depOrderType,
58 depOrderType(_depOrderType),
59 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
62 assert(src != sink && "Self-loop in scheduling graph!");
63 src->addOutEdge(this);
64 sink->addInEdge(this);
69 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
70 SchedGraphNode* _sink,
72 unsigned int _depOrderType,
77 depOrderType(_depOrderType),
78 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
81 assert(src != sink && "Self-loop in scheduling graph!");
82 src->addOutEdge(this);
83 sink->addInEdge(this);
88 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
89 SchedGraphNode* _sink,
91 unsigned int _depOrderType,
95 depType(MachineRegister),
96 depOrderType(_depOrderType),
97 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
98 machineRegNum(_regNum)
100 assert(src != sink && "Self-loop in scheduling graph!");
101 src->addOutEdge(this);
102 sink->addInEdge(this);
107 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
108 SchedGraphNode* _sink,
109 ResourceId _resourceId,
113 depType(MachineResource),
114 depOrderType(NonDataDep),
115 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
116 resourceId(_resourceId)
118 assert(src != sink && "Self-loop in scheduling graph!");
119 src->addOutEdge(this);
120 sink->addInEdge(this);
124 SchedGraphEdge::~SchedGraphEdge()
128 void SchedGraphEdge::dump(int indent) const {
129 cerr << std::string(indent*2, ' ') << *this;
134 // class SchedGraphNode
138 SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
139 const BasicBlock* _bb,
140 const MachineInstr* _minstr,
142 const TargetMachine& target)
146 origIndexInBB(indexInBB),
151 MachineOpCode mopCode = minstr->getOpCode();
152 latency = target.getInstrInfo().hasResultInterlock(mopCode)
153 ? target.getInstrInfo().minLatency(mopCode)
154 : target.getInstrInfo().maxLatency(mopCode);
160 SchedGraphNode::~SchedGraphNode()
162 // for each node, delete its out-edges
163 std::for_each(beginOutEdges(), endOutEdges(),
164 deleter<SchedGraphEdge>);
167 void SchedGraphNode::dump(int indent) const {
168 cerr << std::string(indent*2, ' ') << *this;
173 SchedGraphNode::addInEdge(SchedGraphEdge* edge)
175 inEdges.push_back(edge);
180 SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
182 outEdges.push_back(edge);
186 SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
188 assert(edge->getSink() == this);
190 for (iterator I = beginInEdges(); I != endInEdges(); ++I)
199 SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
201 assert(edge->getSrc() == this);
203 for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
218 SchedGraph::SchedGraph(const BasicBlock* bb,
219 const TargetMachine& target)
227 SchedGraph::~SchedGraph()
229 for (const_iterator I = begin(); I != end(); ++I)
237 SchedGraph::dump() const
239 cerr << " Sched Graph for Basic Blocks: ";
240 for (unsigned i=0, N=bbVec.size(); i < N; i++)
242 cerr << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
243 << " (" << bbVec[i] << ")"
244 << ((i == N-1)? "" : ", ");
247 cerr << "\n\n Actual Root nodes : ";
248 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
249 cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
250 << ((i == N-1)? "" : ", ");
252 cerr << "\n Graph Nodes:\n";
253 for (const_iterator I=begin(); I != end(); ++I)
254 cerr << "\n" << *I->second;
261 SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
263 // Delete and disconnect all in-edges for the node
264 for (SchedGraphNode::iterator I = node->beginInEdges();
265 I != node->endInEdges(); ++I)
267 SchedGraphNode* srcNode = (*I)->getSrc();
268 srcNode->removeOutEdge(*I);
272 srcNode != getRoot() &&
273 srcNode->beginOutEdges() == srcNode->endOutEdges())
274 { // srcNode has no more out edges, so add an edge to dummy EXIT node
275 assert(node != getLeaf() && "Adding edge that was just removed?");
276 (void) new SchedGraphEdge(srcNode, getLeaf(),
277 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
281 node->inEdges.clear();
285 SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
287 // Delete and disconnect all out-edges for the node
288 for (SchedGraphNode::iterator I = node->beginOutEdges();
289 I != node->endOutEdges(); ++I)
291 SchedGraphNode* sinkNode = (*I)->getSink();
292 sinkNode->removeInEdge(*I);
296 sinkNode != getLeaf() &&
297 sinkNode->beginInEdges() == sinkNode->endInEdges())
298 { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
299 assert(node != getRoot() && "Adding edge that was just removed?");
300 (void) new SchedGraphEdge(getRoot(), sinkNode,
301 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
305 node->outEdges.clear();
309 SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
311 this->eraseIncomingEdges(node, addDummyEdges);
312 this->eraseOutgoingEdges(node, addDummyEdges);
317 SchedGraph::addDummyEdges()
319 assert(graphRoot->outEdges.size() == 0);
321 for (const_iterator I=begin(); I != end(); ++I)
323 SchedGraphNode* node = (*I).second;
324 assert(node != graphRoot && node != graphLeaf);
325 if (node->beginInEdges() == node->endInEdges())
326 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
327 SchedGraphEdge::NonDataDep, 0);
328 if (node->beginOutEdges() == node->endOutEdges())
329 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
330 SchedGraphEdge::NonDataDep, 0);
336 SchedGraph::addCDEdges(const TerminatorInst* term,
337 const TargetMachine& target)
339 const MachineInstrInfo& mii = target.getInstrInfo();
340 MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
342 // Find the first branch instr in the sequence of machine instrs for term
345 while (! mii.isBranch(termMvec[first]->getOpCode()) &&
346 ! mii.isReturn(termMvec[first]->getOpCode()))
348 assert(first < termMvec.size() &&
349 "No branch instructions for terminator? Ok, but weird!");
350 if (first == termMvec.size())
353 SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
355 // Add CD edges from each instruction in the sequence to the
356 // *last preceding* branch instr. in the sequence
357 // Use a latency of 0 because we only need to prevent out-of-order issue.
359 for (unsigned i = termMvec.size(); i > first+1; --i)
361 SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
362 assert(toNode && "No node for instr generated for branch/ret?");
364 for (unsigned j = i-1; j != 0; --j)
365 if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
366 mii.isReturn(termMvec[j-1]->getOpCode()))
368 SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
369 assert(brNode && "No node for instr generated for branch/ret?");
370 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
371 SchedGraphEdge::NonDataDep, 0);
372 break; // only one incoming edge is enough
376 // Add CD edges from each instruction preceding the first branch
377 // to the first branch. Use a latency of 0 as above.
379 for (unsigned i = first; i != 0; --i)
381 SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
382 assert(fromNode && "No node for instr generated for branch?");
383 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
384 SchedGraphEdge::NonDataDep, 0);
387 // Now add CD edges to the first branch instruction in the sequence from
388 // all preceding instructions in the basic block. Use 0 latency again.
390 const BasicBlock* bb = firstBrNode->getBB();
391 const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
392 for (unsigned i=0, N=mvec.size(); i < N; i++)
394 if (mvec[i] == termMvec[first]) // reached the first branch
397 SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
398 if (fromNode == NULL)
399 continue; // dummy instruction, e.g., PHI
401 (void) new SchedGraphEdge(fromNode, firstBrNode,
402 SchedGraphEdge::CtrlDep,
403 SchedGraphEdge::NonDataDep, 0);
405 // If we find any other machine instructions (other than due to
406 // the terminator) that also have delay slots, add an outgoing edge
407 // from the instruction to the instructions in the delay slots.
409 unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
410 assert(i+d < N && "Insufficient delay slots for instruction?");
412 for (unsigned j=1; j <= d; j++)
414 SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
415 assert(toNode && "No node for machine instr in delay slot?");
416 (void) new SchedGraphEdge(fromNode, toNode,
417 SchedGraphEdge::CtrlDep,
418 SchedGraphEdge::NonDataDep, 0);
423 static const int SG_LOAD_REF = 0;
424 static const int SG_STORE_REF = 1;
425 static const int SG_CALL_REF = 2;
427 static const unsigned int SG_DepOrderArray[][3] = {
428 { SchedGraphEdge::NonDataDep,
429 SchedGraphEdge::AntiDep,
430 SchedGraphEdge::AntiDep },
431 { SchedGraphEdge::TrueDep,
432 SchedGraphEdge::OutputDep,
433 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
434 { SchedGraphEdge::TrueDep,
435 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
436 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
437 | SchedGraphEdge::OutputDep }
441 // Add a dependence edge between every pair of machine load/store/call
442 // instructions, where at least one is a store or a call.
443 // Use latency 1 just to ensure that memory operations are ordered;
444 // latency does not otherwise matter (true dependences enforce that).
447 SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
448 const TargetMachine& target)
450 const MachineInstrInfo& mii = target.getInstrInfo();
452 // Instructions in memNodeVec are in execution order within the basic block,
453 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
455 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
457 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
458 int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
459 : mii.isLoad(fromOpCode)? SG_LOAD_REF
461 for (unsigned jm=im+1; jm < NM; jm++)
463 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
464 int toType = mii.isCall(toOpCode)? SG_CALL_REF
465 : mii.isLoad(toOpCode)? SG_LOAD_REF
468 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
469 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
470 SchedGraphEdge::MemoryDep,
471 SG_DepOrderArray[fromType][toType], 1);
476 // Add edges from/to CC reg instrs to/from call instrs.
477 // Essentially this prevents anything that sets or uses a CC reg from being
478 // reordered w.r.t. a call.
479 // Use a latency of 0 because we only need to prevent out-of-order issue,
480 // like with control dependences.
483 SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
484 MachineBasicBlock& bbMvec,
485 const TargetMachine& target)
487 const MachineInstrInfo& mii = target.getInstrInfo();
488 vector<SchedGraphNode*> callNodeVec;
490 // Find the call instruction nodes and put them in a vector.
491 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
492 if (mii.isCall(memNodeVec[im]->getOpCode()))
493 callNodeVec.push_back(memNodeVec[im]);
495 // Now walk the entire basic block, looking for CC instructions *and*
496 // call instructions, and keep track of the order of the instructions.
497 // Use the call node vec to quickly find earlier and later call nodes
498 // relative to the current CC instruction.
500 int lastCallNodeIdx = -1;
501 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
502 if (mii.isCall(bbMvec[i]->getOpCode()))
505 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
506 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
508 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
510 else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
511 { // Add incoming/outgoing edges from/to preceding/later calls
512 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
514 for ( ; j <= lastCallNodeIdx; j++)
515 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
516 MachineCCRegsRID, 0);
517 for ( ; j < (int) callNodeVec.size(); j++)
518 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
519 MachineCCRegsRID, 0);
525 SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
526 const TargetMachine& target)
528 assert(bbVec.size() == 1 && "Only handling a single basic block here");
530 // This assumes that such hardwired registers are never allocated
531 // to any LLVM value (since register allocation happens later), i.e.,
532 // any uses or defs of this register have been made explicit!
533 // Also assumes that two registers with different numbers are
536 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
537 I != regToRefVecMap.end(); ++I)
539 int regNum = (*I).first;
540 RefVec& regRefVec = (*I).second;
542 // regRefVec is ordered by control flow order in the basic block
543 for (unsigned i=0; i < regRefVec.size(); ++i)
545 SchedGraphNode* node = regRefVec[i].first;
546 unsigned int opNum = regRefVec[i].second;
547 bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
549 node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
551 for (unsigned p=0; p < i; ++p)
553 SchedGraphNode* prevNode = regRefVec[p].first;
554 if (prevNode != node)
556 unsigned int prevOpNum = regRefVec[p].second;
558 prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
559 bool prevIsDefAndUse =
560 prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
564 new SchedGraphEdge(prevNode, node, regNum,
565 SchedGraphEdge::OutputDep);
566 if (!prevIsDef || prevIsDefAndUse)
567 new SchedGraphEdge(prevNode, node, regNum,
568 SchedGraphEdge::AntiDep);
572 if (!isDef || isDefAndUse)
573 new SchedGraphEdge(prevNode, node, regNum,
574 SchedGraphEdge::TrueDep);
582 // Adds dependences to/from refNode from/to all other defs
583 // in the basic block. refNode may be a use, a def, or both.
584 // We do not consider other uses because we are not building use-use deps.
587 SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
588 const RefVec& defVec,
589 const Value* defValue,
591 bool refNodeIsDefAndUse,
592 const TargetMachine& target)
594 bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
596 // Add true or output dep edges from all def nodes before refNode in BB.
597 // Add anti or output dep edges to all def nodes after refNode.
598 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
600 if ((*I).first == refNode)
601 continue; // Dont add any self-loops
603 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
604 { // (*).first is before refNode
606 (void) new SchedGraphEdge((*I).first, refNode, defValue,
607 SchedGraphEdge::OutputDep);
609 (void) new SchedGraphEdge((*I).first, refNode, defValue,
610 SchedGraphEdge::TrueDep);
613 { // (*).first is after refNode
615 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
616 SchedGraphEdge::OutputDep);
618 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
619 SchedGraphEdge::AntiDep);
626 SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
627 const ValueToDefVecMap& valueToDefVecMap,
628 const TargetMachine& target)
630 SchedGraphNode* node = getGraphNodeForInstr(&MI);
634 // Add edges for all operands of the machine instruction.
636 for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
638 switch (MI.getOperandType(i))
640 case MachineOperand::MO_VirtualRegister:
641 case MachineOperand::MO_CCRegister:
642 if (const Instruction* srcI =
643 dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
645 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
646 if (I != valueToDefVecMap.end())
647 addEdgesForValue(node, I->second, srcI,
648 MI.operandIsDefined(i),
649 MI.operandIsDefinedAndUsed(i), target);
653 case MachineOperand::MO_MachineRegister:
656 case MachineOperand::MO_SignExtendedImmed:
657 case MachineOperand::MO_UnextendedImmed:
658 case MachineOperand::MO_PCRelativeDisp:
659 break; // nothing to do for immediate fields
662 assert(0 && "Unknown machine operand type in SchedGraph builder");
667 // Add edges for values implicitly used by the machine instruction.
668 // Examples include function arguments to a Call instructions or the return
669 // value of a Ret instruction.
671 for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
672 if (! MI.implicitRefIsDefined(i) ||
673 MI.implicitRefIsDefinedAndUsed(i))
674 if (const Instruction *srcI =
675 dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
677 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
678 if (I != valueToDefVecMap.end())
679 addEdgesForValue(node, I->second, srcI,
680 MI.implicitRefIsDefined(i),
681 MI.implicitRefIsDefinedAndUsed(i), target);
687 SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
688 SchedGraphNode* node,
689 vector<SchedGraphNode*>& memNodeVec,
690 RegToRefVecMap& regToRefVecMap,
691 ValueToDefVecMap& valueToDefVecMap)
693 const MachineInstrInfo& mii = target.getInstrInfo();
696 MachineOpCode opCode = node->getOpCode();
697 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
698 memNodeVec.push_back(node);
700 // Collect the register references and value defs. for explicit operands
702 const MachineInstr& minstr = *node->getMachineInstr();
703 for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
705 const MachineOperand& mop = minstr.getOperand(i);
707 // if this references a register other than the hardwired
708 // "zero" register, record the reference.
709 if (mop.getType() == MachineOperand::MO_MachineRegister)
711 int regNum = mop.getMachineRegNum();
712 if (regNum != target.getRegInfo().getZeroRegNum())
713 regToRefVecMap[mop.getMachineRegNum()].push_back(
714 std::make_pair(node, i));
715 continue; // nothing more to do
718 // ignore all other non-def operands
719 if (! minstr.operandIsDefined(i))
722 // We must be defining a value.
723 assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
724 mop.getType() == MachineOperand::MO_CCRegister)
725 && "Do not expect any other kind of operand to be defined!");
727 const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
728 valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
732 // Collect value defs. for implicit operands. The interface to extract
733 // them assumes they must be virtual registers!
735 for (int i=0, N = (int) minstr.getNumImplicitRefs(); i < N; ++i)
736 if (minstr.implicitRefIsDefined(i))
737 if (const Instruction* defInstr =
738 dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
740 valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
746 SchedGraph::buildNodesforBB(const TargetMachine& target,
747 const BasicBlock* bb,
748 vector<SchedGraphNode*>& memNodeVec,
749 RegToRefVecMap& regToRefVecMap,
750 ValueToDefVecMap& valueToDefVecMap)
752 const MachineInstrInfo& mii = target.getInstrInfo();
754 // Build graph nodes for each VM instruction and gather def/use info.
755 // Do both those together in a single pass over all machine instructions.
756 const MachineBasicBlock& mvec = MachineBasicBlock::get(bb);
757 for (unsigned i=0; i < mvec.size(); i++)
758 if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
760 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
762 this->noteGraphNodeForInstr(mvec[i], node);
764 // Remember all register references and value defs
765 findDefUseInfoAtInstr(target, node,
766 memNodeVec, regToRefVecMap,valueToDefVecMap);
769 #undef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
770 #ifdef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
771 // This is a BIG UGLY HACK. IT NEEDS TO BE ELIMINATED.
772 // Look for copy instructions inserted in this BB due to Phi instructions
773 // in the successor BBs.
774 // There MUST be exactly one copy per Phi in successor nodes.
776 for (BasicBlock::succ_const_iterator SI=bb->succ_begin(), SE=bb->succ_end();
778 for (BasicBlock::const_iterator PI=(*SI)->begin(), PE=(*SI)->end();
781 if ((*PI)->getOpcode() != Instruction::PHINode)
782 break; // No more Phis in this successor
784 // Find the incoming value from block bb to block (*SI)
785 int bbIndex = cast<PHINode>(*PI)->getBasicBlockIndex(bb);
786 assert(bbIndex >= 0 && "But I know bb is a predecessor of (*SI)?");
787 Value* inVal = cast<PHINode>(*PI)->getIncomingValue(bbIndex);
788 assert(inVal != NULL && "There must be an in-value on every edge");
790 // Find the machine instruction that makes a copy of inval to (*PI).
791 // This must be in the current basic block (bb).
792 const MachineCodeForVMInstr& mvec = MachineBasicBlock::get(*PI);
793 const MachineInstr* theCopy = NULL;
794 for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
795 if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
796 // not a Phi: assume this is a copy and examine its operands
797 for (int o=0, N=(int) mvec[i]->getNumOperands(); o < N; o++)
799 const MachineOperand& mop = mvec[i]->getOperand(o);
801 if (mvec[i]->operandIsDefined(o))
802 assert(mop.getVRegValue() == (*PI) && "dest shd be my Phi");
804 if (! mvec[i]->operandIsDefined(o) ||
805 NOT NEEDED? mvec[i]->operandIsDefinedAndUsed(o))
806 if (mop.getVRegValue() == inVal)
813 // Found the dang instruction. Now create a node and do the rest...
816 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
817 theCopy, origIndexInBB++, target);
818 this->noteGraphNodeForInstr(theCopy, node);
819 findDefUseInfoAtInstr(target, node,
820 memNodeVec, regToRefVecMap,valueToDefVecMap);
823 #endif //REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
828 SchedGraph::buildGraph(const TargetMachine& target)
830 const BasicBlock* bb = bbVec[0];
832 assert(bbVec.size() == 1 && "Only handling a single basic block here");
834 // Use this data structure to note all machine operands that compute
835 // ordinary LLVM values. These must be computed defs (i.e., instructions).
836 // Note that there may be multiple machine instructions that define
838 ValueToDefVecMap valueToDefVecMap;
840 // Use this data structure to note all memory instructions.
841 // We use this to add memory dependence edges without a second full walk.
843 // vector<const Instruction*> memVec;
844 vector<SchedGraphNode*> memNodeVec;
846 // Use this data structure to note any uses or definitions of
847 // machine registers so we can add edges for those later without
848 // extra passes over the nodes.
849 // The vector holds an ordered list of references to the machine reg,
850 // ordered according to control-flow order. This only works for a
851 // single basic block, hence the assertion. Each reference is identified
852 // by the pair: <node, operand-number>.
854 RegToRefVecMap regToRefVecMap;
856 // Make a dummy root node. We'll add edges to the real roots later.
857 graphRoot = new SchedGraphNode(0, NULL, NULL, -1, target);
858 graphLeaf = new SchedGraphNode(1, NULL, NULL, -1, target);
860 //----------------------------------------------------------------
861 // First add nodes for all the machine instructions in the basic block
862 // because this greatly simplifies identifying which edges to add.
863 // Do this one VM instruction at a time since the SchedGraphNode needs that.
864 // Also, remember the load/store instructions to add memory deps later.
865 //----------------------------------------------------------------
867 buildNodesforBB(target, bb, memNodeVec, regToRefVecMap, valueToDefVecMap);
869 //----------------------------------------------------------------
870 // Now add edges for the following (all are incoming edges except (4)):
871 // (1) operands of the machine instruction, including hidden operands
872 // (2) machine register dependences
873 // (3) memory load/store dependences
874 // (3) other resource dependences for the machine instruction, if any
875 // (4) output dependences when multiple machine instructions define the
876 // same value; all must have been generated from a single VM instrn
877 // (5) control dependences to branch instructions generated for the
878 // terminator instruction of the BB. Because of delay slots and
879 // 2-way conditional branches, multiple CD edges are needed
880 // (see addCDEdges for details).
881 // Also, note any uses or defs of machine registers.
883 //----------------------------------------------------------------
885 MachineBasicBlock& bbMvec = MachineBasicBlock::get(bb);
887 // First, add edges to the terminator instruction of the basic block.
888 this->addCDEdges(bb->getTerminator(), target);
890 // Then add memory dep edges: store->load, load->store, and store->store.
891 // Call instructions are treated as both load and store.
892 this->addMemEdges(memNodeVec, target);
894 // Then add edges between call instructions and CC set/use instructions
895 this->addCallCCEdges(memNodeVec, bbMvec, target);
897 // Then add incoming def-use (SSA) edges for each machine instruction.
898 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
899 addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
901 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
902 // Then add non-SSA edges for all VM instructions in the block.
903 // We assume that all machine instructions that define a value are
904 // generated from the VM instruction corresponding to that value.
905 // TODO: This could probably be done much more efficiently.
906 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
907 this->addNonSSAEdgesForValue(*II, target);
908 #endif //NEED_SEPARATE_NONSSA_EDGES_CODE
910 // Then add edges for dependences on machine registers
911 this->addMachineRegEdges(regToRefVecMap, target);
913 // Finally, add edges from the dummy root and to dummy leaf
914 this->addDummyEdges();
919 // class SchedGraphSet
923 SchedGraphSet::SchedGraphSet(const Function* _function,
924 const TargetMachine& target) :
927 buildGraphsForMethod(method, target);
932 SchedGraphSet::~SchedGraphSet()
934 // delete all the graphs
935 for(iterator I = begin(), E = end(); I != E; ++I)
936 delete *I; // destructor is a friend
941 SchedGraphSet::dump() const
943 cerr << "======== Sched graphs for function `" << method->getName()
946 for (const_iterator I=begin(); I != end(); ++I)
949 cerr << "\n====== End graphs for function `" << method->getName()
955 SchedGraphSet::buildGraphsForMethod(const Function *F,
956 const TargetMachine& target)
958 for (Function::const_iterator BI = F->begin(); BI != F->end(); ++BI)
959 addGraph(new SchedGraph(BI, target));
963 std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge)
965 os << "edge [" << edge.src->getNodeId() << "] -> ["
966 << edge.sink->getNodeId() << "] : ";
968 switch(edge.depType) {
969 case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
970 case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
971 case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
972 case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
973 case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
974 default: assert(0); break;
977 os << " : delay = " << edge.minDelay << "\n";
982 std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
984 os << std::string(8, ' ')
985 << "Node " << node.nodeId << " : "
986 << "latency = " << node.latency << "\n" << std::string(12, ' ');
988 if (node.getMachineInstr() == NULL)
989 os << "(Dummy node)\n";
992 os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
993 os << node.inEdges.size() << " Incoming Edges:\n";
994 for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
995 os << std::string(16, ' ') << *node.inEdges[i];
997 os << std::string(12, ' ') << node.outEdges.size()
998 << " Outgoing Edges:\n";
999 for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
1000 os << std::string(16, ' ') << *node.outEdges[i];