2 //***************************************************************************
7 // Scheduling graph based on SSA graph plus extra dependence edges
8 // capturing dependences due to machine resources (machine registers,
9 // CC registers, and any others).
12 // 7/20/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #include "SchedGraph.h"
16 #include "llvm/CodeGen/InstrSelection.h"
17 #include "llvm/CodeGen/MachineCodeForInstruction.h"
18 #include "llvm/CodeGen/MachineCodeForBasicBlock.h"
19 #include "llvm/Target/MachineRegInfo.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/BasicBlock.h"
22 #include "llvm/Function.h"
23 #include "llvm/iOther.h"
24 #include "Support/StringExtras.h"
25 #include "Support/STLExtras.h"
33 //*********************** Internal Data Structures *************************/
35 // The following two types need to be classes, not typedefs, so we can use
36 // opaque declarations in SchedGraph.h
38 struct RefVec: public vector< pair<SchedGraphNode*, int> > {
39 typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
40 typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
43 struct RegToRefVecMap: public hash_map<int, RefVec> {
44 typedef hash_map<int, RefVec>:: iterator iterator;
45 typedef hash_map<int, RefVec>::const_iterator const_iterator;
48 struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
49 typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
50 typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
54 // class SchedGraphEdge
58 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
59 SchedGraphNode* _sink,
60 SchedGraphEdgeDepType _depType,
61 unsigned int _depOrderType,
66 depOrderType(_depOrderType),
67 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
70 assert(src != sink && "Self-loop in scheduling graph!");
71 src->addOutEdge(this);
72 sink->addInEdge(this);
77 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
78 SchedGraphNode* _sink,
80 unsigned int _depOrderType,
85 depOrderType(_depOrderType),
86 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
89 assert(src != sink && "Self-loop in scheduling graph!");
90 src->addOutEdge(this);
91 sink->addInEdge(this);
96 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
97 SchedGraphNode* _sink,
99 unsigned int _depOrderType,
103 depType(MachineRegister),
104 depOrderType(_depOrderType),
105 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
106 machineRegNum(_regNum)
108 assert(src != sink && "Self-loop in scheduling graph!");
109 src->addOutEdge(this);
110 sink->addInEdge(this);
115 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
116 SchedGraphNode* _sink,
117 ResourceId _resourceId,
121 depType(MachineResource),
122 depOrderType(NonDataDep),
123 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
124 resourceId(_resourceId)
126 assert(src != sink && "Self-loop in scheduling graph!");
127 src->addOutEdge(this);
128 sink->addInEdge(this);
132 SchedGraphEdge::~SchedGraphEdge()
136 void SchedGraphEdge::dump(int indent=0) const {
137 cerr << std::string(indent*2, ' ') << *this;
142 // class SchedGraphNode
146 SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
147 const BasicBlock* _bb,
148 const MachineInstr* _minstr,
150 const TargetMachine& target)
154 origIndexInBB(indexInBB),
159 MachineOpCode mopCode = minstr->getOpCode();
160 latency = target.getInstrInfo().hasResultInterlock(mopCode)
161 ? target.getInstrInfo().minLatency(mopCode)
162 : target.getInstrInfo().maxLatency(mopCode);
168 SchedGraphNode::~SchedGraphNode()
170 // for each node, delete its out-edges
171 std::for_each(beginOutEdges(), endOutEdges(),
172 deleter<SchedGraphEdge>);
175 void SchedGraphNode::dump(int indent=0) const {
176 cerr << std::string(indent*2, ' ') << *this;
181 SchedGraphNode::addInEdge(SchedGraphEdge* edge)
183 inEdges.push_back(edge);
188 SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
190 outEdges.push_back(edge);
194 SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
196 assert(edge->getSink() == this);
198 for (iterator I = beginInEdges(); I != endInEdges(); ++I)
207 SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
209 assert(edge->getSrc() == this);
211 for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
226 SchedGraph::SchedGraph(const BasicBlock* bb,
227 const TargetMachine& target)
235 SchedGraph::~SchedGraph()
237 for (const_iterator I = begin(); I != end(); ++I)
245 SchedGraph::dump() const
247 cerr << " Sched Graph for Basic Blocks: ";
248 for (unsigned i=0, N=bbVec.size(); i < N; i++)
250 cerr << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
251 << " (" << bbVec[i] << ")"
252 << ((i == N-1)? "" : ", ");
255 cerr << "\n\n Actual Root nodes : ";
256 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
257 cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
258 << ((i == N-1)? "" : ", ");
260 cerr << "\n Graph Nodes:\n";
261 for (const_iterator I=begin(); I != end(); ++I)
262 cerr << "\n" << *I->second;
269 SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
271 // Delete and disconnect all in-edges for the node
272 for (SchedGraphNode::iterator I = node->beginInEdges();
273 I != node->endInEdges(); ++I)
275 SchedGraphNode* srcNode = (*I)->getSrc();
276 srcNode->removeOutEdge(*I);
280 srcNode != getRoot() &&
281 srcNode->beginOutEdges() == srcNode->endOutEdges())
282 { // srcNode has no more out edges, so add an edge to dummy EXIT node
283 assert(node != getLeaf() && "Adding edge that was just removed?");
284 (void) new SchedGraphEdge(srcNode, getLeaf(),
285 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
289 node->inEdges.clear();
293 SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
295 // Delete and disconnect all out-edges for the node
296 for (SchedGraphNode::iterator I = node->beginOutEdges();
297 I != node->endOutEdges(); ++I)
299 SchedGraphNode* sinkNode = (*I)->getSink();
300 sinkNode->removeInEdge(*I);
304 sinkNode != getLeaf() &&
305 sinkNode->beginInEdges() == sinkNode->endInEdges())
306 { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
307 assert(node != getRoot() && "Adding edge that was just removed?");
308 (void) new SchedGraphEdge(getRoot(), sinkNode,
309 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
313 node->outEdges.clear();
317 SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
319 this->eraseIncomingEdges(node, addDummyEdges);
320 this->eraseOutgoingEdges(node, addDummyEdges);
325 SchedGraph::addDummyEdges()
327 assert(graphRoot->outEdges.size() == 0);
329 for (const_iterator I=begin(); I != end(); ++I)
331 SchedGraphNode* node = (*I).second;
332 assert(node != graphRoot && node != graphLeaf);
333 if (node->beginInEdges() == node->endInEdges())
334 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
335 SchedGraphEdge::NonDataDep, 0);
336 if (node->beginOutEdges() == node->endOutEdges())
337 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
338 SchedGraphEdge::NonDataDep, 0);
344 SchedGraph::addCDEdges(const TerminatorInst* term,
345 const TargetMachine& target)
347 const MachineInstrInfo& mii = target.getInstrInfo();
348 MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
350 // Find the first branch instr in the sequence of machine instrs for term
353 while (!mii.isBranch(termMvec[first]->getOpCode()))
355 assert(first < termMvec.size() &&
356 "No branch instructions for BR? Ok, but weird! Delete assertion.");
357 if (first == termMvec.size())
360 SchedGraphNode* firstBrNode = this->getGraphNodeForInstr(termMvec[first]);
362 // Add CD edges from each instruction in the sequence to the
363 // *last preceding* branch instr. in the sequence
364 // Use a latency of 0 because we only need to prevent out-of-order issue.
366 for (int i = (int) termMvec.size()-1; i > (int) first; i--)
368 SchedGraphNode* toNode = this->getGraphNodeForInstr(termMvec[i]);
369 assert(toNode && "No node for instr generated for branch?");
371 for (int j = i-1; j >= 0; j--)
372 if (mii.isBranch(termMvec[j]->getOpCode()))
374 SchedGraphNode* brNode = this->getGraphNodeForInstr(termMvec[j]);
375 assert(brNode && "No node for instr generated for branch?");
376 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
377 SchedGraphEdge::NonDataDep, 0);
378 break; // only one incoming edge is enough
382 // Add CD edges from each instruction preceding the first branch
383 // to the first branch. Use a latency of 0 as above.
385 for (int i = first-1; i >= 0; i--)
387 SchedGraphNode* fromNode = this->getGraphNodeForInstr(termMvec[i]);
388 assert(fromNode && "No node for instr generated for branch?");
389 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
390 SchedGraphEdge::NonDataDep, 0);
393 // Now add CD edges to the first branch instruction in the sequence from
394 // all preceding instructions in the basic block. Use 0 latency again.
396 const BasicBlock* bb = firstBrNode->getBB();
397 const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb);
398 for (unsigned i=0, N=mvec.size(); i < N; i++)
400 if (mvec[i] == termMvec[first]) // reached the first branch
403 SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
404 if (fromNode == NULL)
405 continue; // dummy instruction, e.g., PHI
407 (void) new SchedGraphEdge(fromNode, firstBrNode,
408 SchedGraphEdge::CtrlDep,
409 SchedGraphEdge::NonDataDep, 0);
411 // If we find any other machine instructions (other than due to
412 // the terminator) that also have delay slots, add an outgoing edge
413 // from the instruction to the instructions in the delay slots.
415 unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
416 assert(i+d < N && "Insufficient delay slots for instruction?");
418 for (unsigned j=1; j <= d; j++)
420 SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
421 assert(toNode && "No node for machine instr in delay slot?");
422 (void) new SchedGraphEdge(fromNode, toNode,
423 SchedGraphEdge::CtrlDep,
424 SchedGraphEdge::NonDataDep, 0);
429 static const int SG_LOAD_REF = 0;
430 static const int SG_STORE_REF = 1;
431 static const int SG_CALL_REF = 2;
433 static const unsigned int SG_DepOrderArray[][3] = {
434 { SchedGraphEdge::NonDataDep,
435 SchedGraphEdge::AntiDep,
436 SchedGraphEdge::AntiDep },
437 { SchedGraphEdge::TrueDep,
438 SchedGraphEdge::OutputDep,
439 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
440 { SchedGraphEdge::TrueDep,
441 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
442 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
443 | SchedGraphEdge::OutputDep }
447 // Add a dependence edge between every pair of machine load/store/call
448 // instructions, where at least one is a store or a call.
449 // Use latency 1 just to ensure that memory operations are ordered;
450 // latency does not otherwise matter (true dependences enforce that).
453 SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
454 const TargetMachine& target)
456 const MachineInstrInfo& mii = target.getInstrInfo();
458 // Instructions in memNodeVec are in execution order within the basic block,
459 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
461 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
463 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
464 int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
465 : mii.isLoad(fromOpCode)? SG_LOAD_REF
467 for (unsigned jm=im+1; jm < NM; jm++)
469 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
470 int toType = mii.isCall(toOpCode)? SG_CALL_REF
471 : mii.isLoad(toOpCode)? SG_LOAD_REF
474 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
475 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
476 SchedGraphEdge::MemoryDep,
477 SG_DepOrderArray[fromType][toType], 1);
482 // Add edges from/to CC reg instrs to/from call instrs.
483 // Essentially this prevents anything that sets or uses a CC reg from being
484 // reordered w.r.t. a call.
485 // Use a latency of 0 because we only need to prevent out-of-order issue,
486 // like with control dependences.
489 SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
490 MachineCodeForBasicBlock& bbMvec,
491 const TargetMachine& target)
493 const MachineInstrInfo& mii = target.getInstrInfo();
494 vector<SchedGraphNode*> callNodeVec;
496 // Find the call instruction nodes and put them in a vector.
497 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
498 if (mii.isCall(memNodeVec[im]->getOpCode()))
499 callNodeVec.push_back(memNodeVec[im]);
501 // Now walk the entire basic block, looking for CC instructions *and*
502 // call instructions, and keep track of the order of the instructions.
503 // Use the call node vec to quickly find earlier and later call nodes
504 // relative to the current CC instruction.
506 int lastCallNodeIdx = -1;
507 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
508 if (mii.isCall(bbMvec[i]->getOpCode()))
511 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
512 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
514 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
516 else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
517 { // Add incoming/outgoing edges from/to preceding/later calls
518 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
520 for ( ; j <= lastCallNodeIdx; j++)
521 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
522 MachineCCRegsRID, 0);
523 for ( ; j < (int) callNodeVec.size(); j++)
524 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
525 MachineCCRegsRID, 0);
531 SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
532 const TargetMachine& target)
534 assert(bbVec.size() == 1 && "Only handling a single basic block here");
536 // This assumes that such hardwired registers are never allocated
537 // to any LLVM value (since register allocation happens later), i.e.,
538 // any uses or defs of this register have been made explicit!
539 // Also assumes that two registers with different numbers are
542 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
543 I != regToRefVecMap.end(); ++I)
545 int regNum = (*I).first;
546 RefVec& regRefVec = (*I).second;
548 // regRefVec is ordered by control flow order in the basic block
549 for (unsigned i=0; i < regRefVec.size(); ++i)
551 SchedGraphNode* node = regRefVec[i].first;
552 unsigned int opNum = regRefVec[i].second;
553 bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
555 node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
557 for (unsigned p=0; p < i; ++p)
559 SchedGraphNode* prevNode = regRefVec[p].first;
560 if (prevNode != node)
562 unsigned int prevOpNum = regRefVec[p].second;
564 prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
565 bool prevIsDefAndUse =
566 prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
570 new SchedGraphEdge(prevNode, node, regNum,
571 SchedGraphEdge::OutputDep);
572 if (!prevIsDef || prevIsDefAndUse)
573 new SchedGraphEdge(prevNode, node, regNum,
574 SchedGraphEdge::AntiDep);
578 if (!isDef || isDefAndUse)
579 new SchedGraphEdge(prevNode, node, regNum,
580 SchedGraphEdge::TrueDep);
588 // Adds dependences to/from refNode from/to all other defs
589 // in the basic block. refNode may be a use, a def, or both.
590 // We do not consider other uses because we are not building use-use deps.
593 SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
594 const RefVec& defVec,
595 const Value* defValue,
597 bool refNodeIsDefAndUse,
598 const TargetMachine& target)
600 bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
602 // Add true or output dep edges from all def nodes before refNode in BB.
603 // Add anti or output dep edges to all def nodes after refNode.
604 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
606 if ((*I).first == refNode)
607 continue; // Dont add any self-loops
609 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
610 { // (*).first is before refNode
612 (void) new SchedGraphEdge((*I).first, refNode, defValue,
613 SchedGraphEdge::OutputDep);
615 (void) new SchedGraphEdge((*I).first, refNode, defValue,
616 SchedGraphEdge::TrueDep);
619 { // (*).first is after refNode
621 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
622 SchedGraphEdge::OutputDep);
624 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
625 SchedGraphEdge::AntiDep);
632 SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
633 const ValueToDefVecMap& valueToDefVecMap,
634 const TargetMachine& target)
636 SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
640 // Add edges for all operands of the machine instruction.
642 for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
644 const MachineOperand& mop = minstr.getOperand(i);
645 switch(mop.getOperandType())
647 case MachineOperand::MO_VirtualRegister:
648 case MachineOperand::MO_CCRegister:
649 if (const Instruction* srcI =
650 dyn_cast_or_null<Instruction>(mop.getVRegValue()))
652 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
653 if (I != valueToDefVecMap.end())
654 addEdgesForValue(node, (*I).second, mop.getVRegValue(),
655 minstr.operandIsDefined(i),
656 minstr.operandIsDefinedAndUsed(i), target);
660 case MachineOperand::MO_MachineRegister:
663 case MachineOperand::MO_SignExtendedImmed:
664 case MachineOperand::MO_UnextendedImmed:
665 case MachineOperand::MO_PCRelativeDisp:
666 break; // nothing to do for immediate fields
669 assert(0 && "Unknown machine operand type in SchedGraph builder");
674 // Add edges for values implicitly used by the machine instruction.
675 // Examples include function arguments to a Call instructions or the return
676 // value of a Ret instruction.
678 for (unsigned i=0, N=minstr.getNumImplicitRefs(); i < N; ++i)
679 if (! minstr.implicitRefIsDefined(i) ||
680 minstr.implicitRefIsDefinedAndUsed(i))
681 if (const Instruction* srcI =
682 dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
684 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
685 if (I != valueToDefVecMap.end())
686 addEdgesForValue(node, (*I).second, minstr.getImplicitRef(i),
687 minstr.implicitRefIsDefined(i),
688 minstr.implicitRefIsDefinedAndUsed(i), target);
694 SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
695 SchedGraphNode* node,
696 vector<SchedGraphNode*>& memNodeVec,
697 RegToRefVecMap& regToRefVecMap,
698 ValueToDefVecMap& valueToDefVecMap)
700 const MachineInstrInfo& mii = target.getInstrInfo();
703 MachineOpCode opCode = node->getOpCode();
704 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
705 memNodeVec.push_back(node);
707 // Collect the register references and value defs. for explicit operands
709 const MachineInstr& minstr = * node->getMachineInstr();
710 for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
712 const MachineOperand& mop = minstr.getOperand(i);
714 // if this references a register other than the hardwired
715 // "zero" register, record the reference.
716 if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
718 int regNum = mop.getMachineRegNum();
719 if (regNum != target.getRegInfo().getZeroRegNum())
720 regToRefVecMap[mop.getMachineRegNum()].push_back(
721 std::make_pair(node, i));
722 continue; // nothing more to do
725 // ignore all other non-def operands
726 if (! minstr.operandIsDefined(i))
729 // We must be defining a value.
730 assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
731 mop.getOperandType() == MachineOperand::MO_CCRegister)
732 && "Do not expect any other kind of operand to be defined!");
734 const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
735 valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
739 // Collect value defs. for implicit operands. The interface to extract
740 // them assumes they must be virtual registers!
742 for (int i=0, N = (int) minstr.getNumImplicitRefs(); i < N; ++i)
743 if (minstr.implicitRefIsDefined(i))
744 if (const Instruction* defInstr =
745 dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
747 valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
753 SchedGraph::buildNodesforBB(const TargetMachine& target,
754 const BasicBlock* bb,
755 vector<SchedGraphNode*>& memNodeVec,
756 RegToRefVecMap& regToRefVecMap,
757 ValueToDefVecMap& valueToDefVecMap)
759 const MachineInstrInfo& mii = target.getInstrInfo();
761 // Build graph nodes for each VM instruction and gather def/use info.
762 // Do both those together in a single pass over all machine instructions.
763 const MachineCodeForBasicBlock& mvec = MachineCodeForBasicBlock::get(bb);
764 for (unsigned i=0; i < mvec.size(); i++)
765 if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
767 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
769 this->noteGraphNodeForInstr(mvec[i], node);
771 // Remember all register references and value defs
772 findDefUseInfoAtInstr(target, node,
773 memNodeVec, regToRefVecMap,valueToDefVecMap);
776 #undef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
777 #ifdef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
778 // This is a BIG UGLY HACK. IT NEEDS TO BE ELIMINATED.
779 // Look for copy instructions inserted in this BB due to Phi instructions
780 // in the successor BBs.
781 // There MUST be exactly one copy per Phi in successor nodes.
783 for (BasicBlock::succ_const_iterator SI=bb->succ_begin(), SE=bb->succ_end();
785 for (BasicBlock::const_iterator PI=(*SI)->begin(), PE=(*SI)->end();
788 if ((*PI)->getOpcode() != Instruction::PHINode)
789 break; // No more Phis in this successor
791 // Find the incoming value from block bb to block (*SI)
792 int bbIndex = cast<PHINode>(*PI)->getBasicBlockIndex(bb);
793 assert(bbIndex >= 0 && "But I know bb is a predecessor of (*SI)?");
794 Value* inVal = cast<PHINode>(*PI)->getIncomingValue(bbIndex);
795 assert(inVal != NULL && "There must be an in-value on every edge");
797 // Find the machine instruction that makes a copy of inval to (*PI).
798 // This must be in the current basic block (bb).
799 const MachineCodeForVMInstr& mvec = MachineCodeForBasicBlock::get(*PI);
800 const MachineInstr* theCopy = NULL;
801 for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
802 if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
803 // not a Phi: assume this is a copy and examine its operands
804 for (int o=0, N=(int) mvec[i]->getNumOperands(); o < N; o++)
806 const MachineOperand& mop = mvec[i]->getOperand(o);
808 if (mvec[i]->operandIsDefined(o))
809 assert(mop.getVRegValue() == (*PI) && "dest shd be my Phi");
811 if (! mvec[i]->operandIsDefined(o) ||
812 NOT NEEDED? mvec[i]->operandIsDefinedAndUsed(o))
813 if (mop.getVRegValue() == inVal)
820 // Found the dang instruction. Now create a node and do the rest...
823 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
824 theCopy, origIndexInBB++, target);
825 this->noteGraphNodeForInstr(theCopy, node);
826 findDefUseInfoAtInstr(target, node,
827 memNodeVec, regToRefVecMap,valueToDefVecMap);
830 #endif //REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
835 SchedGraph::buildGraph(const TargetMachine& target)
837 const BasicBlock* bb = bbVec[0];
839 assert(bbVec.size() == 1 && "Only handling a single basic block here");
841 // Use this data structure to note all machine operands that compute
842 // ordinary LLVM values. These must be computed defs (i.e., instructions).
843 // Note that there may be multiple machine instructions that define
845 ValueToDefVecMap valueToDefVecMap;
847 // Use this data structure to note all memory instructions.
848 // We use this to add memory dependence edges without a second full walk.
850 // vector<const Instruction*> memVec;
851 vector<SchedGraphNode*> memNodeVec;
853 // Use this data structure to note any uses or definitions of
854 // machine registers so we can add edges for those later without
855 // extra passes over the nodes.
856 // The vector holds an ordered list of references to the machine reg,
857 // ordered according to control-flow order. This only works for a
858 // single basic block, hence the assertion. Each reference is identified
859 // by the pair: <node, operand-number>.
861 RegToRefVecMap regToRefVecMap;
863 // Make a dummy root node. We'll add edges to the real roots later.
864 graphRoot = new SchedGraphNode(0, NULL, NULL, -1, target);
865 graphLeaf = new SchedGraphNode(1, NULL, NULL, -1, target);
867 //----------------------------------------------------------------
868 // First add nodes for all the machine instructions in the basic block
869 // because this greatly simplifies identifying which edges to add.
870 // Do this one VM instruction at a time since the SchedGraphNode needs that.
871 // Also, remember the load/store instructions to add memory deps later.
872 //----------------------------------------------------------------
874 buildNodesforBB(target, bb, memNodeVec, regToRefVecMap, valueToDefVecMap);
876 //----------------------------------------------------------------
877 // Now add edges for the following (all are incoming edges except (4)):
878 // (1) operands of the machine instruction, including hidden operands
879 // (2) machine register dependences
880 // (3) memory load/store dependences
881 // (3) other resource dependences for the machine instruction, if any
882 // (4) output dependences when multiple machine instructions define the
883 // same value; all must have been generated from a single VM instrn
884 // (5) control dependences to branch instructions generated for the
885 // terminator instruction of the BB. Because of delay slots and
886 // 2-way conditional branches, multiple CD edges are needed
887 // (see addCDEdges for details).
888 // Also, note any uses or defs of machine registers.
890 //----------------------------------------------------------------
892 MachineCodeForBasicBlock& bbMvec = MachineCodeForBasicBlock::get(bb);
894 // First, add edges to the terminator instruction of the basic block.
895 this->addCDEdges(bb->getTerminator(), target);
897 // Then add memory dep edges: store->load, load->store, and store->store.
898 // Call instructions are treated as both load and store.
899 this->addMemEdges(memNodeVec, target);
901 // Then add edges between call instructions and CC set/use instructions
902 this->addCallCCEdges(memNodeVec, bbMvec, target);
904 // Then add incoming def-use (SSA) edges for each machine instruction.
905 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
906 addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
908 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
909 // Then add non-SSA edges for all VM instructions in the block.
910 // We assume that all machine instructions that define a value are
911 // generated from the VM instruction corresponding to that value.
912 // TODO: This could probably be done much more efficiently.
913 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
914 this->addNonSSAEdgesForValue(*II, target);
915 #endif //NEED_SEPARATE_NONSSA_EDGES_CODE
917 // Then add edges for dependences on machine registers
918 this->addMachineRegEdges(regToRefVecMap, target);
920 // Finally, add edges from the dummy root and to dummy leaf
921 this->addDummyEdges();
926 // class SchedGraphSet
930 SchedGraphSet::SchedGraphSet(const Function* _function,
931 const TargetMachine& target) :
934 buildGraphsForMethod(method, target);
939 SchedGraphSet::~SchedGraphSet()
941 // delete all the graphs
942 for(iterator I = begin(), E = end(); I != E; ++I)
943 delete *I; // destructor is a friend
948 SchedGraphSet::dump() const
950 cerr << "======== Sched graphs for function `" << method->getName()
953 for (const_iterator I=begin(); I != end(); ++I)
956 cerr << "\n====== End graphs for function `" << method->getName()
962 SchedGraphSet::buildGraphsForMethod(const Function *F,
963 const TargetMachine& target)
965 for (Function::const_iterator BI = F->begin(); BI != F->end(); ++BI)
966 addGraph(new SchedGraph(BI, target));
970 std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge)
972 os << "edge [" << edge.src->getNodeId() << "] -> ["
973 << edge.sink->getNodeId() << "] : ";
975 switch(edge.depType) {
976 case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
977 case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
978 case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
979 case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
980 case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
981 default: assert(0); break;
984 os << " : delay = " << edge.minDelay << "\n";
989 std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
991 os << std::string(8, ' ')
992 << "Node " << node.nodeId << " : "
993 << "latency = " << node.latency << "\n" << std::string(12, ' ');
995 if (node.getMachineInstr() == NULL)
996 os << "(Dummy node)\n";
999 os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
1000 os << node.inEdges.size() << " Incoming Edges:\n";
1001 for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
1002 os << std::string(16, ' ') << *node.inEdges[i];
1004 os << std::string(12, ' ') << node.outEdges.size()
1005 << " Outgoing Edges:\n";
1006 for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
1007 os << std::string(16, ' ') << *node.outEdges[i];