1 //===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
3 // Scheduling graph based on SSA graph plus extra dependence edges capturing
4 // dependences due to machine resources (machine registers, CC registers, and
7 //===----------------------------------------------------------------------===//
9 #include "SchedGraph.h"
10 #include "llvm/Function.h"
11 #include "llvm/iOther.h"
12 #include "llvm/CodeGen/MachineCodeForInstruction.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/TargetRegInfo.h"
17 #include "Support/STLExtras.h"
19 //*********************** Internal Data Structures *************************/
21 // The following two types need to be classes, not typedefs, so we can use
22 // opaque declarations in SchedGraph.h
24 struct RefVec: public std::vector<std::pair<SchedGraphNode*, int> > {
25 typedef std::vector<std::pair<SchedGraphNode*,int> >::iterator iterator;
27 std::vector<std::pair<SchedGraphNode*,int> >::const_iterator const_iterator;
30 struct RegToRefVecMap: public hash_map<int, RefVec> {
31 typedef hash_map<int, RefVec>:: iterator iterator;
32 typedef hash_map<int, RefVec>::const_iterator const_iterator;
35 struct ValueToDefVecMap: public hash_map<const Value*, RefVec> {
36 typedef hash_map<const Value*, RefVec>:: iterator iterator;
37 typedef hash_map<const Value*, RefVec>::const_iterator const_iterator;
42 // class SchedGraphNode
45 SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
46 int indexInBB, const TargetMachine& Target)
47 : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
49 MachineOpCode mopCode = MI->getOpCode();
50 latency = Target.getInstrInfo().hasResultInterlock(mopCode)
51 ? Target.getInstrInfo().minLatency(mopCode)
52 : Target.getInstrInfo().maxLatency(mopCode);
57 // Method: SchedGraphNode Destructor
60 // Free memory allocated by the SchedGraphNode object.
63 // Do not delete the edges here. The base class will take care of that.
64 // Only handle subclass specific stuff here (where currently there is
67 SchedGraphNode::~SchedGraphNode() {
73 SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
79 // Method: SchedGraph Destructor
82 // This method deletes memory allocated by the SchedGraph object.
85 // Do not delete the graphRoot or graphLeaf here. The base class handles
88 SchedGraph::~SchedGraph() {
89 for (const_iterator I = begin(); I != end(); ++I)
93 void SchedGraph::dump() const {
94 std::cerr << " Sched Graph for Basic Block: ";
95 std::cerr << MBB.getBasicBlock()->getName()
96 << " (" << MBB.getBasicBlock() << ")";
98 std::cerr << "\n\n Actual Root nodes : ";
99 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
100 std::cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
101 << ((i == N-1)? "" : ", ");
103 std::cerr << "\n Graph Nodes:\n";
104 for (const_iterator I=begin(); I != end(); ++I)
105 std::cerr << "\n" << *I->second;
112 void SchedGraph::addDummyEdges() {
113 assert(graphRoot->outEdges.size() == 0);
115 for (const_iterator I=begin(); I != end(); ++I) {
116 SchedGraphNode* node = (*I).second;
117 assert(node != graphRoot && node != graphLeaf);
118 if (node->beginInEdges() == node->endInEdges())
119 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
120 SchedGraphEdge::NonDataDep, 0);
121 if (node->beginOutEdges() == node->endOutEdges())
122 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
123 SchedGraphEdge::NonDataDep, 0);
128 void SchedGraph::addCDEdges(const TerminatorInst* term,
129 const TargetMachine& target) {
130 const TargetInstrInfo& mii = target.getInstrInfo();
131 MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
133 // Find the first branch instr in the sequence of machine instrs for term
136 while (! mii.isBranch(termMvec[first]->getOpCode()) &&
137 ! mii.isReturn(termMvec[first]->getOpCode()))
139 assert(first < termMvec.size() &&
140 "No branch instructions for terminator? Ok, but weird!");
141 if (first == termMvec.size())
144 SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
146 // Add CD edges from each instruction in the sequence to the
147 // *last preceding* branch instr. in the sequence
148 // Use a latency of 0 because we only need to prevent out-of-order issue.
150 for (unsigned i = termMvec.size(); i > first+1; --i) {
151 SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
152 assert(toNode && "No node for instr generated for branch/ret?");
154 for (unsigned j = i-1; j != 0; --j)
155 if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
156 mii.isReturn(termMvec[j-1]->getOpCode())) {
157 SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
158 assert(brNode && "No node for instr generated for branch/ret?");
159 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
160 SchedGraphEdge::NonDataDep, 0);
161 break; // only one incoming edge is enough
165 // Add CD edges from each instruction preceding the first branch
166 // to the first branch. Use a latency of 0 as above.
168 for (unsigned i = first; i != 0; --i) {
169 SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
170 assert(fromNode && "No node for instr generated for branch?");
171 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
172 SchedGraphEdge::NonDataDep, 0);
175 // Now add CD edges to the first branch instruction in the sequence from
176 // all preceding instructions in the basic block. Use 0 latency again.
178 for (unsigned i=0, N=MBB.size(); i < N; i++) {
179 if (MBB[i] == termMvec[first]) // reached the first branch
182 SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
183 if (fromNode == NULL)
184 continue; // dummy instruction, e.g., PHI
186 (void) new SchedGraphEdge(fromNode, firstBrNode,
187 SchedGraphEdge::CtrlDep,
188 SchedGraphEdge::NonDataDep, 0);
190 // If we find any other machine instructions (other than due to
191 // the terminator) that also have delay slots, add an outgoing edge
192 // from the instruction to the instructions in the delay slots.
194 unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
195 assert(i+d < N && "Insufficient delay slots for instruction?");
197 for (unsigned j=1; j <= d; j++) {
198 SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
199 assert(toNode && "No node for machine instr in delay slot?");
200 (void) new SchedGraphEdge(fromNode, toNode,
201 SchedGraphEdge::CtrlDep,
202 SchedGraphEdge::NonDataDep, 0);
207 static const int SG_LOAD_REF = 0;
208 static const int SG_STORE_REF = 1;
209 static const int SG_CALL_REF = 2;
211 static const unsigned int SG_DepOrderArray[][3] = {
212 { SchedGraphEdge::NonDataDep,
213 SchedGraphEdge::AntiDep,
214 SchedGraphEdge::AntiDep },
215 { SchedGraphEdge::TrueDep,
216 SchedGraphEdge::OutputDep,
217 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
218 { SchedGraphEdge::TrueDep,
219 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
220 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
221 | SchedGraphEdge::OutputDep }
225 // Add a dependence edge between every pair of machine load/store/call
226 // instructions, where at least one is a store or a call.
227 // Use latency 1 just to ensure that memory operations are ordered;
228 // latency does not otherwise matter (true dependences enforce that).
230 void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
231 const TargetMachine& target) {
232 const TargetInstrInfo& mii = target.getInstrInfo();
234 // Instructions in memNodeVec are in execution order within the basic block,
235 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
237 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) {
238 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
239 int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
240 : (mii.isLoad(fromOpCode)? SG_LOAD_REF
242 for (unsigned jm=im+1; jm < NM; jm++) {
243 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
244 int toType = (mii.isCall(toOpCode)? SG_CALL_REF
245 : (mii.isLoad(toOpCode)? SG_LOAD_REF
248 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
249 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
250 SchedGraphEdge::MemoryDep,
251 SG_DepOrderArray[fromType][toType], 1);
256 // Add edges from/to CC reg instrs to/from call instrs.
257 // Essentially this prevents anything that sets or uses a CC reg from being
258 // reordered w.r.t. a call.
259 // Use a latency of 0 because we only need to prevent out-of-order issue,
260 // like with control dependences.
262 void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNodeVec,
263 const TargetMachine& target) {
264 const TargetInstrInfo& mii = target.getInstrInfo();
266 // Instructions in memNodeVec are in execution order within the basic block,
267 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
269 for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
270 if (mii.isCall(callDepNodeVec[ic]->getOpCode())) {
271 // Add SG_CALL_REF edges from all preds to this instruction.
272 for (unsigned jc=0; jc < ic; jc++)
273 (void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
274 SchedGraphEdge::MachineRegister,
275 MachineIntRegsRID, 0);
277 // And do the same from this instruction to all successors.
278 for (unsigned jc=ic+1; jc < NC; jc++)
279 (void) new SchedGraphEdge(callDepNodeVec[ic], callDepNodeVec[jc],
280 SchedGraphEdge::MachineRegister,
281 MachineIntRegsRID, 0);
284 #ifdef CALL_DEP_NODE_VEC_CANNOT_WORK
285 // Find the call instruction nodes and put them in a vector.
286 std::vector<SchedGraphNode*> callNodeVec;
287 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
288 if (mii.isCall(memNodeVec[im]->getOpCode()))
289 callNodeVec.push_back(memNodeVec[im]);
291 // Now walk the entire basic block, looking for CC instructions *and*
292 // call instructions, and keep track of the order of the instructions.
293 // Use the call node vec to quickly find earlier and later call nodes
294 // relative to the current CC instruction.
296 int lastCallNodeIdx = -1;
297 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
298 if (mii.isCall(bbMvec[i]->getOpCode())) {
300 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
301 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
303 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
305 else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
306 // Add incoming/outgoing edges from/to preceding/later calls
307 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
309 for ( ; j <= lastCallNodeIdx; j++)
310 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
311 MachineCCRegsRID, 0);
312 for ( ; j < (int) callNodeVec.size(); j++)
313 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
314 MachineCCRegsRID, 0);
320 void SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
321 const TargetMachine& target) {
322 // This code assumes that two registers with different numbers are
325 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
326 I != regToRefVecMap.end(); ++I) {
327 int regNum = (*I).first;
328 RefVec& regRefVec = (*I).second;
330 // regRefVec is ordered by control flow order in the basic block
331 for (unsigned i=0; i < regRefVec.size(); ++i) {
332 SchedGraphNode* node = regRefVec[i].first;
333 unsigned int opNum = regRefVec[i].second;
334 const MachineOperand& mop =
335 node->getMachineInstr()->getExplOrImplOperand(opNum);
336 bool isDef = mop.opIsDefOnly();
337 bool isDefAndUse = mop.opIsDefAndUse();
339 for (unsigned p=0; p < i; ++p) {
340 SchedGraphNode* prevNode = regRefVec[p].first;
341 if (prevNode != node) {
342 unsigned int prevOpNum = regRefVec[p].second;
343 const MachineOperand& prevMop =
344 prevNode->getMachineInstr()->getExplOrImplOperand(prevOpNum);
345 bool prevIsDef = prevMop.opIsDefOnly();
346 bool prevIsDefAndUse = prevMop.opIsDefAndUse();
349 new SchedGraphEdge(prevNode, node, regNum,
350 SchedGraphEdge::OutputDep);
351 if (!prevIsDef || prevIsDefAndUse)
352 new SchedGraphEdge(prevNode, node, regNum,
353 SchedGraphEdge::AntiDep);
357 if (!isDef || isDefAndUse)
358 new SchedGraphEdge(prevNode, node, regNum,
359 SchedGraphEdge::TrueDep);
367 // Adds dependences to/from refNode from/to all other defs
368 // in the basic block. refNode may be a use, a def, or both.
369 // We do not consider other uses because we are not building use-use deps.
371 void SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
372 const RefVec& defVec,
373 const Value* defValue,
375 bool refNodeIsDefAndUse,
376 const TargetMachine& target) {
377 bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
379 // Add true or output dep edges from all def nodes before refNode in BB.
380 // Add anti or output dep edges to all def nodes after refNode.
381 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I) {
382 if ((*I).first == refNode)
383 continue; // Dont add any self-loops
385 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB()) {
386 // (*).first is before refNode
388 (void) new SchedGraphEdge((*I).first, refNode, defValue,
389 SchedGraphEdge::OutputDep);
391 (void) new SchedGraphEdge((*I).first, refNode, defValue,
392 SchedGraphEdge::TrueDep);
394 // (*).first is after refNode
396 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
397 SchedGraphEdge::OutputDep);
399 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
400 SchedGraphEdge::AntiDep);
406 void SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
407 const ValueToDefVecMap& valueToDefVecMap,
408 const TargetMachine& target) {
409 SchedGraphNode* node = getGraphNodeForInstr(&MI);
413 // Add edges for all operands of the machine instruction.
415 for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i) {
416 switch (MI.getOperand(i).getType()) {
417 case MachineOperand::MO_VirtualRegister:
418 case MachineOperand::MO_CCRegister:
419 if (const Value* srcI = MI.getOperand(i).getVRegValue()) {
420 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
421 if (I != valueToDefVecMap.end())
422 addEdgesForValue(node, I->second, srcI,
423 MI.getOperand(i).opIsDefOnly(),
424 MI.getOperand(i).opIsDefAndUse(), target);
428 case MachineOperand::MO_MachineRegister:
431 case MachineOperand::MO_SignExtendedImmed:
432 case MachineOperand::MO_UnextendedImmed:
433 case MachineOperand::MO_PCRelativeDisp:
434 break; // nothing to do for immediate fields
437 assert(0 && "Unknown machine operand type in SchedGraph builder");
442 // Add edges for values implicitly used by the machine instruction.
443 // Examples include function arguments to a Call instructions or the return
444 // value of a Ret instruction.
446 for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
447 if (MI.getImplicitOp(i).opIsUse() || MI.getImplicitOp(i).opIsDefAndUse())
448 if (const Value* srcI = MI.getImplicitRef(i)) {
449 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
450 if (I != valueToDefVecMap.end())
451 addEdgesForValue(node, I->second, srcI,
452 MI.getImplicitOp(i).opIsDefOnly(),
453 MI.getImplicitOp(i).opIsDefAndUse(), target);
458 void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
459 SchedGraphNode* node,
460 std::vector<SchedGraphNode*>& memNodeVec,
461 std::vector<SchedGraphNode*>& callDepNodeVec,
462 RegToRefVecMap& regToRefVecMap,
463 ValueToDefVecMap& valueToDefVecMap) {
464 const TargetInstrInfo& mii = target.getInstrInfo();
466 MachineOpCode opCode = node->getOpCode();
468 if (mii.isCall(opCode) || mii.isCCInstr(opCode))
469 callDepNodeVec.push_back(node);
471 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
472 memNodeVec.push_back(node);
474 // Collect the register references and value defs. for explicit operands
476 const MachineInstr& MI = *node->getMachineInstr();
477 for (int i=0, numOps = (int) MI.getNumOperands(); i < numOps; i++) {
478 const MachineOperand& mop = MI.getOperand(i);
480 // if this references a register other than the hardwired
481 // "zero" register, record the reference.
482 if (mop.hasAllocatedReg()) {
483 int regNum = mop.getAllocatedRegNum();
485 // If this is not a dummy zero register, record the reference in order
486 if (regNum != target.getRegInfo().getZeroRegNum())
487 regToRefVecMap[mop.getAllocatedRegNum()]
488 .push_back(std::make_pair(node, i));
490 // If this is a volatile register, add the instruction to callDepVec
491 // (only if the node is not already on the callDepVec!)
492 if (callDepNodeVec.size() == 0 || callDepNodeVec.back() != node)
495 int regInClass = target.getRegInfo().getClassRegNum(regNum, rcid);
496 if (target.getRegInfo().getMachineRegClass(rcid)
497 ->isRegVolatile(regInClass))
498 callDepNodeVec.push_back(node);
501 continue; // nothing more to do
504 // ignore all other non-def operands
505 if (!MI.getOperand(i).opIsDefOnly() &&
506 !MI.getOperand(i).opIsDefAndUse())
509 // We must be defining a value.
510 assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
511 mop.getType() == MachineOperand::MO_CCRegister)
512 && "Do not expect any other kind of operand to be defined!");
513 assert(mop.getVRegValue() != NULL && "Null value being defined?");
515 valueToDefVecMap[mop.getVRegValue()].push_back(std::make_pair(node, i));
519 // Collect value defs. for implicit operands. They may have allocated
520 // physical registers also.
522 for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
523 const MachineOperand& mop = MI.getImplicitOp(i);
524 if (mop.hasAllocatedReg()) {
525 int regNum = mop.getAllocatedRegNum();
526 if (regNum != target.getRegInfo().getZeroRegNum())
527 regToRefVecMap[mop.getAllocatedRegNum()]
528 .push_back(std::make_pair(node, i + MI.getNumOperands()));
529 continue; // nothing more to do
532 if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
533 assert(MI.getImplicitRef(i) != NULL && "Null value being defined?");
534 valueToDefVecMap[MI.getImplicitRef(i)].push_back(std::make_pair(node,
541 void SchedGraph::buildNodesForBB(const TargetMachine& target,
542 MachineBasicBlock& MBB,
543 std::vector<SchedGraphNode*>& memNodeVec,
544 std::vector<SchedGraphNode*>& callDepNodeVec,
545 RegToRefVecMap& regToRefVecMap,
546 ValueToDefVecMap& valueToDefVecMap) {
547 const TargetInstrInfo& mii = target.getInstrInfo();
549 // Build graph nodes for each VM instruction and gather def/use info.
550 // Do both those together in a single pass over all machine instructions.
551 for (unsigned i=0; i < MBB.size(); i++)
552 if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
553 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
554 noteGraphNodeForInstr(MBB[i], node);
556 // Remember all register references and value defs
557 findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
558 regToRefVecMap, valueToDefVecMap);
563 void SchedGraph::buildGraph(const TargetMachine& target) {
564 // Use this data structure to note all machine operands that compute
565 // ordinary LLVM values. These must be computed defs (i.e., instructions).
566 // Note that there may be multiple machine instructions that define
568 ValueToDefVecMap valueToDefVecMap;
570 // Use this data structure to note all memory instructions.
571 // We use this to add memory dependence edges without a second full walk.
572 std::vector<SchedGraphNode*> memNodeVec;
574 // Use this data structure to note all instructions that access physical
575 // registers that can be modified by a call (including call instructions)
576 std::vector<SchedGraphNode*> callDepNodeVec;
578 // Use this data structure to note any uses or definitions of
579 // machine registers so we can add edges for those later without
580 // extra passes over the nodes.
581 // The vector holds an ordered list of references to the machine reg,
582 // ordered according to control-flow order. This only works for a
583 // single basic block, hence the assertion. Each reference is identified
584 // by the pair: <node, operand-number>.
586 RegToRefVecMap regToRefVecMap;
588 // Make a dummy root node. We'll add edges to the real roots later.
589 graphRoot = new SchedGraphNode(0, NULL, -1, target);
590 graphLeaf = new SchedGraphNode(1, NULL, -1, target);
592 //----------------------------------------------------------------
593 // First add nodes for all the machine instructions in the basic block
594 // because this greatly simplifies identifying which edges to add.
595 // Do this one VM instruction at a time since the SchedGraphNode needs that.
596 // Also, remember the load/store instructions to add memory deps later.
597 //----------------------------------------------------------------
599 buildNodesForBB(target, MBB, memNodeVec, callDepNodeVec,
600 regToRefVecMap, valueToDefVecMap);
602 //----------------------------------------------------------------
603 // Now add edges for the following (all are incoming edges except (4)):
604 // (1) operands of the machine instruction, including hidden operands
605 // (2) machine register dependences
606 // (3) memory load/store dependences
607 // (3) other resource dependences for the machine instruction, if any
608 // (4) output dependences when multiple machine instructions define the
609 // same value; all must have been generated from a single VM instrn
610 // (5) control dependences to branch instructions generated for the
611 // terminator instruction of the BB. Because of delay slots and
612 // 2-way conditional branches, multiple CD edges are needed
613 // (see addCDEdges for details).
614 // Also, note any uses or defs of machine registers.
616 //----------------------------------------------------------------
618 // First, add edges to the terminator instruction of the basic block.
619 this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
621 // Then add memory dep edges: store->load, load->store, and store->store.
622 // Call instructions are treated as both load and store.
623 this->addMemEdges(memNodeVec, target);
625 // Then add edges between call instructions and CC set/use instructions
626 this->addCallDepEdges(callDepNodeVec, target);
628 // Then add incoming def-use (SSA) edges for each machine instruction.
629 for (unsigned i=0, N=MBB.size(); i < N; i++)
630 addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
632 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
633 // Then add non-SSA edges for all VM instructions in the block.
634 // We assume that all machine instructions that define a value are
635 // generated from the VM instruction corresponding to that value.
636 // TODO: This could probably be done much more efficiently.
637 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
638 this->addNonSSAEdgesForValue(*II, target);
639 #endif //NEED_SEPARATE_NONSSA_EDGES_CODE
641 // Then add edges for dependences on machine registers
642 this->addMachineRegEdges(regToRefVecMap, target);
644 // Finally, add edges from the dummy root and to dummy leaf
645 this->addDummyEdges();
650 // class SchedGraphSet
652 SchedGraphSet::SchedGraphSet(const Function* _function,
653 const TargetMachine& target) :
654 function(_function) {
655 buildGraphsForMethod(function, target);
658 SchedGraphSet::~SchedGraphSet() {
659 // delete all the graphs
660 for(iterator I = begin(), E = end(); I != E; ++I)
661 delete *I; // destructor is a friend
665 void SchedGraphSet::dump() const {
666 std::cerr << "======== Sched graphs for function `" << function->getName()
669 for (const_iterator I=begin(); I != end(); ++I)
672 std::cerr << "\n====== End graphs for function `" << function->getName()
677 void SchedGraphSet::buildGraphsForMethod(const Function *F,
678 const TargetMachine& target) {
679 MachineFunction &MF = MachineFunction::get(F);
680 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
681 addGraph(new SchedGraph(*I, target));
685 void SchedGraphEdge::print(std::ostream &os) const {
686 os << "edge [" << src->getNodeId() << "] -> ["
687 << sink->getNodeId() << "] : ";
690 case SchedGraphEdge::CtrlDep:
693 case SchedGraphEdge::ValueDep:
694 os<< "Reg Value " << val;
696 case SchedGraphEdge::MemoryDep:
699 case SchedGraphEdge::MachineRegister:
700 os<< "Reg " << machineRegNum;
702 case SchedGraphEdge::MachineResource:
703 os<<"Resource "<< resourceId;
710 os << " : delay = " << minDelay << "\n";
713 void SchedGraphNode::print(std::ostream &os) const {
714 os << std::string(8, ' ')
715 << "Node " << ID << " : "
716 << "latency = " << latency << "\n" << std::string(12, ' ');
718 if (getMachineInstr() == NULL)
719 os << "(Dummy node)\n";
721 os << *getMachineInstr() << "\n" << std::string(12, ' ');
722 os << inEdges.size() << " Incoming Edges:\n";
723 for (unsigned i=0, N = inEdges.size(); i < N; i++)
724 os << std::string(16, ' ') << *inEdges[i];
726 os << std::string(12, ' ') << outEdges.size()
727 << " Outgoing Edges:\n";
728 for (unsigned i=0, N= outEdges.size(); i < N; i++)
729 os << std::string(16, ' ') << *outEdges[i];