2 //***************************************************************************
7 // Scheduling graph based on SSA graph plus extra dependence edges
8 // capturing dependences due to machine resources (machine registers,
9 // CC registers, and any others).
12 // 7/20/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #include "SchedGraph.h"
16 #include "llvm/InstrTypes.h"
17 #include "llvm/Instruction.h"
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Method.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/InstrSelection.h"
22 #include "llvm/Target/MachineInstrInfo.h"
23 #include "llvm/Target/MachineRegInfo.h"
24 #include "llvm/Support/StringExtras.h"
25 #include "llvm/iOther.h"
31 //*********************** Internal Data Structures *************************/
33 // The following two types need to be classes, not typedefs, so we can use
34 // opaque declarations in SchedGraph.h
36 struct RefVec: public vector< pair<SchedGraphNode*, int> > {
37 typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
38 typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
41 struct RegToRefVecMap: public hash_map<int, RefVec> {
42 typedef hash_map<int, RefVec>:: iterator iterator;
43 typedef hash_map<int, RefVec>::const_iterator const_iterator;
46 struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
47 typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
48 typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
52 // class SchedGraphEdge
56 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
57 SchedGraphNode* _sink,
58 SchedGraphEdgeDepType _depType,
59 unsigned int _depOrderType,
64 depOrderType(_depOrderType),
65 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
68 assert(src != sink && "Self-loop in scheduling graph!");
69 src->addOutEdge(this);
70 sink->addInEdge(this);
75 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
76 SchedGraphNode* _sink,
78 unsigned int _depOrderType,
83 depOrderType(_depOrderType),
84 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
87 assert(src != sink && "Self-loop in scheduling graph!");
88 src->addOutEdge(this);
89 sink->addInEdge(this);
94 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
95 SchedGraphNode* _sink,
97 unsigned int _depOrderType,
101 depType(MachineRegister),
102 depOrderType(_depOrderType),
103 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
104 machineRegNum(_regNum)
106 assert(src != sink && "Self-loop in scheduling graph!");
107 src->addOutEdge(this);
108 sink->addInEdge(this);
113 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
114 SchedGraphNode* _sink,
115 ResourceId _resourceId,
119 depType(MachineResource),
120 depOrderType(NonDataDep),
121 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
122 resourceId(_resourceId)
124 assert(src != sink && "Self-loop in scheduling graph!");
125 src->addOutEdge(this);
126 sink->addInEdge(this);
130 SchedGraphEdge::~SchedGraphEdge()
134 void SchedGraphEdge::dump(int indent=0) const {
135 printIndent(indent); cout << *this;
140 // class SchedGraphNode
144 SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
145 const BasicBlock* _bb,
146 const MachineInstr* _minstr,
148 const TargetMachine& target)
152 origIndexInBB(indexInBB),
157 MachineOpCode mopCode = minstr->getOpCode();
158 latency = target.getInstrInfo().hasResultInterlock(mopCode)
159 ? target.getInstrInfo().minLatency(mopCode)
160 : target.getInstrInfo().maxLatency(mopCode);
166 SchedGraphNode::~SchedGraphNode()
170 void SchedGraphNode::dump(int indent=0) const {
171 printIndent(indent); cout << *this;
176 SchedGraphNode::addInEdge(SchedGraphEdge* edge)
178 inEdges.push_back(edge);
183 SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
185 outEdges.push_back(edge);
189 SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
191 assert(edge->getSink() == this);
193 for (iterator I = beginInEdges(); I != endInEdges(); ++I)
202 SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
204 assert(edge->getSrc() == this);
206 for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
221 SchedGraph::SchedGraph(const BasicBlock* bb,
222 const TargetMachine& target)
225 this->buildGraph(target);
230 SchedGraph::~SchedGraph()
232 for (iterator I=begin(); I != end(); ++I)
234 SchedGraphNode* node = (*I).second;
236 // for each node, delete its out-edges
237 for (SchedGraphNode::iterator I = node->beginOutEdges();
238 I != node->endOutEdges(); ++I)
241 // then delete the node itself.
248 SchedGraph::dump() const
250 cout << " Sched Graph for Basic Blocks: ";
251 for (unsigned i=0, N=bbVec.size(); i < N; i++)
253 cout << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
254 << " (" << bbVec[i] << ")"
255 << ((i == N-1)? "" : ", ");
258 cout << endl << endl << " Actual Root nodes : ";
259 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
260 cout << graphRoot->outEdges[i]->getSink()->getNodeId()
261 << ((i == N-1)? "" : ", ");
263 cout << endl << " Graph Nodes:" << endl;
264 for (const_iterator I=begin(); I != end(); ++I)
265 cout << endl << * (*I).second;
272 SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
274 // Delete and disconnect all in-edges for the node
275 for (SchedGraphNode::iterator I = node->beginInEdges();
276 I != node->endInEdges(); ++I)
278 SchedGraphNode* srcNode = (*I)->getSrc();
279 srcNode->removeOutEdge(*I);
283 srcNode != getRoot() &&
284 srcNode->beginOutEdges() == srcNode->endOutEdges())
285 { // srcNode has no more out edges, so add an edge to dummy EXIT node
286 assert(node != getLeaf() && "Adding edge that was just removed?");
287 (void) new SchedGraphEdge(srcNode, getLeaf(),
288 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
292 node->inEdges.clear();
296 SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
298 // Delete and disconnect all out-edges for the node
299 for (SchedGraphNode::iterator I = node->beginOutEdges();
300 I != node->endOutEdges(); ++I)
302 SchedGraphNode* sinkNode = (*I)->getSink();
303 sinkNode->removeInEdge(*I);
307 sinkNode != getLeaf() &&
308 sinkNode->beginInEdges() == sinkNode->endInEdges())
309 { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
310 assert(node != getRoot() && "Adding edge that was just removed?");
311 (void) new SchedGraphEdge(getRoot(), sinkNode,
312 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
316 node->outEdges.clear();
320 SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
322 this->eraseIncomingEdges(node, addDummyEdges);
323 this->eraseOutgoingEdges(node, addDummyEdges);
328 SchedGraph::addDummyEdges()
330 assert(graphRoot->outEdges.size() == 0);
332 for (const_iterator I=begin(); I != end(); ++I)
334 SchedGraphNode* node = (*I).second;
335 assert(node != graphRoot && node != graphLeaf);
336 if (node->beginInEdges() == node->endInEdges())
337 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
338 SchedGraphEdge::NonDataDep, 0);
339 if (node->beginOutEdges() == node->endOutEdges())
340 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
341 SchedGraphEdge::NonDataDep, 0);
347 SchedGraph::addCDEdges(const TerminatorInst* term,
348 const TargetMachine& target)
350 const MachineInstrInfo& mii = target.getInstrInfo();
351 MachineCodeForVMInstr& termMvec = term->getMachineInstrVec();
353 // Find the first branch instr in the sequence of machine instrs for term
356 while (! mii.isBranch(termMvec[first]->getOpCode()))
358 assert(first < termMvec.size() &&
359 "No branch instructions for BR? Ok, but weird! Delete assertion.");
360 if (first == termMvec.size())
363 SchedGraphNode* firstBrNode = this->getGraphNodeForInstr(termMvec[first]);
365 // Add CD edges from each instruction in the sequence to the
366 // *last preceding* branch instr. in the sequence
367 // Use a latency of 0 because we only need to prevent out-of-order issue.
369 for (int i = (int) termMvec.size()-1; i > (int) first; i--)
371 SchedGraphNode* toNode = this->getGraphNodeForInstr(termMvec[i]);
372 assert(toNode && "No node for instr generated for branch?");
374 for (int j = i-1; j >= 0; j--)
375 if (mii.isBranch(termMvec[j]->getOpCode()))
377 SchedGraphNode* brNode = this->getGraphNodeForInstr(termMvec[j]);
378 assert(brNode && "No node for instr generated for branch?");
379 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
380 SchedGraphEdge::NonDataDep, 0);
381 break; // only one incoming edge is enough
385 // Add CD edges from each instruction preceding the first branch
386 // to the first branch. Use a latency of 0 as above.
388 for (int i = first-1; i >= 0; i--)
390 SchedGraphNode* fromNode = this->getGraphNodeForInstr(termMvec[i]);
391 assert(fromNode && "No node for instr generated for branch?");
392 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
393 SchedGraphEdge::NonDataDep, 0);
396 // Now add CD edges to the first branch instruction in the sequence from
397 // all preceding instructions in the basic block. Use 0 latency again.
399 const BasicBlock* bb = firstBrNode->getBB();
400 const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
401 for (unsigned i=0, N=mvec.size(); i < N; i++)
403 if (mvec[i] == termMvec[first]) // reached the first branch
406 SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
407 if (fromNode == NULL)
408 continue; // dummy instruction, e.g., PHI
410 (void) new SchedGraphEdge(fromNode, firstBrNode,
411 SchedGraphEdge::CtrlDep,
412 SchedGraphEdge::NonDataDep, 0);
414 // If we find any other machine instructions (other than due to
415 // the terminator) that also have delay slots, add an outgoing edge
416 // from the instruction to the instructions in the delay slots.
418 unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
419 assert(i+d < N && "Insufficient delay slots for instruction?");
421 for (unsigned j=1; j <= d; j++)
423 SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
424 assert(toNode && "No node for machine instr in delay slot?");
425 (void) new SchedGraphEdge(fromNode, toNode,
426 SchedGraphEdge::CtrlDep,
427 SchedGraphEdge::NonDataDep, 0);
432 static const int SG_LOAD_REF = 0;
433 static const int SG_STORE_REF = 1;
434 static const int SG_CALL_REF = 2;
436 static const unsigned int SG_DepOrderArray[][3] = {
437 { SchedGraphEdge::NonDataDep,
438 SchedGraphEdge::AntiDep,
439 SchedGraphEdge::AntiDep },
440 { SchedGraphEdge::TrueDep,
441 SchedGraphEdge::OutputDep,
442 SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
443 { SchedGraphEdge::TrueDep,
444 SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
445 SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
446 | SchedGraphEdge::OutputDep }
450 // Add a dependence edge between every pair of machine load/store/call
451 // instructions, where at least one is a store or a call.
452 // Use latency 1 just to ensure that memory operations are ordered;
453 // latency does not otherwise matter (true dependences enforce that).
456 SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
457 const TargetMachine& target)
459 const MachineInstrInfo& mii = target.getInstrInfo();
461 // Instructions in memNodeVec are in execution order within the basic block,
462 // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
464 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
466 MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
467 int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
468 : mii.isLoad(fromOpCode)? SG_LOAD_REF
470 for (unsigned jm=im+1; jm < NM; jm++)
472 MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
473 int toType = mii.isCall(toOpCode)? SG_CALL_REF
474 : mii.isLoad(toOpCode)? SG_LOAD_REF
477 if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
478 (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
479 SchedGraphEdge::MemoryDep,
480 SG_DepOrderArray[fromType][toType], 1);
485 // Add edges from/to CC reg instrs to/from call instrs.
486 // Essentially this prevents anything that sets or uses a CC reg from being
487 // reordered w.r.t. a call.
488 // Use a latency of 0 because we only need to prevent out-of-order issue,
489 // like with control dependences.
492 SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
493 MachineCodeForBasicBlock& bbMvec,
494 const TargetMachine& target)
496 const MachineInstrInfo& mii = target.getInstrInfo();
497 vector<SchedGraphNode*> callNodeVec;
499 // Find the call instruction nodes and put them in a vector.
500 for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
501 if (mii.isCall(memNodeVec[im]->getOpCode()))
502 callNodeVec.push_back(memNodeVec[im]);
504 // Now walk the entire basic block, looking for CC instructions *and*
505 // call instructions, and keep track of the order of the instructions.
506 // Use the call node vec to quickly find earlier and later call nodes
507 // relative to the current CC instruction.
509 int lastCallNodeIdx = -1;
510 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
511 if (mii.isCall(bbMvec[i]->getOpCode()))
514 for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
515 if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
517 assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
519 else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
520 { // Add incoming/outgoing edges from/to preceding/later calls
521 SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
523 for ( ; j <= lastCallNodeIdx; j++)
524 (void) new SchedGraphEdge(callNodeVec[j], ccNode,
525 MachineCCRegsRID, 0);
526 for ( ; j < (int) callNodeVec.size(); j++)
527 (void) new SchedGraphEdge(ccNode, callNodeVec[j],
528 MachineCCRegsRID, 0);
534 SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
535 const TargetMachine& target)
537 assert(bbVec.size() == 1 && "Only handling a single basic block here");
539 // This assumes that such hardwired registers are never allocated
540 // to any LLVM value (since register allocation happens later), i.e.,
541 // any uses or defs of this register have been made explicit!
542 // Also assumes that two registers with different numbers are
545 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
546 I != regToRefVecMap.end(); ++I)
548 int regNum = (*I).first;
549 RefVec& regRefVec = (*I).second;
551 // regRefVec is ordered by control flow order in the basic block
552 for (unsigned i=0; i < regRefVec.size(); ++i)
554 SchedGraphNode* node = regRefVec[i].first;
555 unsigned int opNum = regRefVec[i].second;
556 bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
558 for (unsigned p=0; p < i; ++p)
560 SchedGraphNode* prevNode = regRefVec[p].first;
561 if (prevNode != node)
563 unsigned int prevOpNum = regRefVec[p].second;
565 prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
568 new SchedGraphEdge(prevNode, node, regNum,
569 (prevIsDef)? SchedGraphEdge::OutputDep
570 : SchedGraphEdge::AntiDep);
572 new SchedGraphEdge(prevNode, node, regNum,
573 SchedGraphEdge::TrueDep);
582 SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
583 const RefVec& defVec,
584 const Value* defValue,
586 const TargetMachine& target)
588 // Add true or output dep edges from all def nodes before refNode in BB.
589 // Add anti or output dep edges to all def nodes after refNode.
590 for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
592 if ((*I).first == refNode)
593 continue; // Dont add any self-loops
595 if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
596 // (*).first is before refNode
597 (void) new SchedGraphEdge((*I).first, refNode, defValue,
598 (refNodeIsDef)? SchedGraphEdge::OutputDep
599 : SchedGraphEdge::TrueDep);
601 // (*).first is after refNode
602 (void) new SchedGraphEdge(refNode, (*I).first, defValue,
603 (refNodeIsDef)? SchedGraphEdge::OutputDep
604 : SchedGraphEdge::AntiDep);
610 SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
611 const ValueToDefVecMap& valueToDefVecMap,
612 const TargetMachine& target)
614 SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
618 // Add edges for all operands of the machine instruction.
620 for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
622 const MachineOperand& mop = minstr.getOperand(i);
623 switch(mop.getOperandType())
625 case MachineOperand::MO_VirtualRegister:
626 case MachineOperand::MO_CCRegister:
627 if (const Instruction* srcI =
628 dyn_cast_or_null<Instruction>(mop.getVRegValue()))
630 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
631 if (I != valueToDefVecMap.end())
632 addEdgesForValue(node, (*I).second, mop.getVRegValue(),
633 minstr.operandIsDefined(i), target);
637 case MachineOperand::MO_MachineRegister:
640 case MachineOperand::MO_SignExtendedImmed:
641 case MachineOperand::MO_UnextendedImmed:
642 case MachineOperand::MO_PCRelativeDisp:
643 break; // nothing to do for immediate fields
646 assert(0 && "Unknown machine operand type in SchedGraph builder");
651 // Add edges for values implicitly used by the machine instruction.
652 // Examples include function arguments to a Call instructions or the return
653 // value of a Ret instruction.
655 for (unsigned i=0, N=minstr.getNumImplicitRefs(); i < N; ++i)
656 if (! minstr.implicitRefIsDefined(i))
657 if (const Instruction* srcI =
658 dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
660 ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
661 if (I != valueToDefVecMap.end())
662 addEdgesForValue(node, (*I).second, minstr.getImplicitRef(i),
663 minstr.implicitRefIsDefined(i), target);
668 #undef NEED_SEPARATE_NONSSA_EDGES_CODE
669 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
671 SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
672 const TargetMachine& target)
674 if (isa<PHINode>(instr))
677 MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
678 const MachineInstrInfo& mii = target.getInstrInfo();
681 for (unsigned i=0, N=mvec.size(); i < N; i++)
682 for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
684 const MachineOperand& mop = mvec[i]->getOperand(o);
686 if ((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
687 mop.getOperandType() == MachineOperand::MO_CCRegister)
688 && mop.getVRegValue() == (Value*) instr)
690 // this operand is a definition or use of value `instr'
691 SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
692 assert(node && "No node for machine instruction in this BB?");
693 refVec.push_back(make_pair(node, o));
697 // refVec is ordered by control flow order of the machine instructions
698 for (unsigned i=0; i < refVec.size(); ++i)
700 SchedGraphNode* node = refVec[i].first;
701 unsigned int opNum = refVec[i].second;
702 bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
705 // add output and/or anti deps to this definition
706 for (unsigned p=0; p < i; ++p)
708 SchedGraphNode* prevNode = refVec[p].first;
709 if (prevNode != node)
711 bool prevIsDef = prevNode->getMachineInstr()->
712 operandIsDefined(refVec[p].second);
713 new SchedGraphEdge(prevNode, node, SchedGraphEdge::ValueDep,
714 (prevIsDef)? SchedGraphEdge::OutputDep
715 : SchedGraphEdge::AntiDep);
720 #endif NEED_SEPARATE_NONSSA_EDGES_CODE
724 SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
725 SchedGraphNode* node,
726 vector<SchedGraphNode*>& memNodeVec,
727 RegToRefVecMap& regToRefVecMap,
728 ValueToDefVecMap& valueToDefVecMap)
730 const MachineInstrInfo& mii = target.getInstrInfo();
733 MachineOpCode opCode = node->getOpCode();
734 if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
735 memNodeVec.push_back(node);
737 // Collect the register references and value defs. for explicit operands
739 const MachineInstr& minstr = * node->getMachineInstr();
740 for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
742 const MachineOperand& mop = minstr.getOperand(i);
744 // if this references a register other than the hardwired
745 // "zero" register, record the reference.
746 if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
748 int regNum = mop.getMachineRegNum();
749 if (regNum != target.getRegInfo().getZeroRegNum())
750 regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node,
752 continue; // nothing more to do
755 // ignore all other non-def operands
756 if (! minstr.operandIsDefined(i))
759 // We must be defining a value.
760 assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
761 mop.getOperandType() == MachineOperand::MO_CCRegister)
762 && "Do not expect any other kind of operand to be defined!");
764 const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
765 valueToDefVecMap[defInstr].push_back(make_pair(node, i));
769 // Collect value defs. for implicit operands. The interface to extract
770 // them assumes they must be virtual registers!
772 for (int i=0, N = (int) minstr.getNumImplicitRefs(); i < N; ++i)
773 if (minstr.implicitRefIsDefined(i))
774 if (const Instruction* defInstr =
775 dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
777 valueToDefVecMap[defInstr].push_back(make_pair(node, -i));
783 SchedGraph::buildNodesforBB(const TargetMachine& target,
784 const BasicBlock* bb,
785 vector<SchedGraphNode*>& memNodeVec,
786 RegToRefVecMap& regToRefVecMap,
787 ValueToDefVecMap& valueToDefVecMap)
789 const MachineInstrInfo& mii = target.getInstrInfo();
791 // Build graph nodes for each VM instruction and gather def/use info.
792 // Do both those together in a single pass over all machine instructions.
793 const MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
794 for (unsigned i=0; i < mvec.size(); i++)
795 if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
797 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
799 this->noteGraphNodeForInstr(mvec[i], node);
801 // Remember all register references and value defs
802 findDefUseInfoAtInstr(target, node,
803 memNodeVec, regToRefVecMap,valueToDefVecMap);
806 #undef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
807 #ifdef REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
808 // This is a BIG UGLY HACK. IT NEEDS TO BE ELIMINATED.
809 // Look for copy instructions inserted in this BB due to Phi instructions
810 // in the successor BBs.
811 // There MUST be exactly one copy per Phi in successor nodes.
813 for (BasicBlock::succ_const_iterator SI=bb->succ_begin(), SE=bb->succ_end();
815 for (BasicBlock::const_iterator PI=(*SI)->begin(), PE=(*SI)->end();
818 if ((*PI)->getOpcode() != Instruction::PHINode)
819 break; // No more Phis in this successor
821 // Find the incoming value from block bb to block (*SI)
822 int bbIndex = cast<PHINode>(*PI)->getBasicBlockIndex(bb);
823 assert(bbIndex >= 0 && "But I know bb is a predecessor of (*SI)?");
824 Value* inVal = cast<PHINode>(*PI)->getIncomingValue(bbIndex);
825 assert(inVal != NULL && "There must be an in-value on every edge");
827 // Find the machine instruction that makes a copy of inval to (*PI).
828 // This must be in the current basic block (bb).
829 const MachineCodeForVMInstr& mvec = (*PI)->getMachineInstrVec();
830 const MachineInstr* theCopy = NULL;
831 for (unsigned i=0; i < mvec.size() && theCopy == NULL; i++)
832 if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
833 // not a Phi: assume this is a copy and examine its operands
834 for (int o=0, N=(int) mvec[i]->getNumOperands(); o < N; o++)
836 const MachineOperand& mop = mvec[i]->getOperand(o);
837 if (mvec[i]->operandIsDefined(o))
838 assert(mop.getVRegValue() == (*PI) && "dest shd be my Phi");
839 else if (mop.getVRegValue() == inVal)
846 // Found the dang instruction. Now create a node and do the rest...
849 SchedGraphNode* node = new SchedGraphNode(getNumNodes(), bb,
850 theCopy, origIndexInBB++, target);
851 this->noteGraphNodeForInstr(theCopy, node);
852 findDefUseInfoAtInstr(target, node,
853 memNodeVec, regToRefVecMap,valueToDefVecMap);
856 #endif REALLY_NEED_TO_SEARCH_SUCCESSOR_PHIS
861 SchedGraph::buildGraph(const TargetMachine& target)
863 const MachineInstrInfo& mii = target.getInstrInfo();
864 const BasicBlock* bb = bbVec[0];
866 assert(bbVec.size() == 1 && "Only handling a single basic block here");
868 // Use this data structure to note all machine operands that compute
869 // ordinary LLVM values. These must be computed defs (i.e., instructions).
870 // Note that there may be multiple machine instructions that define
872 ValueToDefVecMap valueToDefVecMap;
874 // Use this data structure to note all memory instructions.
875 // We use this to add memory dependence edges without a second full walk.
877 // vector<const Instruction*> memVec;
878 vector<SchedGraphNode*> memNodeVec;
880 // Use this data structure to note any uses or definitions of
881 // machine registers so we can add edges for those later without
882 // extra passes over the nodes.
883 // The vector holds an ordered list of references to the machine reg,
884 // ordered according to control-flow order. This only works for a
885 // single basic block, hence the assertion. Each reference is identified
886 // by the pair: <node, operand-number>.
888 RegToRefVecMap regToRefVecMap;
890 // Make a dummy root node. We'll add edges to the real roots later.
891 graphRoot = new SchedGraphNode(0, NULL, NULL, -1, target);
892 graphLeaf = new SchedGraphNode(1, NULL, NULL, -1, target);
894 //----------------------------------------------------------------
895 // First add nodes for all the machine instructions in the basic block
896 // because this greatly simplifies identifying which edges to add.
897 // Do this one VM instruction at a time since the SchedGraphNode needs that.
898 // Also, remember the load/store instructions to add memory deps later.
899 //----------------------------------------------------------------
901 buildNodesforBB(target, bb, memNodeVec, regToRefVecMap, valueToDefVecMap);
903 //----------------------------------------------------------------
904 // Now add edges for the following (all are incoming edges except (4)):
905 // (1) operands of the machine instruction, including hidden operands
906 // (2) machine register dependences
907 // (3) memory load/store dependences
908 // (3) other resource dependences for the machine instruction, if any
909 // (4) output dependences when multiple machine instructions define the
910 // same value; all must have been generated from a single VM instrn
911 // (5) control dependences to branch instructions generated for the
912 // terminator instruction of the BB. Because of delay slots and
913 // 2-way conditional branches, multiple CD edges are needed
914 // (see addCDEdges for details).
915 // Also, note any uses or defs of machine registers.
917 //----------------------------------------------------------------
919 MachineCodeForBasicBlock& bbMvec = bb->getMachineInstrVec();
921 // First, add edges to the terminator instruction of the basic block.
922 this->addCDEdges(bb->getTerminator(), target);
924 // Then add memory dep edges: store->load, load->store, and store->store.
925 // Call instructions are treated as both load and store.
926 this->addMemEdges(memNodeVec, target);
928 // Then add edges between call instructions and CC set/use instructions
929 this->addCallCCEdges(memNodeVec, bbMvec, target);
931 // Then add incoming def-use (SSA) edges for each machine instruction.
932 for (unsigned i=0, N=bbMvec.size(); i < N; i++)
933 addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
935 #ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
936 // Then add non-SSA edges for all VM instructions in the block.
937 // We assume that all machine instructions that define a value are
938 // generated from the VM instruction corresponding to that value.
939 // TODO: This could probably be done much more efficiently.
940 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
941 this->addNonSSAEdgesForValue(*II, target);
942 #endif NEED_SEPARATE_NONSSA_EDGES_CODE
944 // Then add edges for dependences on machine registers
945 this->addMachineRegEdges(regToRefVecMap, target);
947 // Finally, add edges from the dummy root and to dummy leaf
948 this->addDummyEdges();
953 // class SchedGraphSet
957 SchedGraphSet::SchedGraphSet(const Method* _method,
958 const TargetMachine& target) :
961 buildGraphsForMethod(method, target);
966 SchedGraphSet::~SchedGraphSet()
968 // delete all the graphs
969 for (iterator I=begin(); I != end(); ++I)
975 SchedGraphSet::dump() const
977 cout << "======== Sched graphs for method `"
978 << (method->hasName()? method->getName() : "???")
979 << "' ========" << endl << endl;
981 for (const_iterator I=begin(); I != end(); ++I)
984 cout << endl << "====== End graphs for method `"
985 << (method->hasName()? method->getName() : "")
986 << "' ========" << endl << endl;
991 SchedGraphSet::buildGraphsForMethod(const Method *method,
992 const TargetMachine& target)
994 for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI)
996 SchedGraph* graph = new SchedGraph(*BI, target);
997 this->noteGraphForBlock(*BI, graph);
1004 operator<<(ostream& os, const SchedGraphEdge& edge)
1006 os << "edge [" << edge.src->getNodeId() << "] -> ["
1007 << edge.sink->getNodeId() << "] : ";
1009 switch(edge.depType) {
1010 case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
1011 case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
1012 case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
1013 case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
1014 case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
1015 default: assert(0); break;
1018 os << " : delay = " << edge.minDelay << endl;
1024 operator<<(ostream& os, const SchedGraphNode& node)
1027 os << "Node " << node.nodeId << " : "
1028 << "latency = " << node.latency << endl;
1032 if (node.getMachineInstr() == NULL)
1033 os << "(Dummy node)" << endl;
1036 os << *node.getMachineInstr() << endl;
1039 os << node.inEdges.size() << " Incoming Edges:" << endl;
1040 for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
1043 os << * node.inEdges[i];
1047 os << node.outEdges.size() << " Outgoing Edges:" << endl;
1048 for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
1051 os << * node.outEdges[i];