1 //===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the execution dependency fix pass.
12 // Some X86 SSE instructions like mov, and, or, xor are available in different
13 // variants for different operand types. These variant instructions are
14 // equivalent, but on Nehalem and newer cpus there is extra latency
15 // transferring data between integer and floating point domains. ARM cores
16 // have similar issues when they are configured with both VFP and NEON
19 // This pass changes the variant instructions to minimize domain crossings.
21 //===----------------------------------------------------------------------===//
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/ADT/PostOrderIterator.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/CodeGen/LivePhysRegs.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/Support/Allocator.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Target/TargetInstrInfo.h"
33 #include "llvm/Target/TargetSubtargetInfo.h"
37 #define DEBUG_TYPE "execution-fix"
39 /// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
40 /// of execution domains.
42 /// An open DomainValue represents a set of instructions that can still switch
43 /// execution domain. Multiple registers may refer to the same open
44 /// DomainValue - they will eventually be collapsed to the same execution
47 /// A collapsed DomainValue represents a single register that has been forced
48 /// into one of more execution domains. There is a separate collapsed
49 /// DomainValue for each register, but it may contain multiple execution
50 /// domains. A register value is initially created in a single execution
51 /// domain, but if we were forced to pay the penalty of a domain crossing, we
52 /// keep track of the fact that the register is now available in multiple
56 // Basic reference counting.
59 // Bitmask of available domains. For an open DomainValue, it is the still
60 // possible domains for collapsing. For a collapsed DomainValue it is the
61 // domains where the register is available for free.
62 unsigned AvailableDomains;
64 // Pointer to the next DomainValue in a chain. When two DomainValues are
65 // merged, Victim.Next is set to point to Victor, so old DomainValue
66 // references can be updated by following the chain.
69 // Twiddleable instructions using or defining these registers.
70 SmallVector<MachineInstr*, 8> Instrs;
72 // A collapsed DomainValue has no instructions to twiddle - it simply keeps
73 // track of the domains where the registers are already available.
74 bool isCollapsed() const { return Instrs.empty(); }
76 // Is domain available?
77 bool hasDomain(unsigned domain) const {
79 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
80 "undefined behavior");
81 return AvailableDomains & (1u << domain);
84 // Mark domain as available.
85 void addDomain(unsigned domain) {
86 AvailableDomains |= 1u << domain;
89 // Restrict to a single domain available.
90 void setSingleDomain(unsigned domain) {
91 AvailableDomains = 1u << domain;
94 // Return bitmask of domains that are available and in mask.
95 unsigned getCommonDomains(unsigned mask) const {
96 return AvailableDomains & mask;
99 // First domain available.
100 unsigned getFirstDomain() const {
101 return countTrailingZeros(AvailableDomains);
104 DomainValue() : Refs(0) { clear(); }
106 // Clear this DomainValue and point to next which has all its data.
108 AvailableDomains = 0;
116 /// Information about a live register.
118 /// Value currently in this register, or NULL when no value is being tracked.
119 /// This counts as a DomainValue reference.
122 /// Instruction that defined this register, relative to the beginning of the
123 /// current basic block. When a LiveReg is used to represent a live-out
124 /// register, this value is relative to the end of the basic block, so it
125 /// will be a negative number.
128 } // anonymous namespace
131 class ExeDepsFix : public MachineFunctionPass {
133 SpecificBumpPtrAllocator<DomainValue> Allocator;
134 SmallVector<DomainValue*,16> Avail;
136 const TargetRegisterClass *const RC;
138 const TargetInstrInfo *TII;
139 const TargetRegisterInfo *TRI;
140 std::vector<SmallVector<int, 1>> AliasMap;
141 const unsigned NumRegs;
143 typedef DenseMap<MachineBasicBlock*, LiveReg*> LiveOutMap;
146 /// List of undefined register reads in this block in forward order.
147 std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
149 /// Storage for register unit liveness.
150 LivePhysRegs LiveRegSet;
152 /// Current instruction number.
153 /// The first instruction in each basic block is 0.
156 /// True when the current block has a predecessor that hasn't been visited
158 bool SeenUnknownBackEdge;
161 ExeDepsFix(const TargetRegisterClass *rc)
162 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
164 void getAnalysisUsage(AnalysisUsage &AU) const override {
165 AU.setPreservesAll();
166 MachineFunctionPass::getAnalysisUsage(AU);
169 bool runOnMachineFunction(MachineFunction &MF) override;
171 const char *getPassName() const override {
172 return "Execution dependency fix";
176 iterator_range<SmallVectorImpl<int>::const_iterator>
177 regIndices(unsigned Reg) const;
179 // DomainValue allocation.
180 DomainValue *alloc(int domain = -1);
181 DomainValue *retain(DomainValue *DV) {
185 void release(DomainValue*);
186 DomainValue *resolve(DomainValue*&);
188 // LiveRegs manipulations.
189 void setLiveReg(int rx, DomainValue *DV);
191 void force(int rx, unsigned domain);
192 void collapse(DomainValue *dv, unsigned domain);
193 bool merge(DomainValue *A, DomainValue *B);
195 void enterBasicBlock(MachineBasicBlock*);
196 void leaveBasicBlock(MachineBasicBlock*);
197 void visitInstr(MachineInstr*);
198 void processDefs(MachineInstr*, bool Kill);
199 void visitSoftInstr(MachineInstr*, unsigned mask);
200 void visitHardInstr(MachineInstr*, unsigned domain);
201 bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
202 void processUndefReads(MachineBasicBlock*);
206 char ExeDepsFix::ID = 0;
208 /// Translate TRI register number to a list of indices into our smaller tables
209 /// of interesting registers.
210 iterator_range<SmallVectorImpl<int>::const_iterator>
211 ExeDepsFix::regIndices(unsigned Reg) const {
212 assert(Reg < AliasMap.size() && "Invalid register");
213 const auto &Entry = AliasMap[Reg];
214 return make_range(Entry.begin(), Entry.end());
217 DomainValue *ExeDepsFix::alloc(int domain) {
218 DomainValue *dv = Avail.empty() ?
219 new(Allocator.Allocate()) DomainValue :
220 Avail.pop_back_val();
222 dv->addDomain(domain);
223 assert(dv->Refs == 0 && "Reference count wasn't cleared");
224 assert(!dv->Next && "Chained DomainValue shouldn't have been recycled");
228 /// Release a reference to DV. When the last reference is released,
229 /// collapse if needed.
230 void ExeDepsFix::release(DomainValue *DV) {
232 assert(DV->Refs && "Bad DomainValue");
236 // There are no more DV references. Collapse any contained instructions.
237 if (DV->AvailableDomains && !DV->isCollapsed())
238 collapse(DV, DV->getFirstDomain());
240 DomainValue *Next = DV->Next;
243 // Also release the next DomainValue in the chain.
248 /// Follow the chain of dead DomainValues until a live DomainValue is reached.
249 /// Update the referenced pointer when necessary.
250 DomainValue *ExeDepsFix::resolve(DomainValue *&DVRef) {
251 DomainValue *DV = DVRef;
252 if (!DV || !DV->Next)
255 // DV has a chain. Find the end.
259 // Update DVRef to point to DV.
266 /// Set LiveRegs[rx] = dv, updating reference counts.
267 void ExeDepsFix::setLiveReg(int rx, DomainValue *dv) {
268 assert(unsigned(rx) < NumRegs && "Invalid index");
269 assert(LiveRegs && "Must enter basic block first.");
271 if (LiveRegs[rx].Value == dv)
273 if (LiveRegs[rx].Value)
274 release(LiveRegs[rx].Value);
275 LiveRegs[rx].Value = retain(dv);
278 // Kill register rx, recycle or collapse any DomainValue.
279 void ExeDepsFix::kill(int rx) {
280 assert(unsigned(rx) < NumRegs && "Invalid index");
281 assert(LiveRegs && "Must enter basic block first.");
282 if (!LiveRegs[rx].Value)
285 release(LiveRegs[rx].Value);
286 LiveRegs[rx].Value = nullptr;
289 /// Force register rx into domain.
290 void ExeDepsFix::force(int rx, unsigned domain) {
291 assert(unsigned(rx) < NumRegs && "Invalid index");
292 assert(LiveRegs && "Must enter basic block first.");
293 if (DomainValue *dv = LiveRegs[rx].Value) {
294 if (dv->isCollapsed())
295 dv->addDomain(domain);
296 else if (dv->hasDomain(domain))
297 collapse(dv, domain);
299 // This is an incompatible open DomainValue. Collapse it to whatever and
300 // force the new value into domain. This costs a domain crossing.
301 collapse(dv, dv->getFirstDomain());
302 assert(LiveRegs[rx].Value && "Not live after collapse?");
303 LiveRegs[rx].Value->addDomain(domain);
306 // Set up basic collapsed DomainValue.
307 setLiveReg(rx, alloc(domain));
311 /// Collapse open DomainValue into given domain. If there are multiple
312 /// registers using dv, they each get a unique collapsed DomainValue.
313 void ExeDepsFix::collapse(DomainValue *dv, unsigned domain) {
314 assert(dv->hasDomain(domain) && "Cannot collapse");
316 // Collapse all the instructions.
317 while (!dv->Instrs.empty())
318 TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain);
319 dv->setSingleDomain(domain);
321 // If there are multiple users, give them new, unique DomainValues.
322 if (LiveRegs && dv->Refs > 1)
323 for (unsigned rx = 0; rx != NumRegs; ++rx)
324 if (LiveRegs[rx].Value == dv)
325 setLiveReg(rx, alloc(domain));
328 /// All instructions and registers in B are moved to A, and B is released.
329 bool ExeDepsFix::merge(DomainValue *A, DomainValue *B) {
330 assert(!A->isCollapsed() && "Cannot merge into collapsed");
331 assert(!B->isCollapsed() && "Cannot merge from collapsed");
334 // Restrict to the domains that A and B have in common.
335 unsigned common = A->getCommonDomains(B->AvailableDomains);
338 A->AvailableDomains = common;
339 A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
341 // Clear the old DomainValue so we won't try to swizzle instructions twice.
343 // All uses of B are referred to A.
346 for (unsigned rx = 0; rx != NumRegs; ++rx) {
347 assert(LiveRegs && "no space allocated for live registers");
348 if (LiveRegs[rx].Value == B)
354 /// Set up LiveRegs by merging predecessor live-out values.
355 void ExeDepsFix::enterBasicBlock(MachineBasicBlock *MBB) {
356 // Detect back-edges from predecessors we haven't processed yet.
357 SeenUnknownBackEdge = false;
359 // Reset instruction counter in each basic block.
362 // Set up UndefReads to track undefined register reads.
366 // Set up LiveRegs to represent registers entering MBB.
368 LiveRegs = new LiveReg[NumRegs];
370 // Default values are 'nothing happened a long time ago'.
371 for (unsigned rx = 0; rx != NumRegs; ++rx) {
372 LiveRegs[rx].Value = nullptr;
373 LiveRegs[rx].Def = -(1 << 20);
376 // This is the entry block.
377 if (MBB->pred_empty()) {
378 for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
379 e = MBB->livein_end(); i != e; ++i) {
380 for (int rx : regIndices(*i)) {
381 // Treat function live-ins as if they were defined just before the first
382 // instruction. Usually, function arguments are set up immediately
384 LiveRegs[rx].Def = -1;
387 DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
391 // Try to coalesce live-out registers from predecessors.
392 for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
393 pe = MBB->pred_end(); pi != pe; ++pi) {
394 LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
395 if (fi == LiveOuts.end()) {
396 SeenUnknownBackEdge = true;
399 assert(fi->second && "Can't have NULL entries");
401 for (unsigned rx = 0; rx != NumRegs; ++rx) {
402 // Use the most recent predecessor def for each register.
403 LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, fi->second[rx].Def);
405 DomainValue *pdv = resolve(fi->second[rx].Value);
408 if (!LiveRegs[rx].Value) {
413 // We have a live DomainValue from more than one predecessor.
414 if (LiveRegs[rx].Value->isCollapsed()) {
415 // We are already collapsed, but predecessor is not. Force it.
416 unsigned Domain = LiveRegs[rx].Value->getFirstDomain();
417 if (!pdv->isCollapsed() && pdv->hasDomain(Domain))
418 collapse(pdv, Domain);
422 // Currently open, merge in predecessor.
423 if (!pdv->isCollapsed())
424 merge(LiveRegs[rx].Value, pdv);
426 force(rx, pdv->getFirstDomain());
429 DEBUG(dbgs() << "BB#" << MBB->getNumber()
430 << (SeenUnknownBackEdge ? ": incomplete\n" : ": all preds known\n"));
433 void ExeDepsFix::leaveBasicBlock(MachineBasicBlock *MBB) {
434 assert(LiveRegs && "Must enter basic block first.");
435 // Save live registers at end of MBB - used by enterBasicBlock().
436 // Also use LiveOuts as a visited set to detect back-edges.
437 bool First = LiveOuts.insert(std::make_pair(MBB, LiveRegs)).second;
440 // LiveRegs was inserted in LiveOuts. Adjust all defs to be relative to
441 // the end of this block instead of the beginning.
442 for (unsigned i = 0, e = NumRegs; i != e; ++i)
443 LiveRegs[i].Def -= CurInstr;
445 // Insertion failed, this must be the second pass.
446 // Release all the DomainValues instead of keeping them.
447 for (unsigned i = 0, e = NumRegs; i != e; ++i)
448 release(LiveRegs[i].Value);
454 void ExeDepsFix::visitInstr(MachineInstr *MI) {
455 if (MI->isDebugValue())
458 // Update instructions with explicit execution domains.
459 std::pair<uint16_t, uint16_t> DomP = TII->getExecutionDomain(MI);
462 visitSoftInstr(MI, DomP.second);
464 visitHardInstr(MI, DomP.first);
467 // Process defs to track register ages, and kill values clobbered by generic
469 processDefs(MI, !DomP.first);
472 /// \brief Return true to if it makes sense to break dependence on a partial def
474 bool ExeDepsFix::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
476 unsigned reg = MI->getOperand(OpIdx).getReg();
477 for (int rx : regIndices(reg)) {
478 unsigned Clearance = CurInstr - LiveRegs[rx].Def;
479 DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
481 if (Pref > Clearance) {
482 DEBUG(dbgs() << ": Break dependency.\n");
485 // The current clearance seems OK, but we may be ignoring a def from a
487 if (!SeenUnknownBackEdge || Pref <= unsigned(CurInstr)) {
488 DEBUG(dbgs() << ": OK .\n");
491 // A def from an unprocessed back-edge may make us break this dependency.
492 DEBUG(dbgs() << ": Wait for back-edge to resolve.\n");
498 // Update def-ages for registers defined by MI.
499 // If Kill is set, also kill off DomainValues clobbered by the defs.
501 // Also break dependencies on partial defs and undef uses.
502 void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
503 assert(!MI->isDebugValue() && "Won't process debug values");
505 // Break dependence on undef uses. Do this before updating LiveRegs below.
507 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
509 if (shouldBreakDependence(MI, OpNum, Pref))
510 UndefReads.push_back(std::make_pair(MI, OpNum));
512 const MCInstrDesc &MCID = MI->getDesc();
514 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
516 MachineOperand &MO = MI->getOperand(i);
523 for (int rx : regIndices(MO.getReg())) {
524 // This instruction explicitly defines rx.
525 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
528 // Check clearance before partial register updates.
529 // Call breakDependence before setting LiveRegs[rx].Def.
530 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
531 if (Pref && shouldBreakDependence(MI, i, Pref))
532 TII->breakPartialRegDependency(MI, i, TRI);
534 // How many instructions since rx was last written?
535 LiveRegs[rx].Def = CurInstr;
537 // Kill off domains redefined by generic instructions.
545 /// \break Break false dependencies on undefined register reads.
547 /// Walk the block backward computing precise liveness. This is expensive, so we
548 /// only do it on demand. Note that the occurrence of undefined register reads
549 /// that should be broken is very rare, but when they occur we may have many in
551 void ExeDepsFix::processUndefReads(MachineBasicBlock *MBB) {
552 if (UndefReads.empty())
555 // Collect this block's live out register units.
556 LiveRegSet.init(TRI);
557 LiveRegSet.addLiveOuts(MBB);
559 MachineInstr *UndefMI = UndefReads.back().first;
560 unsigned OpIdx = UndefReads.back().second;
562 for (MachineInstr &I : make_range(MBB->rbegin(), MBB->rend())) {
563 // Update liveness, including the current instruction's defs.
564 LiveRegSet.stepBackward(I);
567 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
568 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
570 UndefReads.pop_back();
571 if (UndefReads.empty())
574 UndefMI = UndefReads.back().first;
575 OpIdx = UndefReads.back().second;
580 // A hard instruction only works in one domain. All input registers will be
581 // forced into that domain.
582 void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
583 // Collapse all uses.
584 for (unsigned i = mi->getDesc().getNumDefs(),
585 e = mi->getDesc().getNumOperands(); i != e; ++i) {
586 MachineOperand &mo = mi->getOperand(i);
587 if (!mo.isReg()) continue;
588 for (int rx : regIndices(mo.getReg())) {
593 // Kill all defs and force them.
594 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
595 MachineOperand &mo = mi->getOperand(i);
596 if (!mo.isReg()) continue;
597 for (int rx : regIndices(mo.getReg())) {
604 // A soft instruction can be changed to work in other domains given by mask.
605 void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
606 // Bitmask of available domains for this instruction after taking collapsed
607 // operands into account.
608 unsigned available = mask;
610 // Scan the explicit use operands for incoming domains.
611 SmallVector<int, 4> used;
613 for (unsigned i = mi->getDesc().getNumDefs(),
614 e = mi->getDesc().getNumOperands(); i != e; ++i) {
615 MachineOperand &mo = mi->getOperand(i);
616 if (!mo.isReg()) continue;
617 for (int rx : regIndices(mo.getReg())) {
618 DomainValue *dv = LiveRegs[rx].Value;
621 // Bitmask of domains that dv and available have in common.
622 unsigned common = dv->getCommonDomains(available);
623 // Is it possible to use this collapsed register for free?
624 if (dv->isCollapsed()) {
625 // Restrict available domains to the ones in common with the operand.
626 // If there are no common domains, we must pay the cross-domain
627 // penalty for this operand.
628 if (common) available = common;
630 // Open DomainValue is compatible, save it for merging.
633 // Open DomainValue is not compatible with instruction. It is useless
639 // If the collapsed operands force a single domain, propagate the collapse.
640 if (isPowerOf2_32(available)) {
641 unsigned domain = countTrailingZeros(available);
642 TII->setExecutionDomain(mi, domain);
643 visitHardInstr(mi, domain);
647 // Kill off any remaining uses that don't match available, and build a list of
648 // incoming DomainValues that we want to merge.
649 SmallVector<LiveReg, 4> Regs;
650 for (SmallVectorImpl<int>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
652 assert(LiveRegs && "no space allocated for live registers");
653 const LiveReg &LR = LiveRegs[rx];
654 // This useless DomainValue could have been missed above.
655 if (!LR.Value->getCommonDomains(available)) {
660 bool Inserted = false;
661 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end();
662 i != e && !Inserted; ++i) {
663 if (LR.Def < i->Def) {
672 // doms are now sorted in order of appearance. Try to merge them all, giving
673 // priority to the latest ones.
674 DomainValue *dv = nullptr;
675 while (!Regs.empty()) {
677 dv = Regs.pop_back_val().Value;
678 // Force the first dv to match the current instruction.
679 dv->AvailableDomains = dv->getCommonDomains(available);
680 assert(dv->AvailableDomains && "Domain should have been filtered");
684 DomainValue *Latest = Regs.pop_back_val().Value;
685 // Skip already merged values.
686 if (Latest == dv || Latest->Next)
688 if (merge(dv, Latest))
691 // If latest didn't merge, it is useless now. Kill all registers using it.
693 assert(LiveRegs && "no space allocated for live registers");
694 if (LiveRegs[i].Value == Latest)
699 // dv is the DomainValue we are going to use for this instruction.
702 dv->AvailableDomains = available;
704 dv->Instrs.push_back(mi);
706 // Finally set all defs and non-collapsed uses to dv. We must iterate through
707 // all the operators, including imp-def ones.
708 for (MachineInstr::mop_iterator ii = mi->operands_begin(),
709 ee = mi->operands_end();
711 MachineOperand &mo = *ii;
712 if (!mo.isReg()) continue;
713 for (int rx : regIndices(mo.getReg())) {
714 if (!LiveRegs[rx].Value || (mo.isDef() && LiveRegs[rx].Value != dv)) {
722 bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
724 TII = MF->getSubtarget().getInstrInfo();
725 TRI = MF->getSubtarget().getRegisterInfo();
727 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
729 DEBUG(dbgs() << "********** FIX EXECUTION DEPENDENCIES: "
730 << TRI->getRegClassName(RC) << " **********\n");
732 // If no relevant registers are used in the function, we can skip it
734 bool anyregs = false;
735 const MachineRegisterInfo &MRI = mf.getRegInfo();
736 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
737 I != E && !anyregs; ++I)
738 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
739 if (!MRI.reg_nodbg_empty(*AI)) {
743 if (!anyregs) return false;
745 // Initialize the AliasMap on the first use.
746 if (AliasMap.empty()) {
747 // Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and
748 // therefore the LiveRegs array.
749 AliasMap.resize(TRI->getNumRegs());
750 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
751 for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true);
753 AliasMap[*AI].push_back(i);
756 MachineBasicBlock *Entry = MF->begin();
757 ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
758 SmallVector<MachineBasicBlock*, 16> Loops;
759 for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
760 MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
761 MachineBasicBlock *MBB = *MBBI;
762 enterBasicBlock(MBB);
763 if (SeenUnknownBackEdge)
764 Loops.push_back(MBB);
765 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
768 processUndefReads(MBB);
769 leaveBasicBlock(MBB);
772 // Visit all the loop blocks again in order to merge DomainValues from
774 for (unsigned i = 0, e = Loops.size(); i != e; ++i) {
775 MachineBasicBlock *MBB = Loops[i];
776 enterBasicBlock(MBB);
777 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
779 if (!I->isDebugValue())
780 processDefs(I, false);
781 processUndefReads(MBB);
782 leaveBasicBlock(MBB);
785 // Clear the LiveOuts vectors and collapse any remaining DomainValues.
786 for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
787 MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
788 LiveOutMap::const_iterator FI = LiveOuts.find(*MBBI);
789 if (FI == LiveOuts.end() || !FI->second)
791 for (unsigned i = 0, e = NumRegs; i != e; ++i)
792 if (FI->second[i].Value)
793 release(FI->second[i].Value);
799 Allocator.DestroyAll();
805 llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
806 return new ExeDepsFix(RC);