1 //===-- EarlyIfConversion.cpp - If-conversion on SSA form machine code ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Early if-conversion is for out-of-order CPUs that don't have a lot of
11 // predicable instructions. The goal is to eliminate conditional branches that
14 // Instructions from both sides of the branch are executed specutatively, and a
15 // cmov instruction selects the result.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "early-ifcvt"
20 #include "MachineTraceMetrics.h"
21 #include "llvm/Function.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/PostOrderIterator.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/SparseSet.h"
27 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
28 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #include "llvm/CodeGen/MachineLoopInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/MC/MCInstrItineraries.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/raw_ostream.h"
43 // Absolute maximum number of instructions allowed per speculated block.
44 // This bypasses all other heuristics, so it should be set fairly high.
45 static cl::opt<unsigned>
46 BlockInstrLimit("early-ifcvt-limit", cl::init(30), cl::Hidden,
47 cl::desc("Maximum number of instructions per speculated block."));
49 // Stress testing mode - disable heuristics.
50 static cl::opt<bool> Stress("stress-early-ifcvt", cl::Hidden,
51 cl::desc("Turn all knobs to 11"));
53 typedef SmallSetVector<MachineBasicBlock*, 8> BlockSetVector;
55 //===----------------------------------------------------------------------===//
57 //===----------------------------------------------------------------------===//
59 // The SSAIfConv class performs if-conversion on SSA form machine code after
60 // determining if it is possible. The class contains no heuristics; external
61 // code should be used to determine when if-conversion is a good idea.
63 // SSAIfConv can convert both triangles and diamonds:
65 // Triangle: Head Diamond: Head
73 // Instructions in the conditional blocks TBB and/or FBB are spliced into the
74 // Head block, and phis in the Tail block are converted to select instructions.
78 const TargetInstrInfo *TII;
79 const TargetRegisterInfo *TRI;
80 MachineRegisterInfo *MRI;
83 /// The block containing the conditional branch.
84 MachineBasicBlock *Head;
86 /// The block containing phis after the if-then-else.
87 MachineBasicBlock *Tail;
89 /// The 'true' conditional block as determined by AnalyzeBranch.
90 MachineBasicBlock *TBB;
92 /// The 'false' conditional block as determined by AnalyzeBranch.
93 MachineBasicBlock *FBB;
95 /// isTriangle - When there is no 'else' block, either TBB or FBB will be
97 bool isTriangle() const { return TBB == Tail || FBB == Tail; }
99 /// Information about each phi in the Tail block.
103 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
104 int CondCycles, TCycles, FCycles;
106 PHIInfo(MachineInstr *phi)
107 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
110 SmallVector<PHIInfo, 8> PHIs;
113 /// The branch condition determined by AnalyzeBranch.
114 SmallVector<MachineOperand, 4> Cond;
116 /// Instructions in Head that define values used by the conditional blocks.
117 /// The hoisted instructions must be inserted after these instructions.
118 SmallPtrSet<MachineInstr*, 8> InsertAfter;
120 /// Register units clobbered by the conditional blocks.
121 BitVector ClobberedRegUnits;
123 // Scratch pad for findInsertionPoint.
124 SparseSet<unsigned> LiveRegUnits;
126 /// Insertion point in Head for speculatively executed instructions form TBB
128 MachineBasicBlock::iterator InsertionPoint;
130 /// Return true if all non-terminator instructions in MBB can be safely
132 bool canSpeculateInstrs(MachineBasicBlock *MBB);
134 /// Find a valid insertion point in Head.
135 bool findInsertionPoint();
138 /// runOnMachineFunction - Initialize per-function data structures.
139 void runOnMachineFunction(MachineFunction &MF) {
140 TII = MF.getTarget().getInstrInfo();
141 TRI = MF.getTarget().getRegisterInfo();
142 MRI = &MF.getRegInfo();
143 LiveRegUnits.clear();
144 LiveRegUnits.setUniverse(TRI->getNumRegUnits());
145 ClobberedRegUnits.clear();
146 ClobberedRegUnits.resize(TRI->getNumRegUnits());
149 /// canConvertIf - If the sub-CFG headed by MBB can be if-converted,
150 /// initialize the internal state, and return true.
151 bool canConvertIf(MachineBasicBlock *MBB);
153 /// convertIf - If-convert the last block passed to canConvertIf(), assuming
154 /// it is possible. Add any erased blocks to RemovedBlocks.
155 void convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks);
157 } // end anonymous namespace
160 /// canSpeculateInstrs - Returns true if all the instructions in MBB can safely
161 /// be speculated. The terminators are not considered.
163 /// If instructions use any values that are defined in the head basic block,
164 /// the defining instructions are added to InsertAfter.
166 /// Any clobbered regunits are added to ClobberedRegUnits.
168 bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
169 // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
171 if (!MBB->livein_empty()) {
172 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
176 unsigned InstrCount = 0;
178 // Check all instructions, except the terminators. It is assumed that
179 // terminators never have side effects or define any used register values.
180 for (MachineBasicBlock::iterator I = MBB->begin(),
181 E = MBB->getFirstTerminator(); I != E; ++I) {
182 if (I->isDebugValue())
185 if (++InstrCount > BlockInstrLimit && !Stress) {
186 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has more than "
187 << BlockInstrLimit << " instructions.\n");
191 // There shouldn't normally be any phis in a single-predecessor block.
193 DEBUG(dbgs() << "Can't hoist: " << *I);
197 // Don't speculate loads. Note that it may be possible and desirable to
198 // speculate GOT or constant pool loads that are guaranteed not to trap,
199 // but we don't support that for now.
201 DEBUG(dbgs() << "Won't speculate load: " << *I);
205 // We never speculate stores, so an AA pointer isn't necessary.
206 bool DontMoveAcrossStore = true;
207 if (!I->isSafeToMove(TII, 0, DontMoveAcrossStore)) {
208 DEBUG(dbgs() << "Can't speculate: " << *I);
212 // Check for any dependencies on Head instructions.
213 for (MIOperands MO(I); MO.isValid(); ++MO) {
214 if (MO->isRegMask()) {
215 DEBUG(dbgs() << "Won't speculate regmask: " << *I);
220 unsigned Reg = MO->getReg();
222 // Remember clobbered regunits.
223 if (MO->isDef() && TargetRegisterInfo::isPhysicalRegister(Reg))
224 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
225 ClobberedRegUnits.set(*Units);
227 if (!MO->readsReg() || !TargetRegisterInfo::isVirtualRegister(Reg))
229 MachineInstr *DefMI = MRI->getVRegDef(Reg);
230 if (!DefMI || DefMI->getParent() != Head)
232 if (InsertAfter.insert(DefMI))
233 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI);
234 if (DefMI->isTerminator()) {
235 DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
244 /// Find an insertion point in Head for the speculated instructions. The
245 /// insertion point must be:
247 /// 1. Before any terminators.
248 /// 2. After any instructions in InsertAfter.
249 /// 3. Not have any clobbered regunits live.
251 /// This function sets InsertionPoint and returns true when successful, it
252 /// returns false if no valid insertion point could be found.
254 bool SSAIfConv::findInsertionPoint() {
255 // Keep track of live regunits before the current position.
256 // Only track RegUnits that are also in ClobberedRegUnits.
257 LiveRegUnits.clear();
258 SmallVector<unsigned, 8> Reads;
259 MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
260 MachineBasicBlock::iterator I = Head->end();
261 MachineBasicBlock::iterator B = Head->begin();
264 // Some of the conditional code depends in I.
265 if (InsertAfter.count(I)) {
266 DEBUG(dbgs() << "Can't insert code after " << *I);
270 // Update live regunits.
271 for (MIOperands MO(I); MO.isValid(); ++MO) {
272 // We're ignoring regmask operands. That is conservatively correct.
275 unsigned Reg = MO->getReg();
276 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
278 // I clobbers Reg, so it isn't live before I.
280 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
281 LiveRegUnits.erase(*Units);
282 // Unless I reads Reg.
284 Reads.push_back(Reg);
286 // Anything read by I is live before I.
287 while (!Reads.empty())
288 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
290 if (ClobberedRegUnits.test(*Units))
291 LiveRegUnits.insert(*Units);
293 // We can't insert before a terminator.
294 if (I != FirstTerm && I->isTerminator())
297 // Some of the clobbered registers are live before I, not a valid insertion
299 if (!LiveRegUnits.empty()) {
301 dbgs() << "Would clobber";
302 for (SparseSet<unsigned>::const_iterator
303 i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i)
304 dbgs() << ' ' << PrintRegUnit(*i, TRI);
305 dbgs() << " live before " << *I;
310 // This is a valid insertion point.
312 DEBUG(dbgs() << "Can insert before " << *I);
315 DEBUG(dbgs() << "No legal insertion point found.\n");
321 /// canConvertIf - analyze the sub-cfg rooted in MBB, and return true if it is
322 /// a potential candidate for if-conversion. Fill out the internal state.
324 bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
326 TBB = FBB = Tail = 0;
328 if (Head->succ_size() != 2)
330 MachineBasicBlock *Succ0 = Head->succ_begin()[0];
331 MachineBasicBlock *Succ1 = Head->succ_begin()[1];
333 // Canonicalize so Succ0 has MBB as its single predecessor.
334 if (Succ0->pred_size() != 1)
335 std::swap(Succ0, Succ1);
337 if (Succ0->pred_size() != 1 || Succ0->succ_size() != 1)
340 // We could support additional Tail predecessors by updating phis instead of
341 // eliminating them. Let's see an example where it matters first.
342 Tail = Succ0->succ_begin()[0];
343 if (Tail->pred_size() != 2)
346 // This is not a triangle.
348 // Check for a diamond. We won't deal with any critical edges.
349 if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 ||
350 Succ1->succ_begin()[0] != Tail)
352 DEBUG(dbgs() << "\nDiamond: BB#" << Head->getNumber()
353 << " -> BB#" << Succ0->getNumber()
354 << "/BB#" << Succ1->getNumber()
355 << " -> BB#" << Tail->getNumber() << '\n');
357 // Live-in physregs are tricky to get right when speculating code.
358 if (!Tail->livein_empty()) {
359 DEBUG(dbgs() << "Tail has live-ins.\n");
363 DEBUG(dbgs() << "\nTriangle: BB#" << Head->getNumber()
364 << " -> BB#" << Succ0->getNumber()
365 << " -> BB#" << Tail->getNumber() << '\n');
368 // This is a triangle or a diamond.
369 // If Tail doesn't have any phis, there must be side effects.
370 if (Tail->empty() || !Tail->front().isPHI()) {
371 DEBUG(dbgs() << "No phis in tail.\n");
375 // The branch we're looking to eliminate must be analyzable.
377 if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) {
378 DEBUG(dbgs() << "Branch not analyzable.\n");
382 // This is weird, probably some sort of degenerate CFG.
384 DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n");
388 // AnalyzeBranch doesn't set FBB on a fall-through branch.
389 // Make sure it is always set.
390 FBB = TBB == Succ0 ? Succ1 : Succ0;
392 // Any phis in the tail block must be convertible to selects.
394 MachineBasicBlock *TPred = TBB == Tail ? Head : TBB;
395 MachineBasicBlock *FPred = FBB == Tail ? Head : FBB;
396 for (MachineBasicBlock::iterator I = Tail->begin(), E = Tail->end();
397 I != E && I->isPHI(); ++I) {
399 PHIInfo &PI = PHIs.back();
400 // Find PHI operands corresponding to TPred and FPred.
401 for (unsigned i = 1; i != PI.PHI->getNumOperands(); i += 2) {
402 if (PI.PHI->getOperand(i+1).getMBB() == TPred)
403 PI.TReg = PI.PHI->getOperand(i).getReg();
404 if (PI.PHI->getOperand(i+1).getMBB() == FPred)
405 PI.FReg = PI.PHI->getOperand(i).getReg();
407 assert(TargetRegisterInfo::isVirtualRegister(PI.TReg) && "Bad PHI");
408 assert(TargetRegisterInfo::isVirtualRegister(PI.FReg) && "Bad PHI");
410 // Get target information.
411 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
412 PI.CondCycles, PI.TCycles, PI.FCycles)) {
413 DEBUG(dbgs() << "Can't convert: " << *PI.PHI);
418 // Check that the conditional instructions can be speculated.
420 ClobberedRegUnits.reset();
421 if (TBB != Tail && !canSpeculateInstrs(TBB))
423 if (FBB != Tail && !canSpeculateInstrs(FBB))
426 // Try to find a valid insertion point for the speculated instructions in the
428 if (!findInsertionPoint())
435 /// convertIf - Execute the if conversion after canConvertIf has determined the
438 /// Any basic blocks erased will be added to RemovedBlocks.
440 void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) {
441 assert(Head && Tail && TBB && FBB && "Call canConvertIf first.");
443 // Move all instructions into Head, except for the terminators.
445 Head->splice(InsertionPoint, TBB, TBB->begin(), TBB->getFirstTerminator());
447 Head->splice(InsertionPoint, FBB, FBB->begin(), FBB->getFirstTerminator());
449 MachineBasicBlock::iterator FirstTerm = Head->getFirstTerminator();
450 assert(FirstTerm != Head->end() && "No terminators");
451 DebugLoc HeadDL = FirstTerm->getDebugLoc();
453 // Convert all PHIs to select instructions inserted before FirstTerm.
454 for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
455 PHIInfo &PI = PHIs[i];
456 DEBUG(dbgs() << "If-converting " << *PI.PHI);
457 assert(PI.PHI->getNumOperands() == 5 && "Unexpected PHI operands.");
458 unsigned DstReg = PI.PHI->getOperand(0).getReg();
459 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
460 DEBUG(dbgs() << " --> " << *llvm::prior(FirstTerm));
461 PI.PHI->eraseFromParent();
465 // Fix up the CFG, temporarily leave Head without any successors.
466 Head->removeSuccessor(TBB);
467 Head->removeSuccessor(FBB);
469 TBB->removeSuccessor(Tail);
471 FBB->removeSuccessor(Tail);
473 // Fix up Head's terminators.
474 // It should become a single branch or a fallthrough.
475 TII->RemoveBranch(*Head);
477 // Erase the now empty conditional blocks. It is likely that Head can fall
478 // through to Tail, and we can join the two blocks.
480 RemovedBlocks.push_back(TBB);
481 TBB->eraseFromParent();
484 RemovedBlocks.push_back(FBB);
485 FBB->eraseFromParent();
488 assert(Head->succ_empty() && "Additional head successors?");
489 if (Head->isLayoutSuccessor(Tail)) {
490 // Splice Tail onto the end of Head.
491 DEBUG(dbgs() << "Joining tail BB#" << Tail->getNumber()
492 << " into head BB#" << Head->getNumber() << '\n');
493 Head->splice(Head->end(), Tail,
494 Tail->begin(), Tail->end());
495 Head->transferSuccessorsAndUpdatePHIs(Tail);
496 RemovedBlocks.push_back(Tail);
497 Tail->eraseFromParent();
499 // We need a branch to Tail, let code placement work it out later.
500 DEBUG(dbgs() << "Converting to unconditional branch.\n");
501 SmallVector<MachineOperand, 0> EmptyCond;
502 TII->InsertBranch(*Head, Tail, 0, EmptyCond, HeadDL);
503 Head->addSuccessor(Tail);
505 DEBUG(dbgs() << *Head);
509 //===----------------------------------------------------------------------===//
510 // EarlyIfConverter Pass
511 //===----------------------------------------------------------------------===//
514 class EarlyIfConverter : public MachineFunctionPass {
515 const TargetInstrInfo *TII;
516 const TargetRegisterInfo *TRI;
517 const MCSchedModel *SchedModel;
518 MachineRegisterInfo *MRI;
519 MachineDominatorTree *DomTree;
520 MachineLoopInfo *Loops;
521 MachineTraceMetrics *Traces;
522 MachineTraceMetrics::Ensemble *MinInstr;
527 EarlyIfConverter() : MachineFunctionPass(ID) {}
528 void getAnalysisUsage(AnalysisUsage &AU) const;
529 bool runOnMachineFunction(MachineFunction &MF);
532 bool tryConvertIf(MachineBasicBlock*);
533 void updateDomTree(ArrayRef<MachineBasicBlock*> Removed);
534 void updateLoops(ArrayRef<MachineBasicBlock*> Removed);
535 void invalidateTraces();
536 bool shouldConvertIf();
538 } // end anonymous namespace
540 char EarlyIfConverter::ID = 0;
541 char &llvm::EarlyIfConverterID = EarlyIfConverter::ID;
543 INITIALIZE_PASS_BEGIN(EarlyIfConverter,
544 "early-ifcvt", "Early If Converter", false, false)
545 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
546 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
547 INITIALIZE_PASS_DEPENDENCY(MachineTraceMetrics)
548 INITIALIZE_PASS_END(EarlyIfConverter,
549 "early-ifcvt", "Early If Converter", false, false)
551 void EarlyIfConverter::getAnalysisUsage(AnalysisUsage &AU) const {
552 AU.addRequired<MachineBranchProbabilityInfo>();
553 AU.addRequired<MachineDominatorTree>();
554 AU.addPreserved<MachineDominatorTree>();
555 AU.addRequired<MachineLoopInfo>();
556 AU.addPreserved<MachineLoopInfo>();
557 AU.addRequired<MachineTraceMetrics>();
558 AU.addPreserved<MachineTraceMetrics>();
559 MachineFunctionPass::getAnalysisUsage(AU);
562 /// Update the dominator tree after if-conversion erased some blocks.
563 void EarlyIfConverter::updateDomTree(ArrayRef<MachineBasicBlock*> Removed) {
564 // convertIf can remove TBB, FBB, and Tail can be merged into Head.
565 // TBB and FBB should not dominate any blocks.
566 // Tail children should be transferred to Head.
567 MachineDomTreeNode *HeadNode = DomTree->getNode(IfConv.Head);
568 for (unsigned i = 0, e = Removed.size(); i != e; ++i) {
569 MachineDomTreeNode *Node = DomTree->getNode(Removed[i]);
570 assert(Node != HeadNode && "Cannot erase the head node");
571 while (Node->getNumChildren()) {
572 assert(Node->getBlock() == IfConv.Tail && "Unexpected children");
573 DomTree->changeImmediateDominator(Node->getChildren().back(), HeadNode);
575 DomTree->eraseNode(Removed[i]);
579 /// Update LoopInfo after if-conversion.
580 void EarlyIfConverter::updateLoops(ArrayRef<MachineBasicBlock*> Removed) {
583 // If-conversion doesn't change loop structure, and it doesn't mess with back
584 // edges, so updating LoopInfo is simply removing the dead blocks.
585 for (unsigned i = 0, e = Removed.size(); i != e; ++i)
586 Loops->removeBlock(Removed[i]);
589 /// Invalidate MachineTraceMetrics before if-conversion.
590 void EarlyIfConverter::invalidateTraces() {
591 Traces->verifyAnalysis();
592 Traces->invalidate(IfConv.Head);
593 Traces->invalidate(IfConv.Tail);
594 Traces->invalidate(IfConv.TBB);
595 Traces->invalidate(IfConv.FBB);
596 DEBUG(if (MinInstr) MinInstr->print(dbgs()));
597 Traces->verifyAnalysis();
600 /// Apply cost model and heuristics to the if-conversion in IfConv.
601 /// Return true if the conversion is a good idea.
603 bool EarlyIfConverter::shouldConvertIf() {
605 MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
607 // Compare the critical path through TBB and FBB. If the difference is
608 // greater than the branch misprediction penalty, it would never pay to
609 // if-convert. The triangle/diamond topology guarantees that these traces
610 // have the same head and tail, so they can be compared.
611 MachineTraceMetrics::Trace TBBTrace = MinInstr->getTrace(IfConv.TBB);
612 MachineTraceMetrics::Trace FBBTrace = MinInstr->getTrace(IfConv.FBB);
613 DEBUG(dbgs() << "TBB: " << TBBTrace << "FBB: " << FBBTrace);
614 unsigned TBBCrit = TBBTrace.getCriticalPath();
615 unsigned FBBCrit = FBBTrace.getCriticalPath();
616 unsigned ExtraCrit = TBBCrit > FBBCrit ? TBBCrit-FBBCrit : FBBCrit-TBBCrit;
617 if (ExtraCrit >= SchedModel->MispredictPenalty) {
618 DEBUG(dbgs() << "Critical path difference larger than "
619 << SchedModel->MispredictPenalty << ".\n");
625 /// Attempt repeated if-conversion on MBB, return true if successful.
627 bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
628 bool Changed = false;
629 while (IfConv.canConvertIf(MBB) && shouldConvertIf()) {
630 // If-convert MBB and update analyses.
632 SmallVector<MachineBasicBlock*, 4> RemovedBlocks;
633 IfConv.convertIf(RemovedBlocks);
635 updateDomTree(RemovedBlocks);
636 updateLoops(RemovedBlocks);
641 bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
642 DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
643 << "********** Function: "
644 << ((Value*)MF.getFunction())->getName() << '\n');
645 TII = MF.getTarget().getInstrInfo();
646 TRI = MF.getTarget().getRegisterInfo();
647 SchedModel = MF.getTarget().getInstrItineraryData()->SchedModel;
648 MRI = &MF.getRegInfo();
649 DomTree = &getAnalysis<MachineDominatorTree>();
650 Loops = getAnalysisIfAvailable<MachineLoopInfo>();
651 Traces = &getAnalysis<MachineTraceMetrics>();
654 bool Changed = false;
655 IfConv.runOnMachineFunction(MF);
657 // Visit blocks in dominator tree post-order. The post-order enables nested
658 // if-conversion in a single pass. The tryConvertIf() function may erase
659 // blocks, but only blocks dominated by the head block. This makes it safe to
660 // update the dominator tree while the post-order iterator is still active.
661 for (po_iterator<MachineDominatorTree*>
662 I = po_begin(DomTree), E = po_end(DomTree); I != E; ++I)
663 if (tryConvertIf(I->getBlock()))
666 MF.verify(this, "After early if-conversion");