1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains support for writing dwarf debug info into asm files.
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
16 #include "DwarfDebug.h"
17 #include "llvm/ADT/SmallBitVector.h"
18 #include "llvm/CodeGen/AsmPrinter.h"
19 #include "llvm/Support/Dwarf.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetRegisterInfo.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
27 const TargetRegisterInfo *DwarfExpression::getTRI() const {
28 return AP.TM.getSubtargetImpl()->getRegisterInfo();
31 void DwarfExpression::AddReg(int DwarfReg, const char* Comment) {
32 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
34 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
36 EmitOp(dwarf::DW_OP_regx, Comment);
37 EmitUnsigned(DwarfReg);
41 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
42 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
44 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
46 EmitOp(dwarf::DW_OP_bregx);
47 EmitUnsigned(DwarfReg);
51 EmitOp(dwarf::DW_OP_deref);
54 void DwarfExpression::AddOpPiece(unsigned SizeInBits,
55 unsigned OffsetInBits) {
56 assert(SizeInBits > 0 && "piece has size zero");
57 const unsigned SizeOfByte = 8;
58 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
59 EmitOp(dwarf::DW_OP_bit_piece);
60 EmitUnsigned(SizeInBits);
61 EmitUnsigned(OffsetInBits);
63 EmitOp(dwarf::DW_OP_piece);
64 unsigned ByteSize = SizeInBits / SizeOfByte;
65 EmitUnsigned(ByteSize);
69 void DwarfExpression::AddShr(unsigned ShiftBy) {
70 EmitOp(dwarf::DW_OP_constu);
71 EmitUnsigned(ShiftBy);
72 EmitOp(dwarf::DW_OP_shr);
75 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
76 int DwarfReg = getTRI()->getDwarfRegNum(MachineReg, false);
80 if (MachineReg == getFrameRegister()) {
81 // If variable offset is based in frame register then use fbreg.
82 EmitOp(dwarf::DW_OP_fbreg);
85 AddRegIndirect(DwarfReg, Offset);
90 void DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
91 unsigned PieceSizeInBits,
92 unsigned PieceOffsetInBits) {
93 const TargetRegisterInfo *TRI = getTRI();
94 int Reg = TRI->getDwarfRegNum(MachineReg, false);
96 // If this is a valid register number, emit it.
100 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
104 // Walk up the super-register chain until we find a valid number.
105 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
106 for (MCSuperRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
107 Reg = TRI->getDwarfRegNum(*SR, false);
109 unsigned Idx = TRI->getSubRegIndex(*SR, MachineReg);
110 unsigned Size = TRI->getSubRegIdxSize(Idx);
111 unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
112 AddReg(Reg, "super-register");
113 if (PieceOffsetInBits == RegOffset) {
114 AddOpPiece(Size, RegOffset);
116 // If this is part of a variable in a sub-register at a
117 // non-zero offset, we need to manually shift the value into
118 // place, since the DW_OP_piece describes the part of the
119 // variable, not the position of the subregister.
122 AddOpPiece(Size, PieceOffsetInBits);
128 // Otherwise, attempt to find a covering set of sub-register numbers.
129 // For example, Q0 on ARM is a composition of D0+D1.
131 // Keep track of the current position so we can emit the more
132 // efficient DW_OP_piece.
133 unsigned CurPos = PieceOffsetInBits;
134 // The size of the register in bits, assuming 8 bits per byte.
135 unsigned RegSize = TRI->getMinimalPhysRegClass(MachineReg)->getSize() * 8;
136 // Keep track of the bits in the register we already emitted, so we
137 // can avoid emitting redundant aliasing subregs.
138 SmallBitVector Coverage(RegSize, false);
139 for (MCSubRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
140 unsigned Idx = TRI->getSubRegIndex(MachineReg, *SR);
141 unsigned Size = TRI->getSubRegIdxSize(Idx);
142 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
143 Reg = TRI->getDwarfRegNum(*SR, false);
145 // Intersection between the bits we already emitted and the bits
146 // covered by this subregister.
147 SmallBitVector Intersection(RegSize, false);
148 Intersection.set(Offset, Offset + Size);
149 Intersection ^= Coverage;
151 // If this sub-register has a DWARF number and we haven't covered
152 // its range, emit a DWARF piece for it.
153 if (Reg >= 0 && Intersection.any()) {
154 AddReg(Reg, "sub-register");
155 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
156 CurPos = Offset + Size;
158 // Mark it as emitted.
159 Coverage.set(Offset, Offset + Size);
163 if (CurPos == PieceOffsetInBits)
164 // FIXME: We have no reasonable way of handling errors in here.
165 EmitOp(dwarf::DW_OP_nop, "nop (could not find a dwarf register number)");