1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains support for writing dwarf debug info into asm files.
12 //===----------------------------------------------------------------------===//
14 #include "DwarfExpression.h"
15 #include "DwarfDebug.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/Support/Dwarf.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
25 void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
26 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
28 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
30 EmitOp(dwarf::DW_OP_regx, Comment);
31 EmitUnsigned(DwarfReg);
35 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
36 assert(DwarfReg >= 0 && "invalid negative dwarf register number");
38 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
40 EmitOp(dwarf::DW_OP_bregx);
41 EmitUnsigned(DwarfReg);
45 EmitOp(dwarf::DW_OP_deref);
48 void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
49 assert(SizeInBits > 0 && "piece has size zero");
50 const unsigned SizeOfByte = 8;
51 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52 EmitOp(dwarf::DW_OP_bit_piece);
53 EmitUnsigned(SizeInBits);
54 EmitUnsigned(OffsetInBits);
56 EmitOp(dwarf::DW_OP_piece);
57 unsigned ByteSize = SizeInBits / SizeOfByte;
58 EmitUnsigned(ByteSize);
62 void DwarfExpression::AddShr(unsigned ShiftBy) {
63 EmitOp(dwarf::DW_OP_constu);
64 EmitUnsigned(ShiftBy);
65 EmitOp(dwarf::DW_OP_shr);
68 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
69 int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
73 if (isFrameRegister(MachineReg)) {
74 // If variable offset is based in frame register then use fbreg.
75 EmitOp(dwarf::DW_OP_fbreg);
78 AddRegIndirect(DwarfReg, Offset);
83 bool DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
84 unsigned PieceSizeInBits,
85 unsigned PieceOffsetInBits) {
86 if (!TRI.isPhysicalRegister(MachineReg))
89 int Reg = TRI.getDwarfRegNum(MachineReg, false);
91 // If this is a valid register number, emit it.
95 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
99 // Walk up the super-register chain until we find a valid number.
100 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
101 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
102 Reg = TRI.getDwarfRegNum(*SR, false);
104 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
105 unsigned Size = TRI.getSubRegIdxSize(Idx);
106 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
107 AddReg(Reg, "super-register");
108 if (PieceOffsetInBits == RegOffset) {
109 AddOpPiece(Size, RegOffset);
111 // If this is part of a variable in a sub-register at a
112 // non-zero offset, we need to manually shift the value into
113 // place, since the DW_OP_piece describes the part of the
114 // variable, not the position of the subregister.
117 AddOpPiece(Size, PieceOffsetInBits);
123 // Otherwise, attempt to find a covering set of sub-register numbers.
124 // For example, Q0 on ARM is a composition of D0+D1.
126 // Keep track of the current position so we can emit the more
127 // efficient DW_OP_piece.
128 unsigned CurPos = PieceOffsetInBits;
129 // The size of the register in bits, assuming 8 bits per byte.
130 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
131 // Keep track of the bits in the register we already emitted, so we
132 // can avoid emitting redundant aliasing subregs.
133 SmallBitVector Coverage(RegSize, false);
134 for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
135 unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
136 unsigned Size = TRI.getSubRegIdxSize(Idx);
137 unsigned Offset = TRI.getSubRegIdxOffset(Idx);
138 Reg = TRI.getDwarfRegNum(*SR, false);
140 // Intersection between the bits we already emitted and the bits
141 // covered by this subregister.
142 SmallBitVector Intersection(RegSize, false);
143 Intersection.set(Offset, Offset + Size);
144 Intersection ^= Coverage;
146 // If this sub-register has a DWARF number and we haven't covered
147 // its range, emit a DWARF piece for it.
148 if (Reg >= 0 && Intersection.any()) {
149 AddReg(Reg, "sub-register");
150 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
151 CurPos = Offset + Size;
153 // Mark it as emitted.
154 Coverage.set(Offset, Offset + Size);
158 return CurPos > PieceOffsetInBits;
161 void DwarfExpression::AddSignedConstant(int Value) {
162 EmitOp(dwarf::DW_OP_consts);
164 // The proper way to describe a constant value is
165 // DW_OP_constu <const>, DW_OP_stack_value.
166 // Unfortunately, DW_OP_stack_value was not available until DWARF-4,
167 // so we will continue to generate DW_OP_constu <const> for DWARF-2
168 // and DWARF-3. Technically, this is incorrect since DW_OP_const <const>
169 // actually describes a value at a constant addess, not a constant value.
170 // However, in the past there was no better way to describe a constant
171 // value, so the producers and consumers started to rely on heuristics
172 // to disambiguate the value vs. location status of the expression.
173 // See PR21176 for more details.
174 if (DwarfVersion >= 4)
175 EmitOp(dwarf::DW_OP_stack_value);
178 void DwarfExpression::AddUnsignedConstant(unsigned Value) {
179 EmitOp(dwarf::DW_OP_constu);
181 // cf. comment in DwarfExpression::AddSignedConstant().
182 if (DwarfVersion >= 4)
183 EmitOp(dwarf::DW_OP_stack_value);
186 static unsigned getOffsetOrZero(unsigned OffsetInBits,
187 unsigned PieceOffsetInBits) {
188 if (OffsetInBits == PieceOffsetInBits)
190 assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
194 bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
196 unsigned PieceOffsetInBits) {
197 auto I = Expr.begin();
198 // Pattern-match combinations for which more efficient representations exist
201 return AddMachineRegPiece(MachineReg);
203 bool ValidReg = false;
205 case dwarf::DW_OP_bit_piece: {
206 unsigned OffsetInBits = I->getArg(1);
207 unsigned SizeInBits = I->getArg(2);
208 // Piece always comes at the end of the expression.
209 return AddMachineRegPiece(MachineReg, SizeInBits,
210 getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
212 case dwarf::DW_OP_plus:
213 // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
214 if (I->getNext() == dwarf::DW_OP_deref) {
215 unsigned Offset = I->getArg(1);
216 ValidReg = AddMachineRegIndirect(MachineReg, Offset);
220 ValidReg = AddMachineRegPiece(MachineReg);
221 case dwarf::DW_OP_deref:
222 // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
223 ValidReg = AddMachineRegIndirect(MachineReg);
227 llvm_unreachable("unsupported operand");
233 // Emit remaining elements of the expression.
234 AddExpression(I, Expr.end(), PieceOffsetInBits);
238 void DwarfExpression::AddExpression(DIExpression::iterator I,
239 DIExpression::iterator E,
240 unsigned PieceOffsetInBits) {
241 for (; I != E; ++I) {
243 case dwarf::DW_OP_bit_piece: {
244 unsigned OffsetInBits = I->getArg(1);
245 unsigned SizeInBits = I->getArg(2);
246 AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
249 case dwarf::DW_OP_plus:
250 EmitOp(dwarf::DW_OP_plus_uconst);
251 EmitUnsigned(I->getArg(1));
253 case dwarf::DW_OP_deref:
254 EmitOp(dwarf::DW_OP_deref);
257 llvm_unreachable("unhandled opcode found in DIExpression");