1 //===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AggressiveAntiDepBreaker class, which
11 // implements register anti-dependence breaking during post-RA
12 // scheduling. It attempts to break all anti-dependencies within a
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "post-RA-sched"
18 #include "AggressiveAntiDepBreaker.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/Target/TargetInstrInfo.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Support/raw_ostream.h"
32 AntiDepTrials("agg-antidep-trials",
33 cl::desc("Maximum number of anti-dependency breaking passes"),
34 cl::init(1), cl::Hidden);
36 AggressiveAntiDepState::AggressiveAntiDepState(MachineBasicBlock *BB) :
37 GroupNodes(TargetRegisterInfo::FirstVirtualRegister, 0) {
38 // Initialize all registers to be in their own group. Initially we
39 // assign the register to the same-indexed GroupNode.
40 for (unsigned i = 0; i < TargetRegisterInfo::FirstVirtualRegister; ++i)
41 GroupNodeIndices[i] = i;
43 // Initialize the indices to indicate that no registers are live.
44 std::fill(KillIndices, array_endof(KillIndices), ~0u);
45 std::fill(DefIndices, array_endof(DefIndices), BB->size());
48 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg)
50 unsigned Node = GroupNodeIndices[Reg];
51 while (GroupNodes[Node] != Node)
52 Node = GroupNodes[Node];
57 void AggressiveAntiDepState::GetGroupRegs(unsigned Group, std::vector<unsigned> &Regs)
59 for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
60 if (GetGroup(Reg) == Group)
65 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
67 assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
68 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
70 // find group for each register
71 unsigned Group1 = GetGroup(Reg1);
72 unsigned Group2 = GetGroup(Reg2);
74 // if either group is 0, then that must become the parent
75 unsigned Parent = (Group1 == 0) ? Group1 : Group2;
76 unsigned Other = (Parent == Group1) ? Group2 : Group1;
77 GroupNodes.at(Other) = Parent;
81 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
83 // Create a new GroupNode for Reg. Reg's existing GroupNode must
84 // stay as is because there could be other GroupNodes referring to
86 unsigned idx = GroupNodes.size();
87 GroupNodes.push_back(idx);
88 GroupNodeIndices[Reg] = idx;
92 bool AggressiveAntiDepState::IsLive(unsigned Reg)
94 // KillIndex must be defined and DefIndex not defined for a register
96 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
101 AggressiveAntiDepBreaker::
102 AggressiveAntiDepBreaker(MachineFunction& MFi) :
103 AntiDepBreaker(), MF(MFi),
104 MRI(MF.getRegInfo()),
105 TRI(MF.getTarget().getRegisterInfo()),
106 AllocatableSet(TRI->getAllocatableSet(MF)),
107 State(NULL), SavedState(NULL) {
110 AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
115 unsigned AggressiveAntiDepBreaker::GetMaxTrials() {
116 if (AntiDepTrials <= 0)
118 return AntiDepTrials;
121 void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
122 assert(State == NULL);
123 State = new AggressiveAntiDepState(BB);
125 bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn());
126 unsigned *KillIndices = State->GetKillIndices();
127 unsigned *DefIndices = State->GetDefIndices();
129 // Determine the live-out physregs for this block.
131 // In a return block, examine the function live-out regs.
132 for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
133 E = MRI.liveout_end(); I != E; ++I) {
135 State->UnionGroups(Reg, 0);
136 KillIndices[Reg] = BB->size();
137 DefIndices[Reg] = ~0u;
138 // Repeat, for all aliases.
139 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
140 unsigned AliasReg = *Alias;
141 State->UnionGroups(AliasReg, 0);
142 KillIndices[AliasReg] = BB->size();
143 DefIndices[AliasReg] = ~0u;
147 // In a non-return block, examine the live-in regs of all successors.
148 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
149 SE = BB->succ_end(); SI != SE; ++SI)
150 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
151 E = (*SI)->livein_end(); I != E; ++I) {
153 State->UnionGroups(Reg, 0);
154 KillIndices[Reg] = BB->size();
155 DefIndices[Reg] = ~0u;
156 // Repeat, for all aliases.
157 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
158 unsigned AliasReg = *Alias;
159 State->UnionGroups(AliasReg, 0);
160 KillIndices[AliasReg] = BB->size();
161 DefIndices[AliasReg] = ~0u;
166 // Mark live-out callee-saved registers. In a return block this is
167 // all callee-saved registers. In non-return this is any
168 // callee-saved register that is not saved in the prolog.
169 const MachineFrameInfo *MFI = MF.getFrameInfo();
170 BitVector Pristine = MFI->getPristineRegs(BB);
171 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) {
173 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
174 State->UnionGroups(Reg, 0);
175 KillIndices[Reg] = BB->size();
176 DefIndices[Reg] = ~0u;
177 // Repeat, for all aliases.
178 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
179 unsigned AliasReg = *Alias;
180 State->UnionGroups(AliasReg, 0);
181 KillIndices[AliasReg] = BB->size();
182 DefIndices[AliasReg] = ~0u;
187 void AggressiveAntiDepBreaker::FinishBlock() {
194 void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
195 unsigned InsertPosIndex) {
196 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
198 std::set<unsigned> PassthruRegs;
199 GetPassthruRegs(MI, PassthruRegs);
200 PrescanInstruction(MI, Count, PassthruRegs);
201 ScanInstruction(MI, Count);
203 DEBUG(errs() << "Observe: ");
205 DEBUG(errs() << "\tRegs:");
207 unsigned *DefIndices = State->GetDefIndices();
208 for (unsigned Reg = 0; Reg != TargetRegisterInfo::FirstVirtualRegister; ++Reg) {
209 // If Reg is current live, then mark that it can't be renamed as
210 // we don't know the extent of its live-range anymore (now that it
211 // has been scheduled). If it is not live but was defined in the
212 // previous schedule region, then set its def index to the most
213 // conservative location (i.e. the beginning of the previous
215 if (State->IsLive(Reg)) {
216 DEBUG(if (State->GetGroup(Reg) != 0)
217 errs() << " " << TRI->getName(Reg) << "=g" <<
218 State->GetGroup(Reg) << "->g0(region live-out)");
219 State->UnionGroups(Reg, 0);
220 } else if ((DefIndices[Reg] < InsertPosIndex) && (DefIndices[Reg] >= Count)) {
221 DefIndices[Reg] = Count;
224 DEBUG(errs() << '\n');
226 // We're starting a new schedule region so forget any saved state.
231 bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
234 if (!MO.isReg() || !MO.isImplicit())
237 unsigned Reg = MO.getReg();
241 MachineOperand *Op = NULL;
243 Op = MI->findRegisterUseOperand(Reg, true);
245 Op = MI->findRegisterDefOperand(Reg);
247 return((Op != NULL) && Op->isImplicit());
250 void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
251 std::set<unsigned>& PassthruRegs) {
252 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
253 MachineOperand &MO = MI->getOperand(i);
254 if (!MO.isReg()) continue;
255 if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
256 IsImplicitDefUse(MI, MO)) {
257 const unsigned Reg = MO.getReg();
258 PassthruRegs.insert(Reg);
259 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
261 PassthruRegs.insert(*Subreg);
267 /// AntiDepPathStep - Return SUnit that SU has an anti-dependence on.
268 static void AntiDepPathStep(SUnit *SU, AntiDepBreaker::AntiDepRegVector& Regs,
269 std::vector<SDep*>& Edges) {
270 AntiDepBreaker::AntiDepRegSet RegSet;
271 for (unsigned i = 0, e = Regs.size(); i < e; ++i)
272 RegSet.insert(Regs[i]);
274 for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
276 if (P->getKind() == SDep::Anti) {
277 unsigned Reg = P->getReg();
278 if (RegSet.count(Reg) != 0) {
279 Edges.push_back(&*P);
285 assert(RegSet.empty() && "Expected all antidep registers to be found");
288 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
290 unsigned *KillIndices = State->GetKillIndices();
291 unsigned *DefIndices = State->GetDefIndices();
292 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
293 RegRefs = State->GetRegRefs();
295 if (!State->IsLive(Reg)) {
296 KillIndices[Reg] = KillIdx;
297 DefIndices[Reg] = ~0u;
299 State->LeaveGroup(Reg);
300 DEBUG(errs() << "->g" << State->GetGroup(Reg) << tag);
302 // Repeat for subregisters.
303 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
305 unsigned SubregReg = *Subreg;
306 if (!State->IsLive(SubregReg)) {
307 KillIndices[SubregReg] = KillIdx;
308 DefIndices[SubregReg] = ~0u;
309 RegRefs.erase(SubregReg);
310 State->LeaveGroup(SubregReg);
311 DEBUG(errs() << " " << TRI->getName(SubregReg) << "->g" <<
312 State->GetGroup(SubregReg) << tag);
317 void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI, unsigned Count,
318 std::set<unsigned>& PassthruRegs) {
319 unsigned *DefIndices = State->GetDefIndices();
320 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
321 RegRefs = State->GetRegRefs();
323 // Handle dead defs by simulating a last-use of the register just
324 // after the def. A dead def can occur because the def is truely
325 // dead, or because only a subregister is live at the def. If we
326 // don't do this the dead def will be incorrectly merged into the
328 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
329 MachineOperand &MO = MI->getOperand(i);
330 if (!MO.isReg() || !MO.isDef()) continue;
331 unsigned Reg = MO.getReg();
332 if (Reg == 0) continue;
334 DEBUG(errs() << "\tDead Def: " << TRI->getName(Reg));
335 HandleLastUse(Reg, Count + 1, "");
336 DEBUG(errs() << '\n');
339 DEBUG(errs() << "\tDef Groups:");
340 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
341 MachineOperand &MO = MI->getOperand(i);
342 if (!MO.isReg() || !MO.isDef()) continue;
343 unsigned Reg = MO.getReg();
344 if (Reg == 0) continue;
346 DEBUG(errs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
348 // If MI's defs have a special allocation requirement, don't allow
349 // any def registers to be changed. Also assume all registers
350 // defined in a call must not be changed (ABI).
351 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq()) {
352 DEBUG(if (State->GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
353 State->UnionGroups(Reg, 0);
356 // Any aliased that are live at this point are completely or
357 // partially defined here, so group those aliases with Reg.
358 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
359 unsigned AliasReg = *Alias;
360 if (State->IsLive(AliasReg)) {
361 State->UnionGroups(Reg, AliasReg);
362 DEBUG(errs() << "->g" << State->GetGroup(Reg) << "(via " <<
363 TRI->getName(AliasReg) << ")");
367 // Note register reference...
368 const TargetRegisterClass *RC = NULL;
369 if (i < MI->getDesc().getNumOperands())
370 RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
371 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
372 RegRefs.insert(std::make_pair(Reg, RR));
375 DEBUG(errs() << '\n');
377 // Scan the register defs for this instruction and update
379 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
380 MachineOperand &MO = MI->getOperand(i);
381 if (!MO.isReg() || !MO.isDef()) continue;
382 unsigned Reg = MO.getReg();
383 if (Reg == 0) continue;
384 // Ignore passthru registers for liveness...
385 if (PassthruRegs.count(Reg) != 0) continue;
387 // Update def for Reg and subregs.
388 DefIndices[Reg] = Count;
389 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
391 unsigned SubregReg = *Subreg;
392 DefIndices[SubregReg] = Count;
397 void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
399 DEBUG(errs() << "\tUse Groups:");
400 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
401 RegRefs = State->GetRegRefs();
403 // Scan the register uses for this instruction and update
404 // live-ranges, groups and RegRefs.
405 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
406 MachineOperand &MO = MI->getOperand(i);
407 if (!MO.isReg() || !MO.isUse()) continue;
408 unsigned Reg = MO.getReg();
409 if (Reg == 0) continue;
411 DEBUG(errs() << " " << TRI->getName(Reg) << "=g" <<
412 State->GetGroup(Reg));
414 // It wasn't previously live but now it is, this is a kill. Forget
415 // the previous live-range information and start a new live-range
417 HandleLastUse(Reg, Count, "(last-use)");
419 // If MI's uses have special allocation requirement, don't allow
420 // any use registers to be changed. Also assume all registers
421 // used in a call must not be changed (ABI).
422 if (MI->getDesc().isCall() || MI->getDesc().hasExtraSrcRegAllocReq()) {
423 DEBUG(if (State->GetGroup(Reg) != 0) errs() << "->g0(alloc-req)");
424 State->UnionGroups(Reg, 0);
427 // Note register reference...
428 const TargetRegisterClass *RC = NULL;
429 if (i < MI->getDesc().getNumOperands())
430 RC = MI->getDesc().OpInfo[i].getRegClass(TRI);
431 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
432 RegRefs.insert(std::make_pair(Reg, RR));
435 DEBUG(errs() << '\n');
437 // Form a group of all defs and uses of a KILL instruction to ensure
438 // that all registers are renamed as a group.
439 if (MI->getOpcode() == TargetInstrInfo::KILL) {
440 DEBUG(errs() << "\tKill Group:");
442 unsigned FirstReg = 0;
443 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
444 MachineOperand &MO = MI->getOperand(i);
445 if (!MO.isReg()) continue;
446 unsigned Reg = MO.getReg();
447 if (Reg == 0) continue;
450 DEBUG(errs() << "=" << TRI->getName(Reg));
451 State->UnionGroups(FirstReg, Reg);
453 DEBUG(errs() << " " << TRI->getName(Reg));
458 DEBUG(errs() << "->g" << State->GetGroup(FirstReg) << '\n');
462 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
463 BitVector BV(TRI->getNumRegs(), false);
466 // Check all references that need rewriting for Reg. For each, use
467 // the corresponding register class to narrow the set of registers
468 // that are appropriate for renaming.
469 std::pair<std::multimap<unsigned,
470 AggressiveAntiDepState::RegisterReference>::iterator,
471 std::multimap<unsigned,
472 AggressiveAntiDepState::RegisterReference>::iterator>
473 Range = State->GetRegRefs().equal_range(Reg);
474 for (std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>::iterator
475 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
476 const TargetRegisterClass *RC = Q->second.RC;
477 if (RC == NULL) continue;
479 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
487 DEBUG(errs() << " " << RC->getName());
493 bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
494 unsigned AntiDepGroupIndex,
495 std::map<unsigned, unsigned> &RenameMap) {
496 unsigned *KillIndices = State->GetKillIndices();
497 unsigned *DefIndices = State->GetDefIndices();
498 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
499 RegRefs = State->GetRegRefs();
501 // Collect all registers in the same group as AntiDepReg. These all
502 // need to be renamed together if we are to break the
504 std::vector<unsigned> Regs;
505 State->GetGroupRegs(AntiDepGroupIndex, Regs);
506 assert(Regs.size() > 0 && "Empty register group!");
507 if (Regs.size() == 0)
510 // Find the "superest" register in the group. At the same time,
511 // collect the BitVector of registers that can be used to rename
513 DEBUG(errs() << "\tRename Candidates for Group g" << AntiDepGroupIndex << ":\n");
514 std::map<unsigned, BitVector> RenameRegisterMap;
515 unsigned SuperReg = 0;
516 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
517 unsigned Reg = Regs[i];
518 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
521 // If Reg has any references, then collect possible rename regs
522 if (RegRefs.count(Reg) > 0) {
523 DEBUG(errs() << "\t\t" << TRI->getName(Reg) << ":");
525 BitVector BV = GetRenameRegisters(Reg);
526 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
528 DEBUG(errs() << " ::");
529 DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
530 errs() << " " << TRI->getName(r));
531 DEBUG(errs() << "\n");
535 // All group registers should be a subreg of SuperReg.
536 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
537 unsigned Reg = Regs[i];
538 if (Reg == SuperReg) continue;
539 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
540 assert(IsSub && "Expecting group subregister");
545 // FIXME: for now just handle single register in group case...
546 // FIXME: check only regs that have references...
550 // Check each possible rename register for SuperReg. If that register
551 // is available, and the corresponding registers are available for
552 // the other group subregisters, then we can use those registers to
554 DEBUG(errs() << "\tFind Register:");
555 BitVector SuperBV = RenameRegisterMap[SuperReg];
556 for (int r = SuperBV.find_first(); r != -1; r = SuperBV.find_next(r)) {
557 const unsigned Reg = (unsigned)r;
558 // Don't replace a register with itself.
559 if (Reg == SuperReg) continue;
561 DEBUG(errs() << " " << TRI->getName(Reg));
563 // If Reg is dead and Reg's most recent def is not before
564 // SuperRegs's kill, it's safe to replace SuperReg with
565 // Reg. We must also check all subregisters of Reg.
566 if (State->IsLive(Reg) || (KillIndices[SuperReg] > DefIndices[Reg])) {
567 DEBUG(errs() << "(live)");
571 for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
573 unsigned SubregReg = *Subreg;
574 if (State->IsLive(SubregReg) || (KillIndices[SuperReg] > DefIndices[SubregReg])) {
575 DEBUG(errs() << "(subreg " << TRI->getName(SubregReg) << " live)");
585 DEBUG(errs() << '\n');
586 RenameMap.insert(std::pair<unsigned, unsigned>(SuperReg, Reg));
591 DEBUG(errs() << '\n');
593 // No registers are free and available!
597 /// BreakAntiDependencies - Identifiy anti-dependencies within the
598 /// ScheduleDAG and break them by renaming registers.
600 unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
601 std::vector<SUnit>& SUnits,
602 CandidateMap& Candidates,
603 MachineBasicBlock::iterator& Begin,
604 MachineBasicBlock::iterator& End,
605 unsigned InsertPosIndex) {
606 unsigned *KillIndices = State->GetKillIndices();
607 unsigned *DefIndices = State->GetDefIndices();
608 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
609 RegRefs = State->GetRegRefs();
611 // Nothing to do if no candidates.
612 if (Candidates.empty()) {
613 DEBUG(errs() << "\n===== No anti-dependency candidates\n");
617 // The code below assumes that there is at least one instruction,
618 // so just duck out immediately if the block is empty.
619 if (SUnits.empty()) return 0;
621 // Manage saved state to enable multiple passes...
622 if (AntiDepTrials > 1) {
623 if (SavedState == NULL) {
624 SavedState = new AggressiveAntiDepState(*State);
627 State = new AggressiveAntiDepState(*SavedState);
631 // ...need a map from MI to SUnit.
632 std::map<MachineInstr *, SUnit *> MISUnitMap;
634 DEBUG(errs() << "\n===== Attempting to break " << Candidates.size() <<
635 " anti-dependencies\n");
636 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
637 SUnit *SU = &SUnits[i];
638 MISUnitMap.insert(std::pair<MachineInstr *, SUnit *>(SU->getInstr(), SU));
643 DEBUG(errs() << "Available regs:");
644 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
645 if (!State->IsLive(Reg))
646 DEBUG(errs() << " " << TRI->getName(Reg));
648 DEBUG(errs() << '\n');
652 // Attempt to break anti-dependence edges. Walk the instructions
653 // from the bottom up, tracking information about liveness as we go
654 // to help determine which registers are available.
656 unsigned Count = InsertPosIndex - 1;
657 for (MachineBasicBlock::iterator I = End, E = Begin;
659 MachineInstr *MI = --I;
661 DEBUG(errs() << "Anti: ");
664 std::set<unsigned> PassthruRegs;
665 GetPassthruRegs(MI, PassthruRegs);
667 // Process the defs in MI...
668 PrescanInstruction(MI, Count, PassthruRegs);
670 std::vector<SDep*> Edges;
671 SUnit *PathSU = MISUnitMap[MI];
672 AntiDepBreaker::CandidateMap::iterator
673 citer = Candidates.find(PathSU);
674 if (citer != Candidates.end())
675 AntiDepPathStep(PathSU, citer->second, Edges);
677 // Ignore KILL instructions (they form a group in ScanInstruction
678 // but don't cause any anti-dependence breaking themselves)
679 if (MI->getOpcode() != TargetInstrInfo::KILL) {
680 // Attempt to break each anti-dependency...
681 for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
682 SDep *Edge = Edges[i];
683 SUnit *NextSU = Edge->getSUnit();
685 if (Edge->getKind() != SDep::Anti) continue;
687 unsigned AntiDepReg = Edge->getReg();
688 DEBUG(errs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
689 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
691 if (!AllocatableSet.test(AntiDepReg)) {
692 // Don't break anti-dependencies on non-allocatable registers.
693 DEBUG(errs() << " (non-allocatable)\n");
695 } else if (PassthruRegs.count(AntiDepReg) != 0) {
696 // If the anti-dep register liveness "passes-thru", then
697 // don't try to change it. It will be changed along with
698 // the use if required to break an earlier antidep.
699 DEBUG(errs() << " (passthru)\n");
702 // No anti-dep breaking for implicit deps
703 MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
704 assert(AntiDepOp != NULL && "Can't find index for defined register operand");
705 if ((AntiDepOp == NULL) || AntiDepOp->isImplicit()) {
706 DEBUG(errs() << " (implicit)\n");
710 // If the SUnit has other dependencies on the SUnit that
711 // it anti-depends on, don't bother breaking the
712 // anti-dependency since those edges would prevent such
713 // units from being scheduled past each other
715 for (SUnit::pred_iterator P = PathSU->Preds.begin(),
716 PE = PathSU->Preds.end(); P != PE; ++P) {
717 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti)) {
718 DEBUG(errs() << " (real dependency)\n");
724 if (AntiDepReg == 0) continue;
727 assert(AntiDepReg != 0);
728 if (AntiDepReg == 0) continue;
730 // Determine AntiDepReg's register group.
731 const unsigned GroupIndex = State->GetGroup(AntiDepReg);
732 if (GroupIndex == 0) {
733 DEBUG(errs() << " (zero group)\n");
737 DEBUG(errs() << '\n');
739 // Look for a suitable register to use to break the anti-dependence.
740 std::map<unsigned, unsigned> RenameMap;
741 if (FindSuitableFreeRegisters(GroupIndex, RenameMap)) {
742 DEBUG(errs() << "\tBreaking anti-dependence edge on "
743 << TRI->getName(AntiDepReg) << ":");
745 // Handle each group register...
746 for (std::map<unsigned, unsigned>::iterator
747 S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
748 unsigned CurrReg = S->first;
749 unsigned NewReg = S->second;
751 DEBUG(errs() << " " << TRI->getName(CurrReg) << "->" <<
752 TRI->getName(NewReg) << "(" <<
753 RegRefs.count(CurrReg) << " refs)");
755 // Update the references to the old register CurrReg to
756 // refer to the new register NewReg.
757 std::pair<std::multimap<unsigned,
758 AggressiveAntiDepState::RegisterReference>::iterator,
759 std::multimap<unsigned,
760 AggressiveAntiDepState::RegisterReference>::iterator>
761 Range = RegRefs.equal_range(CurrReg);
762 for (std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>::iterator
763 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
764 Q->second.Operand->setReg(NewReg);
767 // We just went back in time and modified history; the
768 // liveness information for CurrReg is now inconsistent. Set
769 // the state as if it were dead.
770 State->UnionGroups(NewReg, 0);
771 RegRefs.erase(NewReg);
772 DefIndices[NewReg] = DefIndices[CurrReg];
773 KillIndices[NewReg] = KillIndices[CurrReg];
775 State->UnionGroups(CurrReg, 0);
776 RegRefs.erase(CurrReg);
777 DefIndices[CurrReg] = KillIndices[CurrReg];
778 KillIndices[CurrReg] = ~0u;
779 assert(((KillIndices[CurrReg] == ~0u) !=
780 (DefIndices[CurrReg] == ~0u)) &&
781 "Kill and Def maps aren't consistent for AntiDepReg!");
785 DEBUG(errs() << '\n');
790 ScanInstruction(MI, Count);