1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
17 #include "llvm/CodeGen/PBQPRAConstraint.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/Support/CodeGen.h"
24 class MachineFunction;
28 class TargetFrameLowering;
29 class TargetInstrInfo;
31 class TargetRegisterClass;
32 class TargetRegisterInfo;
33 class TargetSchedModel;
34 class TargetSelectionDAGInfo;
35 struct MachineSchedPolicy;
36 template <typename T> class SmallVectorImpl;
38 //===----------------------------------------------------------------------===//
40 /// TargetSubtargetInfo - Generic base class for all target subtargets. All
41 /// Target-specific options that control code generation and printing should
42 /// be exposed through a TargetSubtargetInfo-derived class.
44 class TargetSubtargetInfo : public MCSubtargetInfo {
45 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
46 void operator=(const TargetSubtargetInfo &) = delete;
48 protected: // Can only create subclasses...
49 TargetSubtargetInfo();
52 // AntiDepBreakMode - Type of anti-dependence breaking that should
53 // be performed before post-RA scheduling.
54 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
55 typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector;
57 virtual ~TargetSubtargetInfo();
59 // Interfaces to the major aspects of target machine information:
61 // -- Instruction opcode and operand information
62 // -- Pipelines and scheduling information
63 // -- Stack frame information
64 // -- Selection DAG lowering information
66 // N.B. These objects may change during compilation. It's not safe to cache
67 // them between functions.
68 virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
69 virtual const TargetFrameLowering *getFrameLowering() const {
72 virtual const TargetLowering *getTargetLowering() const { return nullptr; }
73 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
77 /// getRegisterInfo - If register information is available, return it. If
78 /// not, return null. This is kept separate from RegInfo until RegInfo has
79 /// details of graph coloring register allocation removed from it.
81 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
83 /// getInstrItineraryData - Returns instruction itinerary data for the target
84 /// or specific subtarget.
86 virtual const InstrItineraryData *getInstrItineraryData() const {
90 /// Resolve a SchedClass at runtime, where SchedClass identifies an
91 /// MCSchedClassDesc with the isVariant property. This may return the ID of
92 /// another variant SchedClass, but repeated invocation must quickly terminate
93 /// in a nonvariant SchedClass.
94 virtual unsigned resolveSchedClass(unsigned SchedClass,
95 const MachineInstr *MI,
96 const TargetSchedModel *SchedModel) const {
100 /// \brief True if the subtarget should run MachineScheduler after aggressive
103 /// This currently replaces the SelectionDAG scheduler with the "source" order
104 /// scheduler (though see below for an option to turn this off and use the
105 /// TargetLowering preference). It does not yet disable the postRA scheduler.
106 virtual bool enableMachineScheduler() const;
108 /// \brief True if the machine scheduler should disable the TLI preference
109 /// for preRA scheduling with the source level scheduler.
110 virtual bool enableMachineSchedDefaultSched() const { return true; }
112 /// \brief True if the subtarget should enable joining global copies.
114 /// By default this is enabled if the machine scheduler is enabled, but
115 /// can be overridden.
116 virtual bool enableJoinGlobalCopies() const;
118 /// True if the subtarget should run a scheduler after register allocation.
120 /// By default this queries the PostRAScheduling bit in the scheduling model
121 /// which is the preferred way to influence this.
122 virtual bool enablePostRAScheduler() const;
124 /// \brief True if the subtarget should run the atomic expansion pass.
125 virtual bool enableAtomicExpand() const;
127 /// \brief Override generic scheduling policy within a region.
129 /// This is a convenient way for targets that don't provide any custom
130 /// scheduling heuristics (no custom MachineSchedStrategy) to make
131 /// changes to the generic scheduling policy.
132 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
133 MachineInstr *begin, MachineInstr *end,
134 unsigned NumRegionInstrs) const {}
136 // \brief Perform target specific adjustments to the latency of a schedule
138 virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
140 // For use with PostRAScheduling: get the anti-dependence breaking that should
141 // be performed before post-RA scheduling.
142 virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
144 // For use with PostRAScheduling: in CriticalPathRCs, return any register
145 // classes that should only be considered for anti-dependence breaking if they
146 // are on the critical path.
147 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
148 return CriticalPathRCs.clear();
151 // For use with PostRAScheduling: get the minimum optimization level needed
152 // to enable post-RA scheduling.
153 virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
154 return CodeGenOpt::Default;
157 /// \brief True if the subtarget should run the local reassignment
158 /// heuristic of the register allocator.
159 /// This heuristic may be compile time intensive, \p OptLevel provides
160 /// a finer grain to tune the register allocator.
161 virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
163 /// \brief Enable use of alias analysis during code generation (during MI
164 /// scheduling, DAGCombine, etc.).
165 virtual bool useAA() const;
167 /// \brief Enable the use of the early if conversion pass.
168 virtual bool enableEarlyIfConversion() const { return false; }
170 /// \brief Return PBQPConstraint(s) for the target.
172 /// Override to provide custom PBQP constraints.
173 virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
177 /// Enable tracking of subregister liveness in register allocator.
178 virtual bool enableSubRegLiveness() const { return false; }
181 } // End llvm namespace