1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
17 #include "llvm/CodeGen/PBQPRAConstraint.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/Support/CodeGen.h"
24 class MachineFunction;
28 class TargetFrameLowering;
29 class TargetInstrInfo;
31 class TargetRegisterClass;
32 class TargetRegisterInfo;
33 class TargetSchedModel;
34 class TargetSelectionDAGInfo;
35 struct MachineSchedPolicy;
36 template <typename T> class SmallVectorImpl;
38 //===----------------------------------------------------------------------===//
40 /// TargetSubtargetInfo - Generic base class for all target subtargets. All
41 /// Target-specific options that control code generation and printing should
42 /// be exposed through a TargetSubtargetInfo-derived class.
44 class TargetSubtargetInfo : public MCSubtargetInfo {
45 TargetSubtargetInfo(const TargetSubtargetInfo&) = delete;
46 void operator=(const TargetSubtargetInfo&) = delete;
47 protected: // Can only create subclasses...
48 TargetSubtargetInfo();
50 // AntiDepBreakMode - Type of anti-dependence breaking that should
51 // be performed before post-RA scheduling.
52 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
53 typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector;
55 virtual ~TargetSubtargetInfo();
57 // Interfaces to the major aspects of target machine information:
59 // -- Instruction opcode and operand information
60 // -- Pipelines and scheduling information
61 // -- Stack frame information
62 // -- Selection DAG lowering information
64 // N.B. These objects may change during compilation. It's not safe to cache
65 // them between functions.
66 virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
67 virtual const TargetFrameLowering *getFrameLowering() const {
70 virtual const TargetLowering *getTargetLowering() const { return nullptr; }
71 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
75 /// getRegisterInfo - If register information is available, return it. If
76 /// not, return null. This is kept separate from RegInfo until RegInfo has
77 /// details of graph coloring register allocation removed from it.
79 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
81 /// getInstrItineraryData - Returns instruction itinerary data for the target
82 /// or specific subtarget.
84 virtual const InstrItineraryData *getInstrItineraryData() const {
88 /// Resolve a SchedClass at runtime, where SchedClass identifies an
89 /// MCSchedClassDesc with the isVariant property. This may return the ID of
90 /// another variant SchedClass, but repeated invocation must quickly terminate
91 /// in a nonvariant SchedClass.
92 virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,
93 const TargetSchedModel* SchedModel) const {
97 /// \brief True if the subtarget should run MachineScheduler after aggressive
100 /// This currently replaces the SelectionDAG scheduler with the "source" order
101 /// scheduler (though see below for an option to turn this off and use the
102 /// TargetLowering preference). It does not yet disable the postRA scheduler.
103 virtual bool enableMachineScheduler() const;
105 /// \brief True if the machine scheduler should disable the TLI preference
106 /// for preRA scheduling with the source level scheduler.
107 virtual bool enableMachineSchedDefaultSched() const { return true; }
109 /// \brief True if the subtarget should enable joining global copies.
111 /// By default this is enabled if the machine scheduler is enabled, but
112 /// can be overridden.
113 virtual bool enableJoinGlobalCopies() const;
115 /// \brief True if the subtarget should run PostMachineScheduler.
117 /// This only takes effect if the target has configured the
118 /// PostMachineScheduler pass to run, or if the global cl::opt flag,
119 /// MISchedPostRA, is set.
120 virtual bool enablePostMachineScheduler() const;
122 /// \brief True if the subtarget should run the atomic expansion pass.
123 virtual bool enableAtomicExpand() const;
125 /// \brief Override generic scheduling policy within a region.
127 /// This is a convenient way for targets that don't provide any custom
128 /// scheduling heuristics (no custom MachineSchedStrategy) to make
129 /// changes to the generic scheduling policy.
130 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
133 unsigned NumRegionInstrs) const {}
135 // \brief Perform target specific adjustments to the latency of a schedule
137 virtual void adjustSchedDependency(SUnit *def, SUnit *use,
140 // For use with PostRAScheduling: get the anti-dependence breaking that should
141 // be performed before post-RA scheduling.
142 virtual AntiDepBreakMode getAntiDepBreakMode() const {
146 // For use with PostRAScheduling: in CriticalPathRCs, return any register
147 // classes that should only be considered for anti-dependence breaking if they
148 // are on the critical path.
149 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
150 return CriticalPathRCs.clear();
153 // For use with PostRAScheduling: get the minimum optimization level needed
154 // to enable post-RA scheduling.
155 virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
156 return CodeGenOpt::Default;
159 /// \brief True if the subtarget should run the local reassignment
160 /// heuristic of the register allocator.
161 /// This heuristic may be compile time intensive, \p OptLevel provides
162 /// a finer grain to tune the register allocator.
163 virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
165 /// \brief Enable use of alias analysis during code generation (during MI
166 /// scheduling, DAGCombine, etc.).
167 virtual bool useAA() const;
169 /// \brief Enable the use of the early if conversion pass.
170 virtual bool enableEarlyIfConversion() const { return false; }
172 /// \brief Return PBQPConstraint(s) for the target.
174 /// Override to provide custom PBQP constraints.
175 virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
179 /// Enable tracking of subregister liveness in register allocator.
180 virtual bool enableSubRegLiveness() const {
185 } // End llvm namespace