1 //===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent scheduling interfaces which should
11 // be implemented by each target which is using TableGen based scheduling.
13 //===----------------------------------------------------------------------===//
15 include "llvm/Target/TargetItinerary.td"
17 // The SchedMachineModel is defined by subtargets for three categories of data:
18 // 1) Basic properties for coarse grained instruction cost model.
19 // 2) Scheduler Read/Write resources for simple per-opcode cost model.
20 // 3) Instruction itineraties for detailed reservation tables.
22 // Default values for basic properties are defined in MCSchedModel. "-1"
23 // indicates that the property is not overriden by the target description.
24 class SchedMachineModel {
25 int IssueWidth = -1; // Max instructions that may be scheduled per cycle.
26 int MinLatency = -1; // Determines which instrucions are allowed in a group.
27 // (-1) inorder (0) ooo, (1): inorder +var latencies.
28 int LoadLatency = -1; // Cycles for loads to access the cache.
29 int HighLatency = -1; // Approximation of cycles for "high latency" ops.
30 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
32 ProcessorItineraries Itineraries = NoItineraries;
34 bit NoModel = 0; // Special tag to indicate missing machine model.
37 def NoSchedModel : SchedMachineModel {
41 // TODO: Define classes for processor and scheduler resources.