1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
31 /// TargetRegisterDesc - This record contains all of the information known about
32 /// a particular register. The AliasSet field (if not null) contains a pointer
33 /// to a Zero terminated array of registers that this register aliases. This is
34 /// needed for architectures like X86 which have AL alias AX alias EAX.
35 /// Registers that this does not apply to simply should set this to null.
36 /// The SubRegs field is a zero terminated array of registers that are
37 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
38 /// The SuperRegs field is a zero terminated array of registers that are
39 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
42 struct TargetRegisterDesc {
43 const char *AsmName; // Assembly language name for the register
44 const char *Name; // Printable name for the reg (for debugging)
45 const unsigned *AliasSet; // Register Alias Set, described above
46 const unsigned *SubRegs; // Sub-register set, described above
47 const unsigned *SuperRegs; // Super-register set, described above
50 class TargetRegisterClass {
52 typedef const unsigned* iterator;
53 typedef const unsigned* const_iterator;
55 typedef const MVT* vt_iterator;
56 typedef const TargetRegisterClass* const * sc_iterator;
60 const vt_iterator VTs;
61 const sc_iterator SubClasses;
62 const sc_iterator SuperClasses;
63 const sc_iterator SubRegClasses;
64 const sc_iterator SuperRegClasses;
65 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
67 const iterator RegsBegin, RegsEnd;
69 TargetRegisterClass(unsigned id,
71 const TargetRegisterClass * const *subcs,
72 const TargetRegisterClass * const *supcs,
73 const TargetRegisterClass * const *subregcs,
74 const TargetRegisterClass * const *superregcs,
75 unsigned RS, unsigned Al, int CC,
76 iterator RB, iterator RE)
77 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
78 SubRegClasses(subregcs), SuperRegClasses(superregcs),
79 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
80 virtual ~TargetRegisterClass() {} // Allow subclasses
82 /// getID() - Return the register class ID number.
84 unsigned getID() const { return ID; }
86 /// begin/end - Return all of the registers in this class.
88 iterator begin() const { return RegsBegin; }
89 iterator end() const { return RegsEnd; }
91 /// getNumRegs - Return the number of registers in this class.
93 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
95 /// getRegister - Return the specified register in the class.
97 unsigned getRegister(unsigned i) const {
98 assert(i < getNumRegs() && "Register number out of range!");
102 /// contains - Return true if the specified register is included in this
104 bool contains(unsigned Reg) const {
105 for (iterator I = begin(), E = end(); I != E; ++I)
106 if (*I == Reg) return true;
110 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
112 bool hasType(MVT vt) const {
113 for(int i = 0; VTs[i] != MVT::Other; ++i)
119 /// vt_begin / vt_end - Loop over all of the value types that can be
120 /// represented by values in this register class.
121 vt_iterator vt_begin() const {
125 vt_iterator vt_end() const {
127 while (*I != MVT::Other) ++I;
131 /// hasSubClass - return true if the specified TargetRegisterClass is a
132 /// sub-register class of this TargetRegisterClass.
133 bool hasSubClass(const TargetRegisterClass *cs) const {
134 for (int i = 0; SubClasses[i] != NULL; ++i)
135 if (SubClasses[i] == cs)
140 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
141 /// this register class.
142 sc_iterator subclasses_begin() const {
146 sc_iterator subclasses_end() const {
147 sc_iterator I = SubClasses;
148 while (*I != NULL) ++I;
152 /// hasSuperClass - return true if the specified TargetRegisterClass is a
153 /// super-register class of this TargetRegisterClass.
154 bool hasSuperClass(const TargetRegisterClass *cs) const {
155 for (int i = 0; SuperClasses[i] != NULL; ++i)
156 if (SuperClasses[i] == cs)
161 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
162 /// of this register class.
163 sc_iterator superclasses_begin() const {
167 sc_iterator superclasses_end() const {
168 sc_iterator I = SuperClasses;
169 while (*I != NULL) ++I;
173 /// subregclasses_begin / subregclasses_end - Loop over all of
174 /// the subregister classes of this register class.
175 sc_iterator subregclasses_begin() const {
176 return SubRegClasses;
179 sc_iterator subregclasses_end() const {
180 sc_iterator I = SubRegClasses;
181 while (*I != NULL) ++I;
185 /// superregclasses_begin / superregclasses_end - Loop over all of
186 /// the superregister classes of this register class.
187 sc_iterator superregclasses_begin() const {
188 return SuperRegClasses;
191 sc_iterator superregclasses_end() const {
192 sc_iterator I = SuperRegClasses;
193 while (*I != NULL) ++I;
197 /// allocation_order_begin/end - These methods define a range of registers
198 /// which specify the registers in this class that are valid to register
199 /// allocate, and the preferred order to allocate them in. For example,
200 /// callee saved registers should be at the end of the list, because it is
201 /// cheaper to allocate caller saved registers.
203 /// These methods take a MachineFunction argument, which can be used to tune
204 /// the allocatable registers based on the characteristics of the function.
205 /// One simple example is that the frame pointer register can be used if
206 /// frame-pointer-elimination is performed.
208 /// By default, these methods return all registers in the class.
210 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
213 virtual iterator allocation_order_end(const MachineFunction &MF) const {
219 /// getSize - Return the size of the register in bytes, which is also the size
220 /// of a stack slot allocated to hold a spilled copy of this register.
221 unsigned getSize() const { return RegSize; }
223 /// getAlignment - Return the minimum required alignment for a register of
225 unsigned getAlignment() const { return Alignment; }
227 /// getCopyCost - Return the cost of copying a value between two registers in
229 int getCopyCost() const { return CopyCost; }
233 /// TargetRegisterInfo base class - We assume that the target defines a static
234 /// array of TargetRegisterDesc objects that represent all of the machine
235 /// registers that the target has. As such, we simply have to track a pointer
236 /// to this array so that we can turn register number into a register
239 class TargetRegisterInfo {
241 const unsigned* SubregHash;
242 const unsigned SubregHashSize;
244 typedef const TargetRegisterClass * const * regclass_iterator;
246 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
247 unsigned NumRegs; // Number of entries in the array
249 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
251 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
253 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
254 regclass_iterator RegClassBegin,
255 regclass_iterator RegClassEnd,
256 int CallFrameSetupOpcode = -1,
257 int CallFrameDestroyOpcode = -1,
258 const unsigned* subregs = 0,
259 const unsigned subregsize = 0);
260 virtual ~TargetRegisterInfo();
263 enum { // Define some target independent constants
264 /// NoRegister - This physical register is not a real target register. It
265 /// is useful as a sentinal.
268 /// FirstVirtualRegister - This is the first register number that is
269 /// considered to be a 'virtual' register, which is part of the SSA
270 /// namespace. This must be the same for all targets, which means that each
271 /// target is limited to 1024 registers.
272 FirstVirtualRegister = 1024
275 /// isPhysicalRegister - Return true if the specified register number is in
276 /// the physical register namespace.
277 static bool isPhysicalRegister(unsigned Reg) {
278 assert(Reg && "this is not a register!");
279 return Reg < FirstVirtualRegister;
282 /// isVirtualRegister - Return true if the specified register number is in
283 /// the virtual register namespace.
284 static bool isVirtualRegister(unsigned Reg) {
285 assert(Reg && "this is not a register!");
286 return Reg >= FirstVirtualRegister;
289 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
290 /// register of the given type. If type is MVT::Other, then just return any
291 /// register class the register belongs to.
292 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
293 MVT VT = MVT::Other) const;
295 /// getAllocatableSet - Returns a bitset indexed by register number
296 /// indicating if a register is allocatable or not. If a register class is
297 /// specified, returns the subset for the class.
298 BitVector getAllocatableSet(MachineFunction &MF,
299 const TargetRegisterClass *RC = NULL) const;
301 const TargetRegisterDesc &operator[](unsigned RegNo) const {
302 assert(RegNo < NumRegs &&
303 "Attempting to access record for invalid register number!");
307 /// Provide a get method, equivalent to [], but more useful if we have a
308 /// pointer to this object.
310 const TargetRegisterDesc &get(unsigned RegNo) const {
311 return operator[](RegNo);
314 /// getAliasSet - Return the set of registers aliased by the specified
315 /// register, or a null list of there are none. The list returned is zero
318 const unsigned *getAliasSet(unsigned RegNo) const {
319 return get(RegNo).AliasSet;
322 /// getSubRegisters - Return the list of registers that are sub-registers of
323 /// the specified register, or a null list of there are none. The list
324 /// returned is zero terminated and sorted according to super-sub register
325 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
327 const unsigned *getSubRegisters(unsigned RegNo) const {
328 return get(RegNo).SubRegs;
331 /// getSuperRegisters - Return the list of registers that are super-registers
332 /// of the specified register, or a null list of there are none. The list
333 /// returned is zero terminated and sorted according to super-sub register
334 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
336 const unsigned *getSuperRegisters(unsigned RegNo) const {
337 return get(RegNo).SuperRegs;
340 /// getAsmName - Return the symbolic target-specific name for the
341 /// specified physical register.
342 const char *getAsmName(unsigned RegNo) const {
343 return get(RegNo).AsmName;
346 /// getName - Return the human-readable symbolic target-specific name for the
347 /// specified physical register.
348 const char *getName(unsigned RegNo) const {
349 return get(RegNo).Name;
352 /// getNumRegs - Return the number of registers this target has (useful for
353 /// sizing arrays holding per register information)
354 unsigned getNumRegs() const {
358 /// areAliases - Returns true if the two registers alias each other, false
360 bool areAliases(unsigned regA, unsigned regB) const {
361 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
362 if (*Alias == regB) return true;
366 /// regsOverlap - Returns true if the two registers are equal or alias each
367 /// other. The registers may be virtual register.
368 bool regsOverlap(unsigned regA, unsigned regB) const {
372 if (isVirtualRegister(regA) || isVirtualRegister(regB))
374 return areAliases(regA, regB);
377 /// isSubRegister - Returns true if regB is a sub-register of regA.
379 bool isSubRegister(unsigned regA, unsigned regB) const {
380 // SubregHash is a simple quadratically probed hash table.
381 size_t index = (regA + regB * 37) & (SubregHashSize-1);
382 unsigned ProbeAmt = 2;
383 while (SubregHash[index*2] != 0 &&
384 SubregHash[index*2+1] != 0) {
385 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
388 index = (index + ProbeAmt) & (SubregHashSize-1);
395 /// isSuperRegister - Returns true if regB is a super-register of regA.
397 bool isSuperRegister(unsigned regA, unsigned regB) const {
398 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
399 if (*SR == regB) return true;
403 /// getCalleeSavedRegs - Return a null-terminated list of all of the
404 /// callee saved registers on this target. The register should be in the
405 /// order of desired callee-save stack frame offset. The first register is
406 /// closed to the incoming stack pointer if stack grows down, and vice versa.
407 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
410 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
411 /// register classes to spill each callee saved register with. The order and
412 /// length of this list match the getCalleeSaveRegs() list.
413 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
414 const MachineFunction *MF) const =0;
416 /// getReservedRegs - Returns a bitset indexed by physical register number
417 /// indicating if a register is a special register that has particular uses
418 /// and should be considered unavailable at all times, e.g. SP, RA. This is
419 /// used by register scavenger to determine what registers are free.
420 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
422 /// getSubReg - Returns the physical register number of sub-register "Index"
423 /// for physical register RegNo. Return zero if the sub-register does not
425 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
427 //===--------------------------------------------------------------------===//
428 // Register Class Information
431 /// Register class iterators
433 regclass_iterator regclass_begin() const { return RegClassBegin; }
434 regclass_iterator regclass_end() const { return RegClassEnd; }
436 unsigned getNumRegClasses() const {
437 return (unsigned)(regclass_end()-regclass_begin());
440 /// getRegClass - Returns the register class associated with the enumeration
441 /// value. See class TargetOperandInfo.
442 const TargetRegisterClass *getRegClass(unsigned i) const {
443 assert(i <= getNumRegClasses() && "Register Class ID out of range");
444 return i ? RegClassBegin[i - 1] : NULL;
447 //===--------------------------------------------------------------------===//
448 // Interfaces used by the register allocator and stack frame
449 // manipulation passes to move data around between registers,
450 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
453 /// getCrossCopyRegClass - Returns a legal register class to copy a register
454 /// in the specified class to or from. Returns NULL if it is possible to copy
455 /// between a two registers of the specified class.
456 virtual const TargetRegisterClass *
457 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
461 /// targetHandlesStackFrameRounding - Returns true if the target is
462 /// responsible for rounding up the stack frame (probably at emitPrologue
464 virtual bool targetHandlesStackFrameRounding() const {
468 /// requiresRegisterScavenging - returns true if the target requires (and can
469 /// make use of) the register scavenger.
470 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
474 /// hasFP - Return true if the specified function should have a dedicated
475 /// frame pointer register. For most targets this is true only if the function
476 /// has variable sized allocas or if frame pointer elimination is disabled.
477 virtual bool hasFP(const MachineFunction &MF) const = 0;
479 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
480 // not required, we reserve argument space for call sites in the function
481 // immediately on entry to the current function. This eliminates the need for
482 // add/sub sp brackets around call sites. Returns true if the call frame is
483 // included as part of the stack frame.
484 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
488 // needsStackRealignment - true if storage within the function requires the
489 // stack pointer to be aligned more than the normal calling convention calls
491 virtual bool needsStackRealignment(const MachineFunction &MF) const {
495 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
496 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
497 /// targets use pseudo instructions in order to abstract away the difference
498 /// between operating with a frame pointer and operating without, through the
499 /// use of these two instructions.
501 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
502 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
505 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
506 /// code insertion to eliminate call frame setup and destroy pseudo
507 /// instructions (but only if the Target is using them). It is responsible
508 /// for eliminating these instructions, replacing them with concrete
509 /// instructions. This method need only be implemented if using call frame
510 /// setup/destroy pseudo instructions.
513 eliminateCallFramePseudoInstr(MachineFunction &MF,
514 MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator MI) const {
516 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
517 "eliminateCallFramePseudoInstr must be implemented if using"
518 " call frame setup/destroy pseudo instructions!");
519 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
522 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
523 /// before PrologEpilogInserter scans the physical registers used to determine
524 /// what callee saved registers should be spilled. This method is optional.
525 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
526 RegScavenger *RS = NULL) const {
530 /// processFunctionBeforeFrameFinalized - This method is called immediately
531 /// before the specified functions frame layout (MF.getFrameInfo()) is
532 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
533 /// replaced with direct constants. This method is optional.
535 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
538 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
539 /// frame indices from instructions which may use them. The instruction
540 /// referenced by the iterator contains an MO_FrameIndex operand which must be
541 /// eliminated by this method. This method may modify or replace the
542 /// specified instruction, as long as it keeps the iterator pointing the the
543 /// finished product. SPAdj is the SP adjustment due to call frame setup
545 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
546 int SPAdj, RegScavenger *RS=NULL) const = 0;
548 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
550 virtual void emitPrologue(MachineFunction &MF) const = 0;
551 virtual void emitEpilogue(MachineFunction &MF,
552 MachineBasicBlock &MBB) const = 0;
554 //===--------------------------------------------------------------------===//
555 /// Debug information queries.
557 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
558 /// number. Returns -1 if there is no equivalent value. The second
559 /// parameter allows targets to use different numberings for EH info and
561 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
563 /// getFrameRegister - This method should return the register used as a base
564 /// for values allocated in the current stack frame.
565 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
567 /// getFrameIndexOffset - Returns the displacement from the frame register to
568 /// the stack frame of the specified index.
569 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
571 /// getRARegister - This method should return the register where the return
572 /// address can be found.
573 virtual unsigned getRARegister() const = 0;
575 /// getInitialFrameState - Returns a list of machine moves that are assumed
576 /// on entry to all functions. Note that LabelID is ignored (assumed to be
577 /// the beginning of the function.)
578 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
581 // This is useful when building IndexedMaps keyed on virtual registers
582 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
583 unsigned operator()(unsigned Reg) const {
584 return Reg - TargetRegisterInfo::FirstVirtualRegister;
588 } // End llvm namespace