1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/CallingConv.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
35 class TargetRegisterClass {
37 typedef const uint16_t* iterator;
38 typedef const uint16_t* const_iterator;
39 typedef const MVT::SimpleValueType* vt_iterator;
40 typedef const TargetRegisterClass* const * sc_iterator;
42 // Instance variables filled by tablegen, do not use!
43 const MCRegisterClass *MC;
44 const vt_iterator VTs;
45 const uint32_t *SubClassMask;
46 const uint16_t *SuperRegIndices;
47 const sc_iterator SuperClasses;
48 ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&);
50 /// getID() - Return the register class ID number.
52 unsigned getID() const { return MC->getID(); }
54 /// getName() - Return the register class name for debugging.
56 const char *getName() const { return MC->getName(); }
58 /// begin/end - Return all of the registers in this class.
60 iterator begin() const { return MC->begin(); }
61 iterator end() const { return MC->end(); }
63 /// getNumRegs - Return the number of registers in this class.
65 unsigned getNumRegs() const { return MC->getNumRegs(); }
67 /// getRegister - Return the specified register in the class.
69 unsigned getRegister(unsigned i) const {
70 return MC->getRegister(i);
73 /// contains - Return true if the specified register is included in this
74 /// register class. This does not include virtual registers.
75 bool contains(unsigned Reg) const {
76 return MC->contains(Reg);
79 /// contains - Return true if both registers are in this class.
80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return MC->contains(Reg1, Reg2);
84 /// getSize - Return the size of the register in bytes, which is also the size
85 /// of a stack slot allocated to hold a spilled copy of this register.
86 unsigned getSize() const { return MC->getSize(); }
88 /// getAlignment - Return the minimum required alignment for a register of
90 unsigned getAlignment() const { return MC->getAlignment(); }
92 /// getCopyCost - Return the cost of copying a value between two registers in
93 /// this class. A negative number means the register class is very expensive
94 /// to copy e.g. status flag register classes.
95 int getCopyCost() const { return MC->getCopyCost(); }
97 /// isAllocatable - Return true if this register class may be used to create
98 /// virtual registers.
99 bool isAllocatable() const { return MC->isAllocatable(); }
101 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
103 bool hasType(EVT vt) const {
104 for(int i = 0; VTs[i] != MVT::Other; ++i)
105 if (EVT(VTs[i]) == vt)
110 /// vt_begin / vt_end - Loop over all of the value types that can be
111 /// represented by values in this register class.
112 vt_iterator vt_begin() const {
116 vt_iterator vt_end() const {
118 while (*I != MVT::Other) ++I;
122 /// hasSubClass - return true if the specified TargetRegisterClass
123 /// is a proper sub-class of this TargetRegisterClass.
124 bool hasSubClass(const TargetRegisterClass *RC) const {
125 return RC != this && hasSubClassEq(RC);
128 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
130 bool hasSubClassEq(const TargetRegisterClass *RC) const {
131 unsigned ID = RC->getID();
132 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
135 /// hasSuperClass - return true if the specified TargetRegisterClass is a
136 /// proper super-class of this TargetRegisterClass.
137 bool hasSuperClass(const TargetRegisterClass *RC) const {
138 return RC->hasSubClass(this);
141 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
144 return RC->hasSubClassEq(this);
147 /// getSubClassMask - Returns a bit vector of subclasses, including this one.
148 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
150 const uint32_t *getSubClassMask() const {
154 /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices
155 /// that projec some super-register class into this register class. The list
156 /// has an entry for each Idx such that:
158 /// There exists SuperRC where:
159 /// For all Reg in SuperRC:
160 /// this->contains(Reg:Idx)
162 const uint16_t *getSuperRegIndices() const {
163 return SuperRegIndices;
166 /// getSuperClasses - Returns a NULL terminated list of super-classes. The
167 /// classes are ordered by ID which is also a topological ordering from large
168 /// to small classes. The list does NOT include the current class.
169 sc_iterator getSuperClasses() const {
173 /// isASubClass - return true if this TargetRegisterClass is a subset
174 /// class of at least one other TargetRegisterClass.
175 bool isASubClass() const {
176 return SuperClasses[0] != 0;
179 /// getRawAllocationOrder - Returns the preferred order for allocating
180 /// registers from this register class in MF. The raw order comes directly
181 /// from the .td file and may include reserved registers that are not
182 /// allocatable. Register allocators should also make sure to allocate
183 /// callee-saved registers only after all the volatiles are used. The
184 /// RegisterClassInfo class provides filtered allocation orders with
185 /// callee-saved registers moved to the end.
187 /// The MachineFunction argument can be used to tune the allocatable
188 /// registers based on the characteristics of the function, subtarget, or
191 /// By default, this method returns all registers in the class.
193 ArrayRef<uint16_t> getRawAllocationOrder(const MachineFunction &MF) const {
194 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
198 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
199 /// registers. These are used by codegen, not by MC.
200 struct TargetRegisterInfoDesc {
201 unsigned CostPerUse; // Extra cost of instructions using register.
202 bool inAllocatableClass; // Register belongs to an allocatable regclass.
205 /// Each TargetRegisterClass has a per register weight, and weight
206 /// limit which must be less than the limits of its pressure sets.
207 struct RegClassWeight {
209 unsigned WeightLimit;
212 /// TargetRegisterInfo base class - We assume that the target defines a static
213 /// array of TargetRegisterDesc objects that represent all of the machine
214 /// registers that the target has. As such, we simply have to track a pointer
215 /// to this array so that we can turn register number into a register
218 class TargetRegisterInfo : public MCRegisterInfo {
220 typedef const TargetRegisterClass * const * regclass_iterator;
222 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
223 const char *const *SubRegIndexNames; // Names of subreg indexes.
224 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
227 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
228 regclass_iterator RegClassBegin,
229 regclass_iterator RegClassEnd,
230 const char *const *subregindexnames);
231 virtual ~TargetRegisterInfo();
234 // Register numbers can represent physical registers, virtual registers, and
235 // sometimes stack slots. The unsigned values are divided into these ranges:
237 // 0 Not a register, can be used as a sentinel.
238 // [1;2^30) Physical registers assigned by TableGen.
239 // [2^30;2^31) Stack slots. (Rarely used.)
240 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
242 // Further sentinels can be allocated from the small negative integers.
243 // DenseMapInfo<unsigned> uses -1u and -2u.
245 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
246 /// frame index in a variable that normally holds a register. isStackSlot()
247 /// returns true if Reg is in the range used for stack slots.
249 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
250 /// slots, so if a variable may contains a stack slot, always check
251 /// isStackSlot() first.
253 static bool isStackSlot(unsigned Reg) {
254 return int(Reg) >= (1 << 30);
257 /// stackSlot2Index - Compute the frame index from a register value
258 /// representing a stack slot.
259 static int stackSlot2Index(unsigned Reg) {
260 assert(isStackSlot(Reg) && "Not a stack slot");
261 return int(Reg - (1u << 30));
264 /// index2StackSlot - Convert a non-negative frame index to a stack slot
266 static unsigned index2StackSlot(int FI) {
267 assert(FI >= 0 && "Cannot hold a negative frame index.");
268 return FI + (1u << 30);
271 /// isPhysicalRegister - Return true if the specified register number is in
272 /// the physical register namespace.
273 static bool isPhysicalRegister(unsigned Reg) {
274 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
278 /// isVirtualRegister - Return true if the specified register number is in
279 /// the virtual register namespace.
280 static bool isVirtualRegister(unsigned Reg) {
281 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
285 /// virtReg2Index - Convert a virtual register number to a 0-based index.
286 /// The first virtual register in a function will get the index 0.
287 static unsigned virtReg2Index(unsigned Reg) {
288 assert(isVirtualRegister(Reg) && "Not a virtual register");
289 return Reg & ~(1u << 31);
292 /// index2VirtReg - Convert a 0-based index to a virtual register number.
293 /// This is the inverse operation of VirtReg2IndexFunctor below.
294 static unsigned index2VirtReg(unsigned Index) {
295 return Index | (1u << 31);
298 /// getMinimalPhysRegClass - Returns the Register Class of a physical
299 /// register of the given type, picking the most sub register class of
300 /// the right type that contains this physreg.
301 const TargetRegisterClass *
302 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
304 /// getAllocatableClass - Return the maximal subclass of the given register
305 /// class that is alloctable, or NULL.
306 const TargetRegisterClass *
307 getAllocatableClass(const TargetRegisterClass *RC) const;
309 /// getAllocatableSet - Returns a bitset indexed by register number
310 /// indicating if a register is allocatable or not. If a register class is
311 /// specified, returns the subset for the class.
312 BitVector getAllocatableSet(const MachineFunction &MF,
313 const TargetRegisterClass *RC = NULL) const;
315 /// getCostPerUse - Return the additional cost of using this register instead
316 /// of other registers in its class.
317 unsigned getCostPerUse(unsigned RegNo) const {
318 return InfoDesc[RegNo].CostPerUse;
321 /// isInAllocatableClass - Return true if the register is in the allocation
322 /// of any register class.
323 bool isInAllocatableClass(unsigned RegNo) const {
324 return InfoDesc[RegNo].inAllocatableClass;
327 /// getSubRegIndexName - Return the human-readable symbolic target-specific
328 /// name for the specified SubRegIndex.
329 const char *getSubRegIndexName(unsigned SubIdx) const {
330 assert(SubIdx && "This is not a subregister index");
331 return SubRegIndexNames[SubIdx-1];
334 /// regsOverlap - Returns true if the two registers are equal or alias each
335 /// other. The registers may be virtual register.
336 bool regsOverlap(unsigned regA, unsigned regB) const {
337 if (regA == regB) return true;
338 if (isVirtualRegister(regA) || isVirtualRegister(regB))
341 // Regunits are numerically ordered. Find a common unit.
342 MCRegUnitIterator RUA(regA, this);
343 MCRegUnitIterator RUB(regB, this);
345 if (*RUA == *RUB) return true;
346 if (*RUA < *RUB) ++RUA;
348 } while (RUA.isValid() && RUB.isValid());
352 /// isSubRegister - Returns true if regB is a sub-register of regA.
354 bool isSubRegister(unsigned regA, unsigned regB) const {
355 return isSuperRegister(regB, regA);
358 /// isSuperRegister - Returns true if regB is a super-register of regA.
360 bool isSuperRegister(unsigned RegA, unsigned RegB) const {
361 for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
367 /// getCalleeSavedRegs - Return a null-terminated list of all of the
368 /// callee saved registers on this target. The register should be in the
369 /// order of desired callee-save stack frame offset. The first register is
370 /// closest to the incoming stack pointer if stack grows down, and vice versa.
372 virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF = 0)
375 /// getCallPreservedMask - Return a mask of call-preserved registers for the
376 /// given calling convention on the current sub-target. The mask should
377 /// include all call-preserved aliases. This is used by the register
378 /// allocator to determine which registers can be live across a call.
380 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
381 /// A set bit indicates that all bits of the corresponding register are
382 /// preserved across the function call. The bit mask is expected to be
383 /// sub-register complete, i.e. if A is preserved, so are all its
386 /// Bits are numbered from the LSB, so the bit for physical register Reg can
387 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
389 /// A NULL pointer means that no register mask will be used, and call
390 /// instructions should use implicit-def operands to indicate call clobbered
393 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
394 // The default mask clobbers everything. All targets should override.
398 /// getReservedRegs - Returns a bitset indexed by physical register number
399 /// indicating if a register is a special register that has particular uses
400 /// and should be considered unavailable at all times, e.g. SP, RA. This is
401 /// used by register scavenger to determine what registers are free.
402 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
404 /// getMatchingSuperReg - Return a super-register of the specified register
405 /// Reg so its sub-register of index SubIdx is Reg.
406 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
407 const TargetRegisterClass *RC) const {
408 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
411 /// canCombineSubRegIndices - Given a register class and a list of
412 /// subregister indices, return true if it's possible to combine the
413 /// subregister indices into one that corresponds to a larger
414 /// subregister. Return the new subregister index by reference. Note the
415 /// new index may be zero if the given subregisters can be combined to
416 /// form the whole register.
417 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
418 SmallVectorImpl<unsigned> &SubIndices,
419 unsigned &NewSubIdx) const {
423 /// getMatchingSuperRegClass - Return a subclass of the specified register
424 /// class A so that each register in it has a sub-register of the
425 /// specified sub-register index which is in the specified register class B.
427 /// TableGen will synthesize missing A sub-classes.
428 virtual const TargetRegisterClass *
429 getMatchingSuperRegClass(const TargetRegisterClass *A,
430 const TargetRegisterClass *B, unsigned Idx) const;
432 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
433 /// supports the sub-register index Idx.
434 /// If no such sub-class exists, return NULL.
435 /// If all registers in RC already have an Idx sub-register, return RC.
437 /// TableGen generates a version of this function that is good enough in most
438 /// cases. Targets can override if they have constraints that TableGen
439 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
440 /// supported by the full GR32 register class in 64-bit mode, but only by the
441 /// GR32_ABCD regiister class in 32-bit mode.
443 /// TableGen will synthesize missing RC sub-classes.
444 virtual const TargetRegisterClass *
445 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
446 assert(Idx == 0 && "Target has no sub-registers");
450 /// composeSubRegIndices - Return the subregister index you get from composing
451 /// two subregister indices.
453 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
454 /// returns c. Note that composeSubRegIndices does not tell you about illegal
455 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
456 /// b, composeSubRegIndices doesn't tell you.
458 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
459 /// ssub_0:S0 - ssub_3:S3 subregs.
460 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
462 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
463 // This default implementation is correct for most targets.
467 /// getCommonSuperRegClass - Find a common super-register class if it exists.
469 /// Find a register class, SuperRC and two sub-register indices, PreA and
472 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
474 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
476 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
478 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
479 /// requirements, and there is no register class with a smaller spill size
480 /// that satisfies the requirements.
482 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
484 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
485 /// that case, the returned register class will be a sub-class of the
486 /// corresponding argument register class.
488 /// The function returns NULL if no register class can be found.
490 const TargetRegisterClass*
491 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
492 const TargetRegisterClass *RCB, unsigned SubB,
493 unsigned &PreA, unsigned &PreB) const;
495 //===--------------------------------------------------------------------===//
496 // Register Class Information
499 /// Register class iterators
501 regclass_iterator regclass_begin() const { return RegClassBegin; }
502 regclass_iterator regclass_end() const { return RegClassEnd; }
504 unsigned getNumRegClasses() const {
505 return (unsigned)(regclass_end()-regclass_begin());
508 /// getRegClass - Returns the register class associated with the enumeration
509 /// value. See class MCOperandInfo.
510 const TargetRegisterClass *getRegClass(unsigned i) const {
511 assert(i < getNumRegClasses() && "Register Class ID out of range");
512 return RegClassBegin[i];
515 /// getCommonSubClass - find the largest common subclass of A and B. Return
516 /// NULL if there is no common subclass.
517 const TargetRegisterClass *
518 getCommonSubClass(const TargetRegisterClass *A,
519 const TargetRegisterClass *B) const;
521 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
522 /// values. If a target supports multiple different pointer register classes,
523 /// kind specifies which one is indicated.
524 virtual const TargetRegisterClass *
525 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
526 llvm_unreachable("Target didn't implement getPointerRegClass!");
529 /// getCrossCopyRegClass - Returns a legal register class to copy a register
530 /// in the specified class to or from. If it is possible to copy the register
531 /// directly without using a cross register class copy, return the specified
532 /// RC. Returns NULL if it is not possible to copy between a two registers of
533 /// the specified class.
534 virtual const TargetRegisterClass *
535 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
539 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
540 /// legal to use in the current sub-target and has the same spill size.
541 /// The returned register class can be used to create virtual registers which
542 /// means that all its registers can be copied and spilled.
543 virtual const TargetRegisterClass*
544 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
545 /// The default implementation is very conservative and doesn't allow the
546 /// register allocator to inflate register classes.
550 /// getRegPressureLimit - Return the register pressure "high water mark" for
551 /// the specific register class. The scheduler is in high register pressure
552 /// mode (for the specific register class) if it goes over the limit.
554 /// Note: this is the old register pressure model that relies on a manually
555 /// specified representative register class per value type.
556 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
557 MachineFunction &MF) const {
561 // Get the weight in units of pressure for this register class.
562 virtual const RegClassWeight &getRegClassWeight(
563 const TargetRegisterClass *RC) const = 0;
565 /// Get the number of dimensions of register pressure.
566 virtual unsigned getNumRegPressureSets() const = 0;
568 /// Get the name of this register unit pressure set.
569 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
571 /// Get the register unit pressure limit for this dimension.
572 /// This limit must be adjusted dynamically for reserved registers.
573 virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0;
575 /// Get the dimensions of register pressure impacted by this register class.
576 /// Returns a -1 terminated array of pressure set IDs.
577 virtual const int *getRegClassPressureSets(
578 const TargetRegisterClass *RC) const = 0;
580 /// getRawAllocationOrder - Returns the register allocation order for a
581 /// specified register class with a target-dependent hint. The returned list
582 /// may contain reserved registers that cannot be allocated.
584 /// Register allocators need only call this function to resolve
585 /// target-dependent hints, but it should work without hinting as well.
586 virtual ArrayRef<uint16_t>
587 getRawAllocationOrder(const TargetRegisterClass *RC,
588 unsigned HintType, unsigned HintReg,
589 const MachineFunction &MF) const {
590 return RC->getRawAllocationOrder(MF);
593 /// ResolveRegAllocHint - Resolves the specified register allocation hint
594 /// to a physical register. Returns the physical register if it is successful.
595 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
596 const MachineFunction &MF) const {
597 if (Type == 0 && Reg && isPhysicalRegister(Reg))
602 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
603 /// writing a register from RC in two consecutive instructions.
604 /// This can avoid pipeline stalls on certain architectures.
605 /// It does cause increased register pressure, though.
606 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
610 /// UpdateRegAllocHint - A callback to allow target a chance to update
611 /// register allocation hints when a register is "changed" (e.g. coalesced)
612 /// to another register. e.g. On ARM, some virtual registers should target
613 /// register pairs, if one of pair is coalesced to another register, the
614 /// allocation hint of the other half of the pair should be changed to point
615 /// to the new register.
616 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
617 MachineFunction &MF) const {
621 /// requiresRegisterScavenging - returns true if the target requires (and can
622 /// make use of) the register scavenger.
623 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
627 /// useFPForScavengingIndex - returns true if the target wants to use
628 /// frame pointer based accesses to spill to the scavenger emergency spill
630 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
634 /// requiresFrameIndexScavenging - returns true if the target requires post
635 /// PEI scavenging of registers for materializing frame index constants.
636 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
640 /// requiresVirtualBaseRegisters - Returns true if the target wants the
641 /// LocalStackAllocation pass to be run and virtual base registers
642 /// used for more efficient stack access.
643 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
647 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
648 /// the stack frame of the given function for the specified register. e.g. On
649 /// x86, if the frame register is required, the first fixed stack object is
650 /// reserved as its spill slot. This tells PEI not to create a new stack frame
651 /// object for the given register. It should be called only after
652 /// processFunctionBeforeCalleeSavedScan().
653 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
654 int &FrameIdx) const {
658 /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked
659 /// after register allocation.
660 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
664 /// needsStackRealignment - true if storage within the function requires the
665 /// stack pointer to be aligned more than the normal calling convention calls
667 virtual bool needsStackRealignment(const MachineFunction &MF) const {
671 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
672 /// index in the instruction, if there is one.
673 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
678 /// needsFrameBaseReg - Returns true if the instruction's frame index
679 /// reference would be better served by a base register other than FP
680 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
681 /// references it should create new base registers for.
682 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
686 /// materializeFrameBaseRegister - Insert defining instruction(s) for
687 /// BaseReg to be a pointer to FrameIdx before insertion point I.
688 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
689 unsigned BaseReg, int FrameIdx,
690 int64_t Offset) const {
691 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
695 /// resolveFrameIndex - Resolve a frame index operand of an instruction
696 /// to reference the indicated base register plus offset instead.
697 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
698 unsigned BaseReg, int64_t Offset) const {
699 llvm_unreachable("resolveFrameIndex does not exist on this target");
702 /// isFrameOffsetLegal - Determine whether a given offset immediate is
703 /// encodable to resolve a frame index.
704 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
705 int64_t Offset) const {
706 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
709 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
710 /// code insertion to eliminate call frame setup and destroy pseudo
711 /// instructions (but only if the Target is using them). It is responsible
712 /// for eliminating these instructions, replacing them with concrete
713 /// instructions. This method need only be implemented if using call frame
714 /// setup/destroy pseudo instructions.
717 eliminateCallFramePseudoInstr(MachineFunction &MF,
718 MachineBasicBlock &MBB,
719 MachineBasicBlock::iterator MI) const {
720 llvm_unreachable("Call Frame Pseudo Instructions do not exist on this "
725 /// saveScavengerRegister - Spill the register so it can be used by the
726 /// register scavenger. Return true if the register was spilled, false
727 /// otherwise. If this function does not spill the register, the scavenger
728 /// will instead spill it to the emergency spill slot.
730 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
731 MachineBasicBlock::iterator I,
732 MachineBasicBlock::iterator &UseMI,
733 const TargetRegisterClass *RC,
734 unsigned Reg) const {
738 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
739 /// frame indices from instructions which may use them. The instruction
740 /// referenced by the iterator contains an MO_FrameIndex operand which must be
741 /// eliminated by this method. This method may modify or replace the
742 /// specified instruction, as long as it keeps the iterator pointing at the
743 /// finished product. SPAdj is the SP adjustment due to call frame setup
745 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
746 int SPAdj, RegScavenger *RS=NULL) const = 0;
748 //===--------------------------------------------------------------------===//
749 /// Debug information queries.
751 /// getFrameRegister - This method should return the register used as a base
752 /// for values allocated in the current stack frame.
753 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
755 /// getCompactUnwindRegNum - This function maps the register to the number for
756 /// compact unwind encoding. Return -1 if the register isn't valid.
757 virtual int getCompactUnwindRegNum(unsigned, bool) const {
763 //===----------------------------------------------------------------------===//
764 // SuperRegClassIterator
765 //===----------------------------------------------------------------------===//
767 // Iterate over the possible super-registers for a given register class. The
768 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
769 // possible classes of super-registers.
771 // Each bit mask will have at least one set bit, and each set bit in Mask
772 // corresponds to a SuperRC such that:
774 // For all Reg in SuperRC: Reg:Idx is in RC.
776 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
777 // also satisfies the above requirement, assuming Reg:0 == Reg.
779 class SuperRegClassIterator {
780 const unsigned RCMaskWords;
783 const uint32_t *Mask;
786 /// Create a SuperRegClassIterator that visits all the super-register classes
787 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
788 SuperRegClassIterator(const TargetRegisterClass *RC,
789 const TargetRegisterInfo *TRI,
790 bool IncludeSelf = false)
791 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
793 Idx(RC->getSuperRegIndices()),
794 Mask(RC->getSubClassMask()) {
799 /// Returns true if this iterator is still pointing at a valid entry.
800 bool isValid() const { return Idx; }
802 /// Returns the current sub-register index.
803 unsigned getSubReg() const { return SubReg; }
805 /// Returns the bit mask if register classes that getSubReg() projects into
807 const uint32_t *getMask() const { return Mask; }
809 /// Advance iterator to the next entry.
811 assert(isValid() && "Cannot move iterator past end.");
819 // This is useful when building IndexedMaps keyed on virtual registers
820 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
821 unsigned operator()(unsigned Reg) const {
822 return TargetRegisterInfo::virtReg2Index(Reg);
826 /// PrintReg - Helper class for printing registers on a raw_ostream.
827 /// Prints virtual and physical registers with or without a TRI instance.
830 /// %noreg - NoRegister
831 /// %vreg5 - a virtual register.
832 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
833 /// %EAX - a physical register
834 /// %physreg17 - a physical register when no TRI instance given.
836 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
839 const TargetRegisterInfo *TRI;
843 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
844 : TRI(tri), Reg(reg), SubIdx(subidx) {}
845 void print(raw_ostream&) const;
848 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
853 } // End llvm namespace