1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
31 /// TargetRegisterDesc - This record contains all of the information known about
32 /// a particular register. The AliasSet field (if not null) contains a pointer
33 /// to a Zero terminated array of registers that this register aliases. This is
34 /// needed for architectures like X86 which have AL alias AX alias EAX.
35 /// Registers that this does not apply to simply should set this to null.
36 /// The SubRegs field is a zero terminated array of registers that are
37 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
38 /// The SuperRegs field is a zero terminated array of registers that are
39 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
42 struct TargetRegisterDesc {
43 const char *AsmName; // Assembly language name for the register
44 const char *Name; // Printable name for the reg (for debugging)
45 const unsigned *AliasSet; // Register Alias Set, described above
46 const unsigned *SubRegs; // Sub-register set, described above
47 const unsigned *SuperRegs; // Super-register set, described above
50 class TargetRegisterClass {
52 typedef const unsigned* iterator;
53 typedef const unsigned* const_iterator;
55 typedef const MVT* vt_iterator;
56 typedef const TargetRegisterClass* const * sc_iterator;
60 const vt_iterator VTs;
61 const sc_iterator SubClasses;
62 const sc_iterator SuperClasses;
63 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
65 const iterator RegsBegin, RegsEnd;
67 TargetRegisterClass(unsigned id,
69 const TargetRegisterClass * const *subcs,
70 const TargetRegisterClass * const *supcs,
71 unsigned RS, unsigned Al, int CC,
72 iterator RB, iterator RE)
73 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
74 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
75 virtual ~TargetRegisterClass() {} // Allow subclasses
77 /// getID() - Return the register class ID number.
79 unsigned getID() const { return ID; }
81 /// begin/end - Return all of the registers in this class.
83 iterator begin() const { return RegsBegin; }
84 iterator end() const { return RegsEnd; }
86 /// getNumRegs - Return the number of registers in this class.
88 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
90 /// getRegister - Return the specified register in the class.
92 unsigned getRegister(unsigned i) const {
93 assert(i < getNumRegs() && "Register number out of range!");
97 /// contains - Return true if the specified register is included in this
99 bool contains(unsigned Reg) const {
100 for (iterator I = begin(), E = end(); I != E; ++I)
101 if (*I == Reg) return true;
105 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
107 bool hasType(MVT vt) const {
108 for(int i = 0; VTs[i] != MVT::Other; ++i)
114 /// vt_begin / vt_end - Loop over all of the value types that can be
115 /// represented by values in this register class.
116 vt_iterator vt_begin() const {
120 vt_iterator vt_end() const {
122 while (*I != MVT::Other) ++I;
126 /// hasSubClass - return true if the specified TargetRegisterClass is a
127 /// sub-register class of this TargetRegisterClass.
128 bool hasSubClass(const TargetRegisterClass *cs) const {
129 for (int i = 0; SubClasses[i] != NULL; ++i)
130 if (SubClasses[i] == cs)
135 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
136 /// this register class.
137 sc_iterator subclasses_begin() const {
141 sc_iterator subclasses_end() const {
142 sc_iterator I = SubClasses;
143 while (*I != NULL) ++I;
147 /// hasSuperClass - return true if the specified TargetRegisterClass is a
148 /// super-register class of this TargetRegisterClass.
149 bool hasSuperClass(const TargetRegisterClass *cs) const {
150 for (int i = 0; SuperClasses[i] != NULL; ++i)
151 if (SuperClasses[i] == cs)
156 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
157 /// of this register class.
158 sc_iterator superclasses_begin() const {
162 sc_iterator superclasses_end() const {
163 sc_iterator I = SuperClasses;
164 while (*I != NULL) ++I;
168 /// isASubClass - return true if this TargetRegisterClass is a sub-class of at
169 /// least one other TargetRegisterClass.
170 bool isASubClass() const {
171 return SuperClasses[0] != 0;
174 /// allocation_order_begin/end - These methods define a range of registers
175 /// which specify the registers in this class that are valid to register
176 /// allocate, and the preferred order to allocate them in. For example,
177 /// callee saved registers should be at the end of the list, because it is
178 /// cheaper to allocate caller saved registers.
180 /// These methods take a MachineFunction argument, which can be used to tune
181 /// the allocatable registers based on the characteristics of the function.
182 /// One simple example is that the frame pointer register can be used if
183 /// frame-pointer-elimination is performed.
185 /// By default, these methods return all registers in the class.
187 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
190 virtual iterator allocation_order_end(const MachineFunction &MF) const {
196 /// getSize - Return the size of the register in bytes, which is also the size
197 /// of a stack slot allocated to hold a spilled copy of this register.
198 unsigned getSize() const { return RegSize; }
200 /// getAlignment - Return the minimum required alignment for a register of
202 unsigned getAlignment() const { return Alignment; }
204 /// getCopyCost - Return the cost of copying a value between two registers in
205 /// this class. A negative number means the register class is very expensive
206 /// to copy e.g. status flag register classes.
207 int getCopyCost() const { return CopyCost; }
211 /// TargetRegisterInfo base class - We assume that the target defines a static
212 /// array of TargetRegisterDesc objects that represent all of the machine
213 /// registers that the target has. As such, we simply have to track a pointer
214 /// to this array so that we can turn register number into a register
217 class TargetRegisterInfo {
219 const unsigned* SubregHash;
220 const unsigned SubregHashSize;
222 typedef const TargetRegisterClass * const * regclass_iterator;
224 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
225 unsigned NumRegs; // Number of entries in the array
227 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
229 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
231 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
232 regclass_iterator RegClassBegin,
233 regclass_iterator RegClassEnd,
234 int CallFrameSetupOpcode = -1,
235 int CallFrameDestroyOpcode = -1,
236 const unsigned* subregs = 0,
237 const unsigned subregsize = 0);
238 virtual ~TargetRegisterInfo();
241 enum { // Define some target independent constants
242 /// NoRegister - This physical register is not a real target register. It
243 /// is useful as a sentinal.
246 /// FirstVirtualRegister - This is the first register number that is
247 /// considered to be a 'virtual' register, which is part of the SSA
248 /// namespace. This must be the same for all targets, which means that each
249 /// target is limited to 1024 registers.
250 FirstVirtualRegister = 1024
253 /// isPhysicalRegister - Return true if the specified register number is in
254 /// the physical register namespace.
255 static bool isPhysicalRegister(unsigned Reg) {
256 assert(Reg && "this is not a register!");
257 return Reg < FirstVirtualRegister;
260 /// isVirtualRegister - Return true if the specified register number is in
261 /// the virtual register namespace.
262 static bool isVirtualRegister(unsigned Reg) {
263 assert(Reg && "this is not a register!");
264 return Reg >= FirstVirtualRegister;
267 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
268 /// register of the given type. If type is MVT::Other, then just return any
269 /// register class the register belongs to.
270 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
271 MVT VT = MVT::Other) const;
273 /// getAllocatableSet - Returns a bitset indexed by register number
274 /// indicating if a register is allocatable or not. If a register class is
275 /// specified, returns the subset for the class.
276 BitVector getAllocatableSet(MachineFunction &MF,
277 const TargetRegisterClass *RC = NULL) const;
279 const TargetRegisterDesc &operator[](unsigned RegNo) const {
280 assert(RegNo < NumRegs &&
281 "Attempting to access record for invalid register number!");
285 /// Provide a get method, equivalent to [], but more useful if we have a
286 /// pointer to this object.
288 const TargetRegisterDesc &get(unsigned RegNo) const {
289 return operator[](RegNo);
292 /// getAliasSet - Return the set of registers aliased by the specified
293 /// register, or a null list of there are none. The list returned is zero
296 const unsigned *getAliasSet(unsigned RegNo) const {
297 return get(RegNo).AliasSet;
300 /// getSubRegisters - Return the list of registers that are sub-registers of
301 /// the specified register, or a null list of there are none. The list
302 /// returned is zero terminated and sorted according to super-sub register
303 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
305 const unsigned *getSubRegisters(unsigned RegNo) const {
306 return get(RegNo).SubRegs;
309 /// getSuperRegisters - Return the list of registers that are super-registers
310 /// of the specified register, or a null list of there are none. The list
311 /// returned is zero terminated and sorted according to super-sub register
312 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
314 const unsigned *getSuperRegisters(unsigned RegNo) const {
315 return get(RegNo).SuperRegs;
318 /// getAsmName - Return the symbolic target-specific name for the
319 /// specified physical register.
320 const char *getAsmName(unsigned RegNo) const {
321 return get(RegNo).AsmName;
324 /// getName - Return the human-readable symbolic target-specific name for the
325 /// specified physical register.
326 const char *getName(unsigned RegNo) const {
327 return get(RegNo).Name;
330 /// getNumRegs - Return the number of registers this target has (useful for
331 /// sizing arrays holding per register information)
332 unsigned getNumRegs() const {
336 /// areAliases - Returns true if the two registers alias each other, false
338 bool areAliases(unsigned regA, unsigned regB) const {
339 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
340 if (*Alias == regB) return true;
344 /// regsOverlap - Returns true if the two registers are equal or alias each
345 /// other. The registers may be virtual register.
346 bool regsOverlap(unsigned regA, unsigned regB) const {
350 if (isVirtualRegister(regA) || isVirtualRegister(regB))
352 return areAliases(regA, regB);
355 /// isSubRegister - Returns true if regB is a sub-register of regA.
357 bool isSubRegister(unsigned regA, unsigned regB) const {
358 // SubregHash is a simple quadratically probed hash table.
359 size_t index = (regA + regB * 37) & (SubregHashSize-1);
360 unsigned ProbeAmt = 2;
361 while (SubregHash[index*2] != 0 &&
362 SubregHash[index*2+1] != 0) {
363 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
366 index = (index + ProbeAmt) & (SubregHashSize-1);
373 /// isSuperRegister - Returns true if regB is a super-register of regA.
375 bool isSuperRegister(unsigned regA, unsigned regB) const {
376 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
377 if (*SR == regB) return true;
381 /// getCalleeSavedRegs - Return a null-terminated list of all of the
382 /// callee saved registers on this target. The register should be in the
383 /// order of desired callee-save stack frame offset. The first register is
384 /// closed to the incoming stack pointer if stack grows down, and vice versa.
385 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
388 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
389 /// register classes to spill each callee saved register with. The order and
390 /// length of this list match the getCalleeSaveRegs() list.
391 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
392 const MachineFunction *MF) const =0;
394 /// getReservedRegs - Returns a bitset indexed by physical register number
395 /// indicating if a register is a special register that has particular uses
396 /// and should be considered unavailable at all times, e.g. SP, RA. This is
397 /// used by register scavenger to determine what registers are free.
398 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
400 /// getSubReg - Returns the physical register number of sub-register "Index"
401 /// for physical register RegNo. Return zero if the sub-register does not
403 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
405 //===--------------------------------------------------------------------===//
406 // Register Class Information
409 /// Register class iterators
411 regclass_iterator regclass_begin() const { return RegClassBegin; }
412 regclass_iterator regclass_end() const { return RegClassEnd; }
414 unsigned getNumRegClasses() const {
415 return (unsigned)(regclass_end()-regclass_begin());
418 /// getRegClass - Returns the register class associated with the enumeration
419 /// value. See class TargetOperandInfo.
420 const TargetRegisterClass *getRegClass(unsigned i) const {
421 assert(i <= getNumRegClasses() && "Register Class ID out of range");
422 return i ? RegClassBegin[i - 1] : NULL;
425 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
427 virtual const TargetRegisterClass *getPointerRegClass() const {
428 assert(0 && "Target didn't implement getPointerRegClass!");
430 return 0; // Must return a value in order to compile with VS 2005
433 /// getCrossCopyRegClass - Returns a legal register class to copy a register
434 /// in the specified class to or from. Returns NULL if it is possible to copy
435 /// between a two registers of the specified class.
436 virtual const TargetRegisterClass *
437 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
441 /// targetHandlesStackFrameRounding - Returns true if the target is
442 /// responsible for rounding up the stack frame (probably at emitPrologue
444 virtual bool targetHandlesStackFrameRounding() const {
448 /// requiresRegisterScavenging - returns true if the target requires (and can
449 /// make use of) the register scavenger.
450 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
454 /// hasFP - Return true if the specified function should have a dedicated
455 /// frame pointer register. For most targets this is true only if the function
456 /// has variable sized allocas or if frame pointer elimination is disabled.
457 virtual bool hasFP(const MachineFunction &MF) const = 0;
459 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
460 // not required, we reserve argument space for call sites in the function
461 // immediately on entry to the current function. This eliminates the need for
462 // add/sub sp brackets around call sites. Returns true if the call frame is
463 // included as part of the stack frame.
464 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
468 // needsStackRealignment - true if storage within the function requires the
469 // stack pointer to be aligned more than the normal calling convention calls
471 virtual bool needsStackRealignment(const MachineFunction &MF) const {
475 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
476 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
477 /// targets use pseudo instructions in order to abstract away the difference
478 /// between operating with a frame pointer and operating without, through the
479 /// use of these two instructions.
481 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
482 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
484 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
485 /// code insertion to eliminate call frame setup and destroy pseudo
486 /// instructions (but only if the Target is using them). It is responsible
487 /// for eliminating these instructions, replacing them with concrete
488 /// instructions. This method need only be implemented if using call frame
489 /// setup/destroy pseudo instructions.
492 eliminateCallFramePseudoInstr(MachineFunction &MF,
493 MachineBasicBlock &MBB,
494 MachineBasicBlock::iterator MI) const {
495 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
496 "eliminateCallFramePseudoInstr must be implemented if using"
497 " call frame setup/destroy pseudo instructions!");
498 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
501 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
502 /// before PrologEpilogInserter scans the physical registers used to determine
503 /// what callee saved registers should be spilled. This method is optional.
504 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
505 RegScavenger *RS = NULL) const {
509 /// processFunctionBeforeFrameFinalized - This method is called immediately
510 /// before the specified functions frame layout (MF.getFrameInfo()) is
511 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
512 /// replaced with direct constants. This method is optional.
514 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
517 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
518 /// frame indices from instructions which may use them. The instruction
519 /// referenced by the iterator contains an MO_FrameIndex operand which must be
520 /// eliminated by this method. This method may modify or replace the
521 /// specified instruction, as long as it keeps the iterator pointing the the
522 /// finished product. SPAdj is the SP adjustment due to call frame setup
524 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
525 int SPAdj, RegScavenger *RS=NULL) const = 0;
527 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
529 virtual void emitPrologue(MachineFunction &MF) const = 0;
530 virtual void emitEpilogue(MachineFunction &MF,
531 MachineBasicBlock &MBB) const = 0;
533 //===--------------------------------------------------------------------===//
534 /// Debug information queries.
536 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
537 /// number. Returns -1 if there is no equivalent value. The second
538 /// parameter allows targets to use different numberings for EH info and
540 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
542 /// getFrameRegister - This method should return the register used as a base
543 /// for values allocated in the current stack frame.
544 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
546 /// getFrameIndexOffset - Returns the displacement from the frame register to
547 /// the stack frame of the specified index.
548 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
550 /// getRARegister - This method should return the register where the return
551 /// address can be found.
552 virtual unsigned getRARegister() const = 0;
554 /// getInitialFrameState - Returns a list of machine moves that are assumed
555 /// on entry to all functions. Note that LabelID is ignored (assumed to be
556 /// the beginning of the function.)
557 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
560 // This is useful when building IndexedMaps keyed on virtual registers
561 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
562 unsigned operator()(unsigned Reg) const {
563 return Reg - TargetRegisterInfo::FirstVirtualRegister;
567 } // End llvm namespace