1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
31 /// TargetRegisterDesc - This record contains all of the information known about
32 /// a particular register. The AliasSet field (if not null) contains a pointer
33 /// to a Zero terminated array of registers that this register aliases. This is
34 /// needed for architectures like X86 which have AL alias AX alias EAX.
35 /// Registers that this does not apply to simply should set this to null.
36 /// The SubRegs field is a zero terminated array of registers that are
37 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
38 /// The SuperRegs field is a zero terminated array of registers that are
39 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
42 struct TargetRegisterDesc {
43 const char *AsmName; // Assembly language name for the register
44 const char *Name; // Printable name for the reg (for debugging)
45 const unsigned *AliasSet; // Register Alias Set, described above
46 const unsigned *SubRegs; // Sub-register set, described above
47 const unsigned *SuperRegs; // Super-register set, described above
50 class TargetRegisterClass {
52 typedef const unsigned* iterator;
53 typedef const unsigned* const_iterator;
55 typedef const MVT* vt_iterator;
56 typedef const TargetRegisterClass* const * sc_iterator;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
66 const iterator RegsBegin, RegsEnd;
68 TargetRegisterClass(unsigned id,
71 const TargetRegisterClass * const *subcs,
72 const TargetRegisterClass * const *supcs,
73 unsigned RS, unsigned Al, int CC,
74 iterator RB, iterator RE)
75 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
76 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
77 virtual ~TargetRegisterClass() {} // Allow subclasses
79 /// getID() - Return the register class ID number.
81 unsigned getID() const { return ID; }
83 /// getName() - Return the register class name for debugging.
85 const char *getName() const { return Name; }
87 /// begin/end - Return all of the registers in this class.
89 iterator begin() const { return RegsBegin; }
90 iterator end() const { return RegsEnd; }
92 /// getNumRegs - Return the number of registers in this class.
94 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
96 /// getRegister - Return the specified register in the class.
98 unsigned getRegister(unsigned i) const {
99 assert(i < getNumRegs() && "Register number out of range!");
103 /// contains - Return true if the specified register is included in this
105 bool contains(unsigned Reg) const {
106 for (iterator I = begin(), E = end(); I != E; ++I)
107 if (*I == Reg) return true;
111 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
113 bool hasType(MVT vt) const {
114 for(int i = 0; VTs[i] != MVT::Other; ++i)
120 /// vt_begin / vt_end - Loop over all of the value types that can be
121 /// represented by values in this register class.
122 vt_iterator vt_begin() const {
126 vt_iterator vt_end() const {
128 while (*I != MVT::Other) ++I;
132 /// hasSubClass - return true if the specified TargetRegisterClass is a
133 /// sub-register class of this TargetRegisterClass.
134 bool hasSubClass(const TargetRegisterClass *cs) const {
135 for (int i = 0; SubClasses[i] != NULL; ++i)
136 if (SubClasses[i] == cs)
141 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
142 /// this register class.
143 sc_iterator subclasses_begin() const {
147 sc_iterator subclasses_end() const {
148 sc_iterator I = SubClasses;
149 while (*I != NULL) ++I;
153 /// hasSuperClass - return true if the specified TargetRegisterClass is a
154 /// super-register class of this TargetRegisterClass.
155 bool hasSuperClass(const TargetRegisterClass *cs) const {
156 for (int i = 0; SuperClasses[i] != NULL; ++i)
157 if (SuperClasses[i] == cs)
162 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
163 /// of this register class.
164 sc_iterator superclasses_begin() const {
168 sc_iterator superclasses_end() const {
169 sc_iterator I = SuperClasses;
170 while (*I != NULL) ++I;
174 /// isASubClass - return true if this TargetRegisterClass is a sub-class of at
175 /// least one other TargetRegisterClass.
176 bool isASubClass() const {
177 return SuperClasses[0] != 0;
180 /// allocation_order_begin/end - These methods define a range of registers
181 /// which specify the registers in this class that are valid to register
182 /// allocate, and the preferred order to allocate them in. For example,
183 /// callee saved registers should be at the end of the list, because it is
184 /// cheaper to allocate caller saved registers.
186 /// These methods take a MachineFunction argument, which can be used to tune
187 /// the allocatable registers based on the characteristics of the function.
188 /// One simple example is that the frame pointer register can be used if
189 /// frame-pointer-elimination is performed.
191 /// By default, these methods return all registers in the class.
193 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
196 virtual iterator allocation_order_end(const MachineFunction &MF) const {
202 /// getSize - Return the size of the register in bytes, which is also the size
203 /// of a stack slot allocated to hold a spilled copy of this register.
204 unsigned getSize() const { return RegSize; }
206 /// getAlignment - Return the minimum required alignment for a register of
208 unsigned getAlignment() const { return Alignment; }
210 /// getCopyCost - Return the cost of copying a value between two registers in
211 /// this class. A negative number means the register class is very expensive
212 /// to copy e.g. status flag register classes.
213 int getCopyCost() const { return CopyCost; }
217 /// TargetRegisterInfo base class - We assume that the target defines a static
218 /// array of TargetRegisterDesc objects that represent all of the machine
219 /// registers that the target has. As such, we simply have to track a pointer
220 /// to this array so that we can turn register number into a register
223 class TargetRegisterInfo {
225 const unsigned* SubregHash;
226 const unsigned SubregHashSize;
228 typedef const TargetRegisterClass * const * regclass_iterator;
230 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
231 unsigned NumRegs; // Number of entries in the array
233 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
235 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
237 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
238 regclass_iterator RegClassBegin,
239 regclass_iterator RegClassEnd,
240 int CallFrameSetupOpcode = -1,
241 int CallFrameDestroyOpcode = -1,
242 const unsigned* subregs = 0,
243 const unsigned subregsize = 0);
244 virtual ~TargetRegisterInfo();
247 enum { // Define some target independent constants
248 /// NoRegister - This physical register is not a real target register. It
249 /// is useful as a sentinal.
252 /// FirstVirtualRegister - This is the first register number that is
253 /// considered to be a 'virtual' register, which is part of the SSA
254 /// namespace. This must be the same for all targets, which means that each
255 /// target is limited to 1024 registers.
256 FirstVirtualRegister = 1024
259 /// isPhysicalRegister - Return true if the specified register number is in
260 /// the physical register namespace.
261 static bool isPhysicalRegister(unsigned Reg) {
262 assert(Reg && "this is not a register!");
263 return Reg < FirstVirtualRegister;
266 /// isVirtualRegister - Return true if the specified register number is in
267 /// the virtual register namespace.
268 static bool isVirtualRegister(unsigned Reg) {
269 assert(Reg && "this is not a register!");
270 return Reg >= FirstVirtualRegister;
273 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
274 /// register of the given type. If type is MVT::Other, then just return any
275 /// register class the register belongs to.
276 virtual const TargetRegisterClass *
277 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
279 /// getAllocatableSet - Returns a bitset indexed by register number
280 /// indicating if a register is allocatable or not. If a register class is
281 /// specified, returns the subset for the class.
282 BitVector getAllocatableSet(MachineFunction &MF,
283 const TargetRegisterClass *RC = NULL) const;
285 const TargetRegisterDesc &operator[](unsigned RegNo) const {
286 assert(RegNo < NumRegs &&
287 "Attempting to access record for invalid register number!");
291 /// Provide a get method, equivalent to [], but more useful if we have a
292 /// pointer to this object.
294 const TargetRegisterDesc &get(unsigned RegNo) const {
295 return operator[](RegNo);
298 /// getAliasSet - Return the set of registers aliased by the specified
299 /// register, or a null list of there are none. The list returned is zero
302 const unsigned *getAliasSet(unsigned RegNo) const {
303 return get(RegNo).AliasSet;
306 /// getSubRegisters - Return the list of registers that are sub-registers of
307 /// the specified register, or a null list of there are none. The list
308 /// returned is zero terminated and sorted according to super-sub register
309 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
311 const unsigned *getSubRegisters(unsigned RegNo) const {
312 return get(RegNo).SubRegs;
315 /// getSuperRegisters - Return the list of registers that are super-registers
316 /// of the specified register, or a null list of there are none. The list
317 /// returned is zero terminated and sorted according to super-sub register
318 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
320 const unsigned *getSuperRegisters(unsigned RegNo) const {
321 return get(RegNo).SuperRegs;
324 /// getAsmName - Return the symbolic target-specific name for the
325 /// specified physical register.
326 const char *getAsmName(unsigned RegNo) const {
327 return get(RegNo).AsmName;
330 /// getName - Return the human-readable symbolic target-specific name for the
331 /// specified physical register.
332 const char *getName(unsigned RegNo) const {
333 return get(RegNo).Name;
336 /// getNumRegs - Return the number of registers this target has (useful for
337 /// sizing arrays holding per register information)
338 unsigned getNumRegs() const {
342 /// areAliases - Returns true if the two registers alias each other, false
344 bool areAliases(unsigned regA, unsigned regB) const {
345 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
346 if (*Alias == regB) return true;
350 /// regsOverlap - Returns true if the two registers are equal or alias each
351 /// other. The registers may be virtual register.
352 bool regsOverlap(unsigned regA, unsigned regB) const {
356 if (isVirtualRegister(regA) || isVirtualRegister(regB))
358 return areAliases(regA, regB);
361 /// isSubRegister - Returns true if regB is a sub-register of regA.
363 bool isSubRegister(unsigned regA, unsigned regB) const {
364 // SubregHash is a simple quadratically probed hash table.
365 size_t index = (regA + regB * 37) & (SubregHashSize-1);
366 unsigned ProbeAmt = 2;
367 while (SubregHash[index*2] != 0 &&
368 SubregHash[index*2+1] != 0) {
369 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
372 index = (index + ProbeAmt) & (SubregHashSize-1);
379 /// isSuperRegister - Returns true if regB is a super-register of regA.
381 bool isSuperRegister(unsigned regA, unsigned regB) const {
382 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
383 if (*SR == regB) return true;
387 /// getCalleeSavedRegs - Return a null-terminated list of all of the
388 /// callee saved registers on this target. The register should be in the
389 /// order of desired callee-save stack frame offset. The first register is
390 /// closed to the incoming stack pointer if stack grows down, and vice versa.
391 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
394 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
395 /// register classes to spill each callee saved register with. The order and
396 /// length of this list match the getCalleeSaveRegs() list.
397 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
398 const MachineFunction *MF) const =0;
400 /// getReservedRegs - Returns a bitset indexed by physical register number
401 /// indicating if a register is a special register that has particular uses
402 /// and should be considered unavailable at all times, e.g. SP, RA. This is
403 /// used by register scavenger to determine what registers are free.
404 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
406 /// getSubReg - Returns the physical register number of sub-register "Index"
407 /// for physical register RegNo. Return zero if the sub-register does not
409 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
411 //===--------------------------------------------------------------------===//
412 // Register Class Information
415 /// Register class iterators
417 regclass_iterator regclass_begin() const { return RegClassBegin; }
418 regclass_iterator regclass_end() const { return RegClassEnd; }
420 unsigned getNumRegClasses() const {
421 return (unsigned)(regclass_end()-regclass_begin());
424 /// getRegClass - Returns the register class associated with the enumeration
425 /// value. See class TargetOperandInfo.
426 const TargetRegisterClass *getRegClass(unsigned i) const {
427 assert(i <= getNumRegClasses() && "Register Class ID out of range");
428 return i ? RegClassBegin[i - 1] : NULL;
431 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
433 virtual const TargetRegisterClass *getPointerRegClass() const {
434 assert(0 && "Target didn't implement getPointerRegClass!");
435 return 0; // Must return a value in order to compile with VS 2005
438 /// getCrossCopyRegClass - Returns a legal register class to copy a register
439 /// in the specified class to or from. Returns NULL if it is possible to copy
440 /// between a two registers of the specified class.
441 virtual const TargetRegisterClass *
442 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
446 /// targetHandlesStackFrameRounding - Returns true if the target is
447 /// responsible for rounding up the stack frame (probably at emitPrologue
449 virtual bool targetHandlesStackFrameRounding() const {
453 /// requiresRegisterScavenging - returns true if the target requires (and can
454 /// make use of) the register scavenger.
455 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
459 /// hasFP - Return true if the specified function should have a dedicated
460 /// frame pointer register. For most targets this is true only if the function
461 /// has variable sized allocas or if frame pointer elimination is disabled.
462 virtual bool hasFP(const MachineFunction &MF) const = 0;
464 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
465 // not required, we reserve argument space for call sites in the function
466 // immediately on entry to the current function. This eliminates the need for
467 // add/sub sp brackets around call sites. Returns true if the call frame is
468 // included as part of the stack frame.
469 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
473 // needsStackRealignment - true if storage within the function requires the
474 // stack pointer to be aligned more than the normal calling convention calls
476 virtual bool needsStackRealignment(const MachineFunction &MF) const {
480 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
481 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
482 /// targets use pseudo instructions in order to abstract away the difference
483 /// between operating with a frame pointer and operating without, through the
484 /// use of these two instructions.
486 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
487 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
489 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
490 /// code insertion to eliminate call frame setup and destroy pseudo
491 /// instructions (but only if the Target is using them). It is responsible
492 /// for eliminating these instructions, replacing them with concrete
493 /// instructions. This method need only be implemented if using call frame
494 /// setup/destroy pseudo instructions.
497 eliminateCallFramePseudoInstr(MachineFunction &MF,
498 MachineBasicBlock &MBB,
499 MachineBasicBlock::iterator MI) const {
500 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
501 "eliminateCallFramePseudoInstr must be implemented if using"
502 " call frame setup/destroy pseudo instructions!");
503 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
506 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
507 /// before PrologEpilogInserter scans the physical registers used to determine
508 /// what callee saved registers should be spilled. This method is optional.
509 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
510 RegScavenger *RS = NULL) const {
514 /// processFunctionBeforeFrameFinalized - This method is called immediately
515 /// before the specified functions frame layout (MF.getFrameInfo()) is
516 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
517 /// replaced with direct constants. This method is optional.
519 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
522 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
523 /// frame indices from instructions which may use them. The instruction
524 /// referenced by the iterator contains an MO_FrameIndex operand which must be
525 /// eliminated by this method. This method may modify or replace the
526 /// specified instruction, as long as it keeps the iterator pointing the the
527 /// finished product. SPAdj is the SP adjustment due to call frame setup
529 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
530 int SPAdj, RegScavenger *RS=NULL) const = 0;
532 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
534 virtual void emitPrologue(MachineFunction &MF) const = 0;
535 virtual void emitEpilogue(MachineFunction &MF,
536 MachineBasicBlock &MBB) const = 0;
538 //===--------------------------------------------------------------------===//
539 /// Debug information queries.
541 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
542 /// number. Returns -1 if there is no equivalent value. The second
543 /// parameter allows targets to use different numberings for EH info and
545 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
547 /// getFrameRegister - This method should return the register used as a base
548 /// for values allocated in the current stack frame.
549 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
551 /// getFrameIndexOffset - Returns the displacement from the frame register to
552 /// the stack frame of the specified index.
553 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
555 /// getRARegister - This method should return the register where the return
556 /// address can be found.
557 virtual unsigned getRARegister() const = 0;
559 /// getInitialFrameState - Returns a list of machine moves that are assumed
560 /// on entry to all functions. Note that LabelID is ignored (assumed to be
561 /// the beginning of the function.)
562 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
565 // This is useful when building IndexedMaps keyed on virtual registers
566 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
567 unsigned operator()(unsigned Reg) const {
568 return Reg - TargetRegisterInfo::FirstVirtualRegister;
572 } // End llvm namespace