1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/ADT/DenseSet.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
35 class TargetRegisterClass {
37 typedef const unsigned* iterator;
38 typedef const unsigned* const_iterator;
39 typedef const EVT* vt_iterator;
40 typedef const TargetRegisterClass* const * sc_iterator;
42 const MCRegisterClass *MC;
43 const vt_iterator VTs;
44 const sc_iterator SubClasses;
45 const sc_iterator SuperClasses;
46 const sc_iterator SubRegClasses;
47 const sc_iterator SuperRegClasses;
49 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
50 const TargetRegisterClass * const *subcs,
51 const TargetRegisterClass * const *supcs,
52 const TargetRegisterClass * const *subregcs,
53 const TargetRegisterClass * const *superregcs)
54 : MC(MC), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
55 SubRegClasses(subregcs), SuperRegClasses(superregcs) {}
57 virtual ~TargetRegisterClass() {} // Allow subclasses
59 /// getID() - Return the register class ID number.
61 unsigned getID() const { return MC->getID(); }
63 /// getName() - Return the register class name for debugging.
65 const char *getName() const { return MC->getName(); }
67 /// begin/end - Return all of the registers in this class.
69 iterator begin() const { return MC->begin(); }
70 iterator end() const { return MC->end(); }
72 /// getNumRegs - Return the number of registers in this class.
74 unsigned getNumRegs() const { return MC->getNumRegs(); }
76 /// getRegister - Return the specified register in the class.
78 unsigned getRegister(unsigned i) const {
79 return MC->getRegister(i);
82 /// contains - Return true if the specified register is included in this
83 /// register class. This does not include virtual registers.
84 bool contains(unsigned Reg) const {
85 return MC->contains(Reg);
88 /// contains - Return true if both registers are in this class.
89 bool contains(unsigned Reg1, unsigned Reg2) const {
90 return MC->contains(Reg1, Reg2);
93 /// getSize - Return the size of the register in bytes, which is also the size
94 /// of a stack slot allocated to hold a spilled copy of this register.
95 unsigned getSize() const { return MC->getSize(); }
97 /// getAlignment - Return the minimum required alignment for a register of
99 unsigned getAlignment() const { return MC->getAlignment(); }
101 /// getCopyCost - Return the cost of copying a value between two registers in
102 /// this class. A negative number means the register class is very expensive
103 /// to copy e.g. status flag register classes.
104 int getCopyCost() const { return MC->getCopyCost(); }
106 /// isAllocatable - Return true if this register class may be used to create
107 /// virtual registers.
108 bool isAllocatable() const { return MC->isAllocatable(); }
110 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
112 bool hasType(EVT vt) const {
113 for(int i = 0; VTs[i] != MVT::Other; ++i)
119 /// vt_begin / vt_end - Loop over all of the value types that can be
120 /// represented by values in this register class.
121 vt_iterator vt_begin() const {
125 vt_iterator vt_end() const {
127 while (*I != MVT::Other) ++I;
131 /// subregclasses_begin / subregclasses_end - Loop over all of
132 /// the subreg register classes of this register class.
133 sc_iterator subregclasses_begin() const {
134 return SubRegClasses;
137 sc_iterator subregclasses_end() const {
138 sc_iterator I = SubRegClasses;
139 while (*I != NULL) ++I;
143 /// getSubRegisterRegClass - Return the register class of subregisters with
144 /// index SubIdx, or NULL if no such class exists.
145 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
146 assert(SubIdx>0 && "Invalid subregister index");
147 return SubRegClasses[SubIdx-1];
150 /// superregclasses_begin / superregclasses_end - Loop over all of
151 /// the superreg register classes of this register class.
152 sc_iterator superregclasses_begin() const {
153 return SuperRegClasses;
156 sc_iterator superregclasses_end() const {
157 sc_iterator I = SuperRegClasses;
158 while (*I != NULL) ++I;
162 /// hasSubClass - return true if the specified TargetRegisterClass
163 /// is a proper subset of this TargetRegisterClass.
164 bool hasSubClass(const TargetRegisterClass *cs) const {
165 for (int i = 0; SubClasses[i] != NULL; ++i)
166 if (SubClasses[i] == cs)
171 /// hasSubClassEq - Returns true if RC is a subclass of or equal to this
173 bool hasSubClassEq(const TargetRegisterClass *RC) const {
174 return RC == this || hasSubClass(RC);
177 /// subclasses_begin / subclasses_end - Loop over all of the classes
178 /// that are proper subsets of this register class.
179 sc_iterator subclasses_begin() const {
183 sc_iterator subclasses_end() const {
184 sc_iterator I = SubClasses;
185 while (*I != NULL) ++I;
189 /// hasSuperClass - return true if the specified TargetRegisterClass is a
190 /// proper superset of this TargetRegisterClass.
191 bool hasSuperClass(const TargetRegisterClass *cs) const {
192 for (int i = 0; SuperClasses[i] != NULL; ++i)
193 if (SuperClasses[i] == cs)
198 /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this
200 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
201 return RC == this || hasSuperClass(RC);
204 /// superclasses_begin / superclasses_end - Loop over all of the classes
205 /// that are proper supersets of this register class.
206 sc_iterator superclasses_begin() const {
210 sc_iterator superclasses_end() const {
211 sc_iterator I = SuperClasses;
212 while (*I != NULL) ++I;
216 /// isASubClass - return true if this TargetRegisterClass is a subset
217 /// class of at least one other TargetRegisterClass.
218 bool isASubClass() const {
219 return SuperClasses[0] != 0;
222 /// getRawAllocationOrder - Returns the preferred order for allocating
223 /// registers from this register class in MF. The raw order comes directly
224 /// from the .td file and may include reserved registers that are not
225 /// allocatable. Register allocators should also make sure to allocate
226 /// callee-saved registers only after all the volatiles are used. The
227 /// RegisterClassInfo class provides filtered allocation orders with
228 /// callee-saved registers moved to the end.
230 /// The MachineFunction argument can be used to tune the allocatable
231 /// registers based on the characteristics of the function, subtarget, or
234 /// By default, this method returns all registers in the class.
237 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
238 return makeArrayRef(begin(), getNumRegs());
242 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
243 /// registers. These are used by codegen, not by MC.
244 struct TargetRegisterInfoDesc {
245 unsigned CostPerUse; // Extra cost of instructions using register.
246 bool inAllocatableClass; // Register belongs to an allocatable regclass.
249 /// TargetRegisterInfo base class - We assume that the target defines a static
250 /// array of TargetRegisterDesc objects that represent all of the machine
251 /// registers that the target has. As such, we simply have to track a pointer
252 /// to this array so that we can turn register number into a register
255 class TargetRegisterInfo : public MCRegisterInfo {
257 typedef const TargetRegisterClass * const * regclass_iterator;
259 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
260 const char *const *SubRegIndexNames; // Names of subreg indexes.
261 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
264 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
265 regclass_iterator RegClassBegin,
266 regclass_iterator RegClassEnd,
267 const char *const *subregindexnames);
268 virtual ~TargetRegisterInfo();
271 // Register numbers can represent physical registers, virtual registers, and
272 // sometimes stack slots. The unsigned values are divided into these ranges:
274 // 0 Not a register, can be used as a sentinel.
275 // [1;2^30) Physical registers assigned by TableGen.
276 // [2^30;2^31) Stack slots. (Rarely used.)
277 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
279 // Further sentinels can be allocated from the small negative integers.
280 // DenseMapInfo<unsigned> uses -1u and -2u.
282 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
283 /// frame index in a variable that normally holds a register. isStackSlot()
284 /// returns true if Reg is in the range used for stack slots.
286 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
287 /// slots, so if a variable may contains a stack slot, always check
288 /// isStackSlot() first.
290 static bool isStackSlot(unsigned Reg) {
291 return int(Reg) >= (1 << 30);
294 /// stackSlot2Index - Compute the frame index from a register value
295 /// representing a stack slot.
296 static int stackSlot2Index(unsigned Reg) {
297 assert(isStackSlot(Reg) && "Not a stack slot");
298 return int(Reg - (1u << 30));
301 /// index2StackSlot - Convert a non-negative frame index to a stack slot
303 static unsigned index2StackSlot(int FI) {
304 assert(FI >= 0 && "Cannot hold a negative frame index.");
305 return FI + (1u << 30);
308 /// isPhysicalRegister - Return true if the specified register number is in
309 /// the physical register namespace.
310 static bool isPhysicalRegister(unsigned Reg) {
311 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
315 /// isVirtualRegister - Return true if the specified register number is in
316 /// the virtual register namespace.
317 static bool isVirtualRegister(unsigned Reg) {
318 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
322 /// virtReg2Index - Convert a virtual register number to a 0-based index.
323 /// The first virtual register in a function will get the index 0.
324 static unsigned virtReg2Index(unsigned Reg) {
325 assert(isVirtualRegister(Reg) && "Not a virtual register");
326 return Reg & ~(1u << 31);
329 /// index2VirtReg - Convert a 0-based index to a virtual register number.
330 /// This is the inverse operation of VirtReg2IndexFunctor below.
331 static unsigned index2VirtReg(unsigned Index) {
332 return Index | (1u << 31);
335 /// getMinimalPhysRegClass - Returns the Register Class of a physical
336 /// register of the given type, picking the most sub register class of
337 /// the right type that contains this physreg.
338 const TargetRegisterClass *
339 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
341 /// getAllocatableSet - Returns a bitset indexed by register number
342 /// indicating if a register is allocatable or not. If a register class is
343 /// specified, returns the subset for the class.
344 BitVector getAllocatableSet(const MachineFunction &MF,
345 const TargetRegisterClass *RC = NULL) const;
347 /// getCostPerUse - Return the additional cost of using this register instead
348 /// of other registers in its class.
349 unsigned getCostPerUse(unsigned RegNo) const {
350 return InfoDesc[RegNo].CostPerUse;
353 /// isInAllocatableClass - Return true if the register is in the allocation
354 /// of any register class.
355 bool isInAllocatableClass(unsigned RegNo) const {
356 return InfoDesc[RegNo].inAllocatableClass;
359 /// getSubRegIndexName - Return the human-readable symbolic target-specific
360 /// name for the specified SubRegIndex.
361 const char *getSubRegIndexName(unsigned SubIdx) const {
362 assert(SubIdx && "This is not a subregister index");
363 return SubRegIndexNames[SubIdx-1];
366 /// regsOverlap - Returns true if the two registers are equal or alias each
367 /// other. The registers may be virtual register.
368 bool regsOverlap(unsigned regA, unsigned regB) const {
369 if (regA == regB) return true;
370 if (isVirtualRegister(regA) || isVirtualRegister(regB))
372 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) {
373 if (*regList == regB) return true;
378 /// isSubRegister - Returns true if regB is a sub-register of regA.
380 bool isSubRegister(unsigned regA, unsigned regB) const {
381 return isSuperRegister(regB, regA);
384 /// isSuperRegister - Returns true if regB is a super-register of regA.
386 bool isSuperRegister(unsigned regA, unsigned regB) const {
387 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){
388 if (*regList == regB) return true;
393 /// getCalleeSavedRegs - Return a null-terminated list of all of the
394 /// callee saved registers on this target. The register should be in the
395 /// order of desired callee-save stack frame offset. The first register is
396 /// closed to the incoming stack pointer if stack grows down, and vice versa.
397 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
401 /// getReservedRegs - Returns a bitset indexed by physical register number
402 /// indicating if a register is a special register that has particular uses
403 /// and should be considered unavailable at all times, e.g. SP, RA. This is
404 /// used by register scavenger to determine what registers are free.
405 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
407 /// getSubReg - Returns the physical register number of sub-register "Index"
408 /// for physical register RegNo. Return zero if the sub-register does not
410 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
412 /// getSubRegIndex - For a given register pair, return the sub-register index
413 /// if the second register is a sub-register of the first. Return zero
415 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
417 /// getMatchingSuperReg - Return a super-register of the specified register
418 /// Reg so its sub-register of index SubIdx is Reg.
419 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
420 const TargetRegisterClass *RC) const {
421 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
422 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
427 /// canCombineSubRegIndices - Given a register class and a list of
428 /// subregister indices, return true if it's possible to combine the
429 /// subregister indices into one that corresponds to a larger
430 /// subregister. Return the new subregister index by reference. Note the
431 /// new index may be zero if the given subregisters can be combined to
432 /// form the whole register.
433 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
434 SmallVectorImpl<unsigned> &SubIndices,
435 unsigned &NewSubIdx) const {
439 /// getMatchingSuperRegClass - Return a subclass of the specified register
440 /// class A so that each register in it has a sub-register of the
441 /// specified sub-register index which is in the specified register class B.
442 virtual const TargetRegisterClass *
443 getMatchingSuperRegClass(const TargetRegisterClass *A,
444 const TargetRegisterClass *B, unsigned Idx) const {
448 /// composeSubRegIndices - Return the subregister index you get from composing
449 /// two subregister indices.
451 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
452 /// returns c. Note that composeSubRegIndices does not tell you about illegal
453 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
454 /// b, composeSubRegIndices doesn't tell you.
456 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
457 /// ssub_0:S0 - ssub_3:S3 subregs.
458 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
460 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
461 // This default implementation is correct for most targets.
465 //===--------------------------------------------------------------------===//
466 // Register Class Information
469 /// Register class iterators
471 regclass_iterator regclass_begin() const { return RegClassBegin; }
472 regclass_iterator regclass_end() const { return RegClassEnd; }
474 unsigned getNumRegClasses() const {
475 return (unsigned)(regclass_end()-regclass_begin());
478 /// getRegClass - Returns the register class associated with the enumeration
479 /// value. See class MCOperandInfo.
480 const TargetRegisterClass *getRegClass(unsigned i) const {
481 assert(i < getNumRegClasses() && "Register Class ID out of range");
482 return RegClassBegin[i];
485 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
486 /// values. If a target supports multiple different pointer register classes,
487 /// kind specifies which one is indicated.
488 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
489 assert(0 && "Target didn't implement getPointerRegClass!");
490 return 0; // Must return a value in order to compile with VS 2005
493 /// getCrossCopyRegClass - Returns a legal register class to copy a register
494 /// in the specified class to or from. If it is possible to copy the register
495 /// directly without using a cross register class copy, return the specified
496 /// RC. Returns NULL if it is not possible to copy between a two registers of
497 /// the specified class.
498 virtual const TargetRegisterClass *
499 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
503 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
504 /// legal to use in the current sub-target and has the same spill size.
505 /// The returned register class can be used to create virtual registers which
506 /// means that all its registers can be copied and spilled.
507 virtual const TargetRegisterClass*
508 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
509 /// The default implementation is very conservative and doesn't allow the
510 /// register allocator to inflate register classes.
514 /// getRegPressureLimit - Return the register pressure "high water mark" for
515 /// the specific register class. The scheduler is in high register pressure
516 /// mode (for the specific register class) if it goes over the limit.
517 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
518 MachineFunction &MF) const {
522 /// getRawAllocationOrder - Returns the register allocation order for a
523 /// specified register class with a target-dependent hint. The returned list
524 /// may contain reserved registers that cannot be allocated.
526 /// Register allocators need only call this function to resolve
527 /// target-dependent hints, but it should work without hinting as well.
528 virtual ArrayRef<unsigned>
529 getRawAllocationOrder(const TargetRegisterClass *RC,
530 unsigned HintType, unsigned HintReg,
531 const MachineFunction &MF) const {
532 return RC->getRawAllocationOrder(MF);
535 /// ResolveRegAllocHint - Resolves the specified register allocation hint
536 /// to a physical register. Returns the physical register if it is successful.
537 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
538 const MachineFunction &MF) const {
539 if (Type == 0 && Reg && isPhysicalRegister(Reg))
544 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
545 /// writing a register from RC in two consecutive instructions.
546 /// This can avoid pipeline stalls on certain architectures.
547 /// It does cause increased register pressure, though.
548 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
552 /// UpdateRegAllocHint - A callback to allow target a chance to update
553 /// register allocation hints when a register is "changed" (e.g. coalesced)
554 /// to another register. e.g. On ARM, some virtual registers should target
555 /// register pairs, if one of pair is coalesced to another register, the
556 /// allocation hint of the other half of the pair should be changed to point
557 /// to the new register.
558 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
559 MachineFunction &MF) const {
563 /// requiresRegisterScavenging - returns true if the target requires (and can
564 /// make use of) the register scavenger.
565 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
569 /// useFPForScavengingIndex - returns true if the target wants to use
570 /// frame pointer based accesses to spill to the scavenger emergency spill
572 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
576 /// requiresFrameIndexScavenging - returns true if the target requires post
577 /// PEI scavenging of registers for materializing frame index constants.
578 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
582 /// requiresVirtualBaseRegisters - Returns true if the target wants the
583 /// LocalStackAllocation pass to be run and virtual base registers
584 /// used for more efficient stack access.
585 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
589 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
590 /// the stack frame of the given function for the specified register. e.g. On
591 /// x86, if the frame register is required, the first fixed stack object is
592 /// reserved as its spill slot. This tells PEI not to create a new stack frame
593 /// object for the given register. It should be called only after
594 /// processFunctionBeforeCalleeSavedScan().
595 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
596 int &FrameIdx) const {
600 /// needsStackRealignment - true if storage within the function requires the
601 /// stack pointer to be aligned more than the normal calling convention calls
603 virtual bool needsStackRealignment(const MachineFunction &MF) const {
607 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
608 /// index in the instruction, if there is one.
609 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
614 /// needsFrameBaseReg - Returns true if the instruction's frame index
615 /// reference would be better served by a base register other than FP
616 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
617 /// references it should create new base registers for.
618 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
622 /// materializeFrameBaseRegister - Insert defining instruction(s) for
623 /// BaseReg to be a pointer to FrameIdx before insertion point I.
624 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
625 unsigned BaseReg, int FrameIdx,
626 int64_t Offset) const {
627 assert(0 && "materializeFrameBaseRegister does not exist on this target");
630 /// resolveFrameIndex - Resolve a frame index operand of an instruction
631 /// to reference the indicated base register plus offset instead.
632 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
633 unsigned BaseReg, int64_t Offset) const {
634 assert(0 && "resolveFrameIndex does not exist on this target");
637 /// isFrameOffsetLegal - Determine whether a given offset immediate is
638 /// encodable to resolve a frame index.
639 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
640 int64_t Offset) const {
641 assert(0 && "isFrameOffsetLegal does not exist on this target");
642 return false; // Must return a value in order to compile with VS 2005
645 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
646 /// code insertion to eliminate call frame setup and destroy pseudo
647 /// instructions (but only if the Target is using them). It is responsible
648 /// for eliminating these instructions, replacing them with concrete
649 /// instructions. This method need only be implemented if using call frame
650 /// setup/destroy pseudo instructions.
653 eliminateCallFramePseudoInstr(MachineFunction &MF,
654 MachineBasicBlock &MBB,
655 MachineBasicBlock::iterator MI) const {
656 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
660 /// saveScavengerRegister - Spill the register so it can be used by the
661 /// register scavenger. Return true if the register was spilled, false
662 /// otherwise. If this function does not spill the register, the scavenger
663 /// will instead spill it to the emergency spill slot.
665 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
666 MachineBasicBlock::iterator I,
667 MachineBasicBlock::iterator &UseMI,
668 const TargetRegisterClass *RC,
669 unsigned Reg) const {
673 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
674 /// frame indices from instructions which may use them. The instruction
675 /// referenced by the iterator contains an MO_FrameIndex operand which must be
676 /// eliminated by this method. This method may modify or replace the
677 /// specified instruction, as long as it keeps the iterator pointing at the
678 /// finished product. SPAdj is the SP adjustment due to call frame setup
680 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
681 int SPAdj, RegScavenger *RS=NULL) const = 0;
683 //===--------------------------------------------------------------------===//
684 /// Debug information queries.
686 /// getFrameRegister - This method should return the register used as a base
687 /// for values allocated in the current stack frame.
688 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
690 /// getCompactUnwindRegNum - This function maps the register to the number for
691 /// compact unwind encoding. Return -1 if the register isn't valid.
692 virtual int getCompactUnwindRegNum(unsigned, bool) const {
698 // This is useful when building IndexedMaps keyed on virtual registers
699 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
700 unsigned operator()(unsigned Reg) const {
701 return TargetRegisterInfo::virtReg2Index(Reg);
705 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
706 /// if there is no common subclass.
707 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
708 const TargetRegisterClass *B);
710 /// PrintReg - Helper class for printing registers on a raw_ostream.
711 /// Prints virtual and physical registers with or without a TRI instance.
714 /// %noreg - NoRegister
715 /// %vreg5 - a virtual register.
716 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
717 /// %EAX - a physical register
718 /// %physreg17 - a physical register when no TRI instance given.
720 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
723 const TargetRegisterInfo *TRI;
727 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
728 : TRI(tri), Reg(reg), SubIdx(subidx) {}
729 void print(raw_ostream&) const;
732 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
737 } // End llvm namespace