1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
32 /// TargetRegisterDesc - This record contains all of the information known about
33 /// a particular register. The AliasSet field (if not null) contains a pointer
34 /// to a Zero terminated array of registers that this register aliases. This is
35 /// needed for architectures like X86 which have AL alias AX alias EAX.
36 /// Registers that this does not apply to simply should set this to null.
37 /// The SubRegs field is a zero terminated array of registers that are
38 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
39 /// The SuperRegs field is a zero terminated array of registers that are
40 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
43 struct TargetRegisterDesc {
44 const char *Name; // Printable name for the reg (for debugging)
45 const unsigned *AliasSet; // Register Alias Set, described above
46 const unsigned *SubRegs; // Sub-register set, described above
47 const unsigned *SuperRegs; // Super-register set, described above
50 class TargetRegisterClass {
52 typedef const unsigned* iterator;
53 typedef const unsigned* const_iterator;
55 typedef const EVT* vt_iterator;
56 typedef const TargetRegisterClass* const * sc_iterator;
60 const vt_iterator VTs;
61 const sc_iterator SubClasses;
62 const sc_iterator SuperClasses;
63 const sc_iterator SubRegClasses;
64 const sc_iterator SuperRegClasses;
65 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
67 const iterator RegsBegin, RegsEnd;
68 DenseSet<unsigned> RegSet;
70 TargetRegisterClass(unsigned id,
73 const TargetRegisterClass * const *subcs,
74 const TargetRegisterClass * const *supcs,
75 const TargetRegisterClass * const *subregcs,
76 const TargetRegisterClass * const *superregcs,
77 unsigned RS, unsigned Al, int CC,
78 iterator RB, iterator RE)
79 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
80 SubRegClasses(subregcs), SuperRegClasses(superregcs),
81 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
82 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
85 virtual ~TargetRegisterClass() {} // Allow subclasses
87 /// getID() - Return the register class ID number.
89 unsigned getID() const { return ID; }
91 /// getName() - Return the register class name for debugging.
93 const char *getName() const { return Name; }
95 /// begin/end - Return all of the registers in this class.
97 iterator begin() const { return RegsBegin; }
98 iterator end() const { return RegsEnd; }
100 /// getNumRegs - Return the number of registers in this class.
102 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
104 /// getRegister - Return the specified register in the class.
106 unsigned getRegister(unsigned i) const {
107 assert(i < getNumRegs() && "Register number out of range!");
111 /// contains - Return true if the specified register is included in this
113 bool contains(unsigned Reg) const {
114 return RegSet.count(Reg);
117 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
119 bool hasType(EVT vt) const {
120 for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
126 /// vt_begin / vt_end - Loop over all of the value types that can be
127 /// represented by values in this register class.
128 vt_iterator vt_begin() const {
132 vt_iterator vt_end() const {
134 while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
138 /// subregclasses_begin / subregclasses_end - Loop over all of
139 /// the subreg register classes of this register class.
140 sc_iterator subregclasses_begin() const {
141 return SubRegClasses;
144 sc_iterator subregclasses_end() const {
145 sc_iterator I = SubRegClasses;
146 while (*I != NULL) ++I;
150 /// getSubRegisterRegClass - Return the register class of subregisters with
151 /// index SubIdx, or NULL if no such class exists.
152 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
153 assert(SubIdx>0 && "Invalid subregister index");
154 for (unsigned s = 0; s != SubIdx-1; ++s)
155 if (!SubRegClasses[s])
157 return SubRegClasses[SubIdx-1];
160 /// superregclasses_begin / superregclasses_end - Loop over all of
161 /// the superreg register classes of this register class.
162 sc_iterator superregclasses_begin() const {
163 return SuperRegClasses;
166 sc_iterator superregclasses_end() const {
167 sc_iterator I = SuperRegClasses;
168 while (*I != NULL) ++I;
172 /// hasSubClass - return true if the the specified TargetRegisterClass
173 /// is a proper subset of this TargetRegisterClass.
174 bool hasSubClass(const TargetRegisterClass *cs) const {
175 for (int i = 0; SubClasses[i] != NULL; ++i)
176 if (SubClasses[i] == cs)
181 /// subclasses_begin / subclasses_end - Loop over all of the classes
182 /// that are proper subsets of this register class.
183 sc_iterator subclasses_begin() const {
187 sc_iterator subclasses_end() const {
188 sc_iterator I = SubClasses;
189 while (*I != NULL) ++I;
193 /// hasSuperClass - return true if the specified TargetRegisterClass is a
194 /// proper superset of this TargetRegisterClass.
195 bool hasSuperClass(const TargetRegisterClass *cs) const {
196 for (int i = 0; SuperClasses[i] != NULL; ++i)
197 if (SuperClasses[i] == cs)
202 /// superclasses_begin / superclasses_end - Loop over all of the classes
203 /// that are proper supersets of this register class.
204 sc_iterator superclasses_begin() const {
208 sc_iterator superclasses_end() const {
209 sc_iterator I = SuperClasses;
210 while (*I != NULL) ++I;
214 /// isASubClass - return true if this TargetRegisterClass is a subset
215 /// class of at least one other TargetRegisterClass.
216 bool isASubClass() const {
217 return SuperClasses[0] != 0;
220 /// allocation_order_begin/end - These methods define a range of registers
221 /// which specify the registers in this class that are valid to register
222 /// allocate, and the preferred order to allocate them in. For example,
223 /// callee saved registers should be at the end of the list, because it is
224 /// cheaper to allocate caller saved registers.
226 /// These methods take a MachineFunction argument, which can be used to tune
227 /// the allocatable registers based on the characteristics of the function.
228 /// One simple example is that the frame pointer register can be used if
229 /// frame-pointer-elimination is performed.
231 /// By default, these methods return all registers in the class.
233 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
236 virtual iterator allocation_order_end(const MachineFunction &MF) const {
240 /// getSize - Return the size of the register in bytes, which is also the size
241 /// of a stack slot allocated to hold a spilled copy of this register.
242 unsigned getSize() const { return RegSize; }
244 /// getAlignment - Return the minimum required alignment for a register of
246 unsigned getAlignment() const { return Alignment; }
248 /// getCopyCost - Return the cost of copying a value between two registers in
249 /// this class. A negative number means the register class is very expensive
250 /// to copy e.g. status flag register classes.
251 int getCopyCost() const { return CopyCost; }
255 /// TargetRegisterInfo base class - We assume that the target defines a static
256 /// array of TargetRegisterDesc objects that represent all of the machine
257 /// registers that the target has. As such, we simply have to track a pointer
258 /// to this array so that we can turn register number into a register
261 class TargetRegisterInfo {
263 const unsigned* SubregHash;
264 const unsigned SubregHashSize;
265 const unsigned* SuperregHash;
266 const unsigned SuperregHashSize;
267 const unsigned* AliasesHash;
268 const unsigned AliasesHashSize;
270 typedef const TargetRegisterClass * const * regclass_iterator;
272 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
273 unsigned NumRegs; // Number of entries in the array
275 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
277 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
280 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
281 regclass_iterator RegClassBegin,
282 regclass_iterator RegClassEnd,
283 int CallFrameSetupOpcode = -1,
284 int CallFrameDestroyOpcode = -1,
285 const unsigned* subregs = 0,
286 const unsigned subregsize = 0,
287 const unsigned* superregs = 0,
288 const unsigned superregsize = 0,
289 const unsigned* aliases = 0,
290 const unsigned aliasessize = 0);
291 virtual ~TargetRegisterInfo();
294 enum { // Define some target independent constants
295 /// NoRegister - This physical register is not a real target register. It
296 /// is useful as a sentinal.
299 /// FirstVirtualRegister - This is the first register number that is
300 /// considered to be a 'virtual' register, which is part of the SSA
301 /// namespace. This must be the same for all targets, which means that each
302 /// target is limited to 1024 registers.
303 FirstVirtualRegister = 1024
306 /// isPhysicalRegister - Return true if the specified register number is in
307 /// the physical register namespace.
308 static bool isPhysicalRegister(unsigned Reg) {
309 assert(Reg && "this is not a register!");
310 return Reg < FirstVirtualRegister;
313 /// isVirtualRegister - Return true if the specified register number is in
314 /// the virtual register namespace.
315 static bool isVirtualRegister(unsigned Reg) {
316 assert(Reg && "this is not a register!");
317 return Reg >= FirstVirtualRegister;
320 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
321 /// register of the given type. If type is EVT::Other, then just return any
322 /// register class the register belongs to.
323 virtual const TargetRegisterClass *
324 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
326 /// getAllocatableSet - Returns a bitset indexed by register number
327 /// indicating if a register is allocatable or not. If a register class is
328 /// specified, returns the subset for the class.
329 BitVector getAllocatableSet(const MachineFunction &MF,
330 const TargetRegisterClass *RC = NULL) const;
332 const TargetRegisterDesc &operator[](unsigned RegNo) const {
333 assert(RegNo < NumRegs &&
334 "Attempting to access record for invalid register number!");
338 /// Provide a get method, equivalent to [], but more useful if we have a
339 /// pointer to this object.
341 const TargetRegisterDesc &get(unsigned RegNo) const {
342 return operator[](RegNo);
345 /// getAliasSet - Return the set of registers aliased by the specified
346 /// register, or a null list of there are none. The list returned is zero
349 const unsigned *getAliasSet(unsigned RegNo) const {
350 return get(RegNo).AliasSet;
353 /// getSubRegisters - Return the list of registers that are sub-registers of
354 /// the specified register, or a null list of there are none. The list
355 /// returned is zero terminated and sorted according to super-sub register
356 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
358 const unsigned *getSubRegisters(unsigned RegNo) const {
359 return get(RegNo).SubRegs;
362 /// getSuperRegisters - Return the list of registers that are super-registers
363 /// of the specified register, or a null list of there are none. The list
364 /// returned is zero terminated and sorted according to super-sub register
365 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
367 const unsigned *getSuperRegisters(unsigned RegNo) const {
368 return get(RegNo).SuperRegs;
371 /// getName - Return the human-readable symbolic target-specific name for the
372 /// specified physical register.
373 const char *getName(unsigned RegNo) const {
374 return get(RegNo).Name;
377 /// getNumRegs - Return the number of registers this target has (useful for
378 /// sizing arrays holding per register information)
379 unsigned getNumRegs() const {
383 /// regsOverlap - Returns true if the two registers are equal or alias each
384 /// other. The registers may be virtual register.
385 bool regsOverlap(unsigned regA, unsigned regB) const {
389 if (isVirtualRegister(regA) || isVirtualRegister(regB))
392 // regA and regB are distinct physical registers. Do they alias?
393 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
394 unsigned ProbeAmt = 0;
395 while (AliasesHash[index*2] != 0 &&
396 AliasesHash[index*2+1] != 0) {
397 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
400 index = (index + ProbeAmt) & (AliasesHashSize-1);
407 /// isSubRegister - Returns true if regB is a sub-register of regA.
409 bool isSubRegister(unsigned regA, unsigned regB) const {
410 // SubregHash is a simple quadratically probed hash table.
411 size_t index = (regA + regB * 37) & (SubregHashSize-1);
412 unsigned ProbeAmt = 2;
413 while (SubregHash[index*2] != 0 &&
414 SubregHash[index*2+1] != 0) {
415 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
418 index = (index + ProbeAmt) & (SubregHashSize-1);
425 /// isSuperRegister - Returns true if regB is a super-register of regA.
427 bool isSuperRegister(unsigned regA, unsigned regB) const {
428 // SuperregHash is a simple quadratically probed hash table.
429 size_t index = (regA + regB * 37) & (SuperregHashSize-1);
430 unsigned ProbeAmt = 2;
431 while (SuperregHash[index*2] != 0 &&
432 SuperregHash[index*2+1] != 0) {
433 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
436 index = (index + ProbeAmt) & (SuperregHashSize-1);
443 /// getCalleeSavedRegs - Return a null-terminated list of all of the
444 /// callee saved registers on this target. The register should be in the
445 /// order of desired callee-save stack frame offset. The first register is
446 /// closed to the incoming stack pointer if stack grows down, and vice versa.
447 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
450 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
451 /// register classes to spill each callee saved register with. The order and
452 /// length of this list match the getCalleeSaveRegs() list.
453 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
454 const MachineFunction *MF) const =0;
456 /// getReservedRegs - Returns a bitset indexed by physical register number
457 /// indicating if a register is a special register that has particular uses
458 /// and should be considered unavailable at all times, e.g. SP, RA. This is
459 /// used by register scavenger to determine what registers are free.
460 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
462 /// getSubReg - Returns the physical register number of sub-register "Index"
463 /// for physical register RegNo. Return zero if the sub-register does not
465 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
467 /// getMatchingSuperReg - Return a super-register of the specified register
468 /// Reg so its sub-register of index SubIdx is Reg.
469 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
470 const TargetRegisterClass *RC) const {
471 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
472 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
477 /// getMatchingSuperRegClass - Return a subclass of the specified register
478 /// class A so that each register in it has a sub-register of the
479 /// specified sub-register index which is in the specified register class B.
480 virtual const TargetRegisterClass *
481 getMatchingSuperRegClass(const TargetRegisterClass *A,
482 const TargetRegisterClass *B, unsigned Idx) const {
486 //===--------------------------------------------------------------------===//
487 // Register Class Information
490 /// Register class iterators
492 regclass_iterator regclass_begin() const { return RegClassBegin; }
493 regclass_iterator regclass_end() const { return RegClassEnd; }
495 unsigned getNumRegClasses() const {
496 return (unsigned)(regclass_end()-regclass_begin());
499 /// getRegClass - Returns the register class associated with the enumeration
500 /// value. See class TargetOperandInfo.
501 const TargetRegisterClass *getRegClass(unsigned i) const {
502 assert(i <= getNumRegClasses() && "Register Class ID out of range");
503 return i ? RegClassBegin[i - 1] : NULL;
506 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
507 /// values. If a target supports multiple different pointer register classes,
508 /// kind specifies which one is indicated.
509 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
510 assert(0 && "Target didn't implement getPointerRegClass!");
511 return 0; // Must return a value in order to compile with VS 2005
514 /// getCrossCopyRegClass - Returns a legal register class to copy a register
515 /// in the specified class to or from. Returns NULL if it is possible to copy
516 /// between a two registers of the specified class.
517 virtual const TargetRegisterClass *
518 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
522 /// getAllocationOrder - Returns the register allocation order for a specified
523 /// register class in the form of a pair of TargetRegisterClass iterators.
524 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
525 getAllocationOrder(const TargetRegisterClass *RC,
526 unsigned HintType, unsigned HintReg,
527 const MachineFunction &MF) const {
528 return std::make_pair(RC->allocation_order_begin(MF),
529 RC->allocation_order_end(MF));
532 /// ResolveRegAllocHint - Resolves the specified register allocation hint
533 /// to a physical register. Returns the physical register if it is successful.
534 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
535 const MachineFunction &MF) const {
536 if (Type == 0 && Reg && isPhysicalRegister(Reg))
541 /// UpdateRegAllocHint - A callback to allow target a chance to update
542 /// register allocation hints when a register is "changed" (e.g. coalesced)
543 /// to another register. e.g. On ARM, some virtual registers should target
544 /// register pairs, if one of pair is coalesced to another register, the
545 /// allocation hint of the other half of the pair should be changed to point
546 /// to the new register.
547 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
548 MachineFunction &MF) const {
552 /// targetHandlesStackFrameRounding - Returns true if the target is
553 /// responsible for rounding up the stack frame (probably at emitPrologue
555 virtual bool targetHandlesStackFrameRounding() const {
559 /// requiresRegisterScavenging - returns true if the target requires (and can
560 /// make use of) the register scavenger.
561 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
565 /// requiresFrameIndexScavenging - returns true if the target requires post
566 /// PEI scavenging of registers for materializing frame index constants.
567 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
571 /// hasFP - Return true if the specified function should have a dedicated
572 /// frame pointer register. For most targets this is true only if the function
573 /// has variable sized allocas or if frame pointer elimination is disabled.
574 virtual bool hasFP(const MachineFunction &MF) const = 0;
576 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
577 /// not required, we reserve argument space for call sites in the function
578 /// immediately on entry to the current function. This eliminates the need for
579 /// add/sub sp brackets around call sites. Returns true if the call frame is
580 /// included as part of the stack frame.
581 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
585 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
586 /// the stack frame of the given function for the specified register. e.g. On
587 /// x86, if the frame register is required, the first fixed stack object is
588 /// reserved as its spill slot. This tells PEI not to create a new stack frame
589 /// object for the given register. It should be called only after
590 /// processFunctionBeforeCalleeSavedScan().
591 virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
592 int &FrameIdx) const {
596 /// needsStackRealignment - true if storage within the function requires the
597 /// stack pointer to be aligned more than the normal calling convention calls
599 virtual bool needsStackRealignment(const MachineFunction &MF) const {
603 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
604 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
605 /// targets use pseudo instructions in order to abstract away the difference
606 /// between operating with a frame pointer and operating without, through the
607 /// use of these two instructions.
609 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
610 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
612 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
613 /// code insertion to eliminate call frame setup and destroy pseudo
614 /// instructions (but only if the Target is using them). It is responsible
615 /// for eliminating these instructions, replacing them with concrete
616 /// instructions. This method need only be implemented if using call frame
617 /// setup/destroy pseudo instructions.
620 eliminateCallFramePseudoInstr(MachineFunction &MF,
621 MachineBasicBlock &MBB,
622 MachineBasicBlock::iterator MI) const {
623 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
624 "eliminateCallFramePseudoInstr must be implemented if using"
625 " call frame setup/destroy pseudo instructions!");
626 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
629 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
630 /// before PrologEpilogInserter scans the physical registers used to determine
631 /// what callee saved registers should be spilled. This method is optional.
632 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
633 RegScavenger *RS = NULL) const {
637 /// processFunctionBeforeFrameFinalized - This method is called immediately
638 /// before the specified functions frame layout (MF.getFrameInfo()) is
639 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
640 /// replaced with direct constants. This method is optional.
642 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
645 /// saveScavengerRegister - Spill the register so it can be used by the
646 /// register scavenger. Return true if the register was spilled, false
647 /// otherwise. If this function does not spill the register, the scavenger
648 /// will instead spill it to the emergency spill slot.
650 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
651 MachineBasicBlock::iterator I,
652 MachineBasicBlock::iterator &UseMI,
653 const TargetRegisterClass *RC,
654 unsigned Reg) const {return false;}
656 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
657 /// frame indices from instructions which may use them. The instruction
658 /// referenced by the iterator contains an MO_FrameIndex operand which must be
659 /// eliminated by this method. This method may modify or replace the
660 /// specified instruction, as long as it keeps the iterator pointing the the
661 /// finished product. SPAdj is the SP adjustment due to call frame setup
664 /// When -enable-frame-index-scavenging is enabled, the virtual register
665 /// allocated for this frame index is returned and its value is stored in
667 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
668 int SPAdj, int *Value = NULL,
669 RegScavenger *RS=NULL) const = 0;
671 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
673 virtual void emitPrologue(MachineFunction &MF) const = 0;
674 virtual void emitEpilogue(MachineFunction &MF,
675 MachineBasicBlock &MBB) const = 0;
677 //===--------------------------------------------------------------------===//
678 /// Debug information queries.
680 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
681 /// number. Returns -1 if there is no equivalent value. The second
682 /// parameter allows targets to use different numberings for EH info and
684 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
686 /// getFrameRegister - This method should return the register used as a base
687 /// for values allocated in the current stack frame.
688 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
690 /// getFrameIndexOffset - Returns the displacement from the frame register to
691 /// the stack frame of the specified index.
692 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
694 /// getRARegister - This method should return the register where the return
695 /// address can be found.
696 virtual unsigned getRARegister() const = 0;
698 /// getInitialFrameState - Returns a list of machine moves that are assumed
699 /// on entry to all functions. Note that LabelID is ignored (assumed to be
700 /// the beginning of the function.)
701 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
705 // This is useful when building IndexedMaps keyed on virtual registers
706 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
707 unsigned operator()(unsigned Reg) const {
708 return Reg - TargetRegisterInfo::FirstVirtualRegister;
712 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
713 /// if there is no common subclass.
714 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
715 const TargetRegisterClass *B);
717 } // End llvm namespace