1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
31 template<class T> class SmallVectorImpl;
34 /// TargetRegisterDesc - This record contains all of the information known about
35 /// a particular register. The Overlaps field contains a pointer to a zero
36 /// terminated array of registers that this register aliases, starting with
37 /// itself. This is needed for architectures like X86 which have AL alias AX
38 /// alias EAX. The SubRegs field is a zero terminated array of registers that
39 /// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
40 /// AX. The SuperRegs field is a zero terminated array of registers that are
41 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
44 struct TargetRegisterDesc {
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *Overlaps; // Overlapping registers, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
51 class TargetRegisterClass {
53 typedef const unsigned* iterator;
54 typedef const unsigned* const_iterator;
56 typedef const EVT* vt_iterator;
57 typedef const TargetRegisterClass* const * sc_iterator;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const sc_iterator SubRegClasses;
65 const sc_iterator SuperRegClasses;
66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
68 const iterator RegsBegin, RegsEnd;
69 DenseSet<unsigned> RegSet;
71 TargetRegisterClass(unsigned id,
74 const TargetRegisterClass * const *subcs,
75 const TargetRegisterClass * const *supcs,
76 const TargetRegisterClass * const *subregcs,
77 const TargetRegisterClass * const *superregcs,
78 unsigned RS, unsigned Al, int CC,
79 iterator RB, iterator RE)
80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
81 SubRegClasses(subregcs), SuperRegClasses(superregcs),
82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
86 virtual ~TargetRegisterClass() {} // Allow subclasses
88 /// getID() - Return the register class ID number.
90 unsigned getID() const { return ID; }
92 /// getName() - Return the register class name for debugging.
94 const char *getName() const { return Name; }
96 /// begin/end - Return all of the registers in this class.
98 iterator begin() const { return RegsBegin; }
99 iterator end() const { return RegsEnd; }
101 /// getNumRegs - Return the number of registers in this class.
103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
105 /// getRegister - Return the specified register in the class.
107 unsigned getRegister(unsigned i) const {
108 assert(i < getNumRegs() && "Register number out of range!");
112 /// contains - Return true if the specified register is included in this
113 /// register class. This does not include virtual registers.
114 bool contains(unsigned Reg) const {
115 return RegSet.count(Reg);
118 /// contains - Return true if both registers are in this class.
119 bool contains(unsigned Reg1, unsigned Reg2) const {
120 return contains(Reg1) && contains(Reg2);
123 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
125 bool hasType(EVT vt) const {
126 for(int i = 0; VTs[i] != MVT::Other; ++i)
132 /// vt_begin / vt_end - Loop over all of the value types that can be
133 /// represented by values in this register class.
134 vt_iterator vt_begin() const {
138 vt_iterator vt_end() const {
140 while (*I != MVT::Other) ++I;
144 /// subregclasses_begin / subregclasses_end - Loop over all of
145 /// the subreg register classes of this register class.
146 sc_iterator subregclasses_begin() const {
147 return SubRegClasses;
150 sc_iterator subregclasses_end() const {
151 sc_iterator I = SubRegClasses;
152 while (*I != NULL) ++I;
156 /// getSubRegisterRegClass - Return the register class of subregisters with
157 /// index SubIdx, or NULL if no such class exists.
158 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
159 assert(SubIdx>0 && "Invalid subregister index");
160 return SubRegClasses[SubIdx-1];
163 /// superregclasses_begin / superregclasses_end - Loop over all of
164 /// the superreg register classes of this register class.
165 sc_iterator superregclasses_begin() const {
166 return SuperRegClasses;
169 sc_iterator superregclasses_end() const {
170 sc_iterator I = SuperRegClasses;
171 while (*I != NULL) ++I;
175 /// hasSubClass - return true if the specified TargetRegisterClass
176 /// is a proper subset of this TargetRegisterClass.
177 bool hasSubClass(const TargetRegisterClass *cs) const {
178 for (int i = 0; SubClasses[i] != NULL; ++i)
179 if (SubClasses[i] == cs)
184 /// subclasses_begin / subclasses_end - Loop over all of the classes
185 /// that are proper subsets of this register class.
186 sc_iterator subclasses_begin() const {
190 sc_iterator subclasses_end() const {
191 sc_iterator I = SubClasses;
192 while (*I != NULL) ++I;
196 /// hasSuperClass - return true if the specified TargetRegisterClass is a
197 /// proper superset of this TargetRegisterClass.
198 bool hasSuperClass(const TargetRegisterClass *cs) const {
199 for (int i = 0; SuperClasses[i] != NULL; ++i)
200 if (SuperClasses[i] == cs)
205 /// superclasses_begin / superclasses_end - Loop over all of the classes
206 /// that are proper supersets of this register class.
207 sc_iterator superclasses_begin() const {
211 sc_iterator superclasses_end() const {
212 sc_iterator I = SuperClasses;
213 while (*I != NULL) ++I;
217 /// isASubClass - return true if this TargetRegisterClass is a subset
218 /// class of at least one other TargetRegisterClass.
219 bool isASubClass() const {
220 return SuperClasses[0] != 0;
223 /// allocation_order_begin/end - These methods define a range of registers
224 /// which specify the registers in this class that are valid to register
225 /// allocate, and the preferred order to allocate them in. For example,
226 /// callee saved registers should be at the end of the list, because it is
227 /// cheaper to allocate caller saved registers.
229 /// These methods take a MachineFunction argument, which can be used to tune
230 /// the allocatable registers based on the characteristics of the function,
231 /// subtarget, or other criteria.
233 /// Register allocators should account for the fact that an allocation
234 /// order iterator may return a reserved register and always check
235 /// if the register is allocatable (getAllocatableSet()) before using it.
237 /// By default, these methods return all registers in the class.
239 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
242 virtual iterator allocation_order_end(const MachineFunction &MF) const {
246 /// getSize - Return the size of the register in bytes, which is also the size
247 /// of a stack slot allocated to hold a spilled copy of this register.
248 unsigned getSize() const { return RegSize; }
250 /// getAlignment - Return the minimum required alignment for a register of
252 unsigned getAlignment() const { return Alignment; }
254 /// getCopyCost - Return the cost of copying a value between two registers in
255 /// this class. A negative number means the register class is very expensive
256 /// to copy e.g. status flag register classes.
257 int getCopyCost() const { return CopyCost; }
261 /// TargetRegisterInfo base class - We assume that the target defines a static
262 /// array of TargetRegisterDesc objects that represent all of the machine
263 /// registers that the target has. As such, we simply have to track a pointer
264 /// to this array so that we can turn register number into a register
267 class TargetRegisterInfo {
269 const unsigned* SubregHash;
270 const unsigned SubregHashSize;
271 const unsigned* AliasesHash;
272 const unsigned AliasesHashSize;
274 typedef const TargetRegisterClass * const * regclass_iterator;
276 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
277 const char *const *SubRegIndexNames; // Names of subreg indexes.
278 unsigned NumRegs; // Number of entries in the array
280 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
282 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
285 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
286 regclass_iterator RegClassBegin,
287 regclass_iterator RegClassEnd,
288 const char *const *subregindexnames,
289 int CallFrameSetupOpcode = -1,
290 int CallFrameDestroyOpcode = -1,
291 const unsigned* subregs = 0,
292 const unsigned subregsize = 0,
293 const unsigned* aliases = 0,
294 const unsigned aliasessize = 0);
295 virtual ~TargetRegisterInfo();
298 // Register numbers can represent physical registers, virtual registers, and
299 // sometimes stack slots. The unsigned values are divided into these ranges:
301 // 0 Not a register, can be used as a sentinel.
302 // [1;2^30) Physical registers assigned by TableGen.
303 // [2^30;2^31) Stack slots. (Rarely used.)
304 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
306 // Further sentinels can be allocated from the small negative integers.
307 // DenseMapInfo<unsigned> uses -1u and -2u.
309 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
310 /// frame index in a variable that normally holds a register. isStackSlot()
311 /// returns true if Reg is in the range used for stack slots.
313 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
314 /// slots, so if a variable may contains a stack slot, always check
315 /// isStackSlot() first.
317 static bool isStackSlot(unsigned Reg) {
318 return int(Reg) >= (1 << 30);
321 /// stackSlot2Index - Compute the frame index from a register value
322 /// representing a stack slot.
323 static int stackSlot2Index(unsigned Reg) {
324 assert(isStackSlot(Reg) && "Not a stack slot");
325 return int(Reg - (1u << 30));
328 /// index2StackSlot - Convert a non-negative frame index to a stack slot
330 static unsigned index2StackSlot(int FI) {
331 assert(FI >= 0 && "Cannot hold a negative frame index.");
332 return FI + (1u << 30);
335 /// isPhysicalRegister - Return true if the specified register number is in
336 /// the physical register namespace.
337 static bool isPhysicalRegister(unsigned Reg) {
338 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
342 /// isVirtualRegister - Return true if the specified register number is in
343 /// the virtual register namespace.
344 static bool isVirtualRegister(unsigned Reg) {
345 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
349 /// virtReg2Index - Convert a virtual register number to a 0-based index.
350 /// The first virtual register in a function will get the index 0.
351 static unsigned virtReg2Index(unsigned Reg) {
352 assert(isVirtualRegister(Reg) && "Not a virtual register");
353 return Reg - (1u << 31);
356 /// index2VirtReg - Convert a 0-based index to a virtual register number.
357 /// This is the inverse operation of VirtReg2IndexFunctor below.
358 static unsigned index2VirtReg(unsigned Index) {
359 return Index + (1u << 31);
362 /// getMinimalPhysRegClass - Returns the Register Class of a physical
363 /// register of the given type, picking the most sub register class of
364 /// the right type that contains this physreg.
365 const TargetRegisterClass *
366 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
368 /// getAllocatableSet - Returns a bitset indexed by register number
369 /// indicating if a register is allocatable or not. If a register class is
370 /// specified, returns the subset for the class.
371 BitVector getAllocatableSet(const MachineFunction &MF,
372 const TargetRegisterClass *RC = NULL) const;
374 const TargetRegisterDesc &operator[](unsigned RegNo) const {
375 assert(RegNo < NumRegs &&
376 "Attempting to access record for invalid register number!");
380 /// Provide a get method, equivalent to [], but more useful if we have a
381 /// pointer to this object.
383 const TargetRegisterDesc &get(unsigned RegNo) const {
384 return operator[](RegNo);
387 /// getAliasSet - Return the set of registers aliased by the specified
388 /// register, or a null list of there are none. The list returned is zero
391 const unsigned *getAliasSet(unsigned RegNo) const {
392 // The Overlaps set always begins with Reg itself.
393 return get(RegNo).Overlaps + 1;
396 /// getOverlaps - Return a list of registers that overlap Reg, including
397 /// itself. This is the same as the alias set except Reg is included in the
399 /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
401 const unsigned *getOverlaps(unsigned RegNo) const {
402 return get(RegNo).Overlaps;
405 /// getSubRegisters - Return the list of registers that are sub-registers of
406 /// the specified register, or a null list of there are none. The list
407 /// returned is zero terminated and sorted according to super-sub register
408 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
410 const unsigned *getSubRegisters(unsigned RegNo) const {
411 return get(RegNo).SubRegs;
414 /// getSuperRegisters - Return the list of registers that are super-registers
415 /// of the specified register, or a null list of there are none. The list
416 /// returned is zero terminated and sorted according to super-sub register
417 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
419 const unsigned *getSuperRegisters(unsigned RegNo) const {
420 return get(RegNo).SuperRegs;
423 /// getName - Return the human-readable symbolic target-specific name for the
424 /// specified physical register.
425 const char *getName(unsigned RegNo) const {
426 return get(RegNo).Name;
429 /// getNumRegs - Return the number of registers this target has (useful for
430 /// sizing arrays holding per register information)
431 unsigned getNumRegs() const {
435 /// getSubRegIndexName - Return the human-readable symbolic target-specific
436 /// name for the specified SubRegIndex.
437 const char *getSubRegIndexName(unsigned SubIdx) const {
438 assert(SubIdx && "This is not a subregister index");
439 return SubRegIndexNames[SubIdx-1];
442 /// regsOverlap - Returns true if the two registers are equal or alias each
443 /// other. The registers may be virtual register.
444 bool regsOverlap(unsigned regA, unsigned regB) const {
448 if (isVirtualRegister(regA) || isVirtualRegister(regB))
451 // regA and regB are distinct physical registers. Do they alias?
452 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
453 unsigned ProbeAmt = 0;
454 while (AliasesHash[index*2] != 0 &&
455 AliasesHash[index*2+1] != 0) {
456 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
459 index = (index + ProbeAmt) & (AliasesHashSize-1);
466 /// isSubRegister - Returns true if regB is a sub-register of regA.
468 bool isSubRegister(unsigned regA, unsigned regB) const {
469 // SubregHash is a simple quadratically probed hash table.
470 size_t index = (regA + regB * 37) & (SubregHashSize-1);
471 unsigned ProbeAmt = 2;
472 while (SubregHash[index*2] != 0 &&
473 SubregHash[index*2+1] != 0) {
474 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
477 index = (index + ProbeAmt) & (SubregHashSize-1);
484 /// isSuperRegister - Returns true if regB is a super-register of regA.
486 bool isSuperRegister(unsigned regA, unsigned regB) const {
487 return isSubRegister(regB, regA);
490 /// getCalleeSavedRegs - Return a null-terminated list of all of the
491 /// callee saved registers on this target. The register should be in the
492 /// order of desired callee-save stack frame offset. The first register is
493 /// closed to the incoming stack pointer if stack grows down, and vice versa.
494 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
498 /// getReservedRegs - Returns a bitset indexed by physical register number
499 /// indicating if a register is a special register that has particular uses
500 /// and should be considered unavailable at all times, e.g. SP, RA. This is
501 /// used by register scavenger to determine what registers are free.
502 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
504 /// getSubReg - Returns the physical register number of sub-register "Index"
505 /// for physical register RegNo. Return zero if the sub-register does not
507 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
509 /// getSubRegIndex - For a given register pair, return the sub-register index
510 /// if the second register is a sub-register of the first. Return zero
512 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
514 /// getMatchingSuperReg - Return a super-register of the specified register
515 /// Reg so its sub-register of index SubIdx is Reg.
516 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
517 const TargetRegisterClass *RC) const {
518 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
519 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
524 /// canCombineSubRegIndices - Given a register class and a list of
525 /// subregister indices, return true if it's possible to combine the
526 /// subregister indices into one that corresponds to a larger
527 /// subregister. Return the new subregister index by reference. Note the
528 /// new index may be zero if the given subregisters can be combined to
529 /// form the whole register.
530 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
531 SmallVectorImpl<unsigned> &SubIndices,
532 unsigned &NewSubIdx) const {
536 /// getMatchingSuperRegClass - Return a subclass of the specified register
537 /// class A so that each register in it has a sub-register of the
538 /// specified sub-register index which is in the specified register class B.
539 virtual const TargetRegisterClass *
540 getMatchingSuperRegClass(const TargetRegisterClass *A,
541 const TargetRegisterClass *B, unsigned Idx) const {
545 /// composeSubRegIndices - Return the subregister index you get from composing
546 /// two subregister indices.
548 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
549 /// returns c. Note that composeSubRegIndices does not tell you about illegal
550 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
551 /// b, composeSubRegIndices doesn't tell you.
553 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
554 /// ssub_0:S0 - ssub_3:S3 subregs.
555 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
557 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
558 // This default implementation is correct for most targets.
562 //===--------------------------------------------------------------------===//
563 // Register Class Information
566 /// Register class iterators
568 regclass_iterator regclass_begin() const { return RegClassBegin; }
569 regclass_iterator regclass_end() const { return RegClassEnd; }
571 unsigned getNumRegClasses() const {
572 return (unsigned)(regclass_end()-regclass_begin());
575 /// getRegClass - Returns the register class associated with the enumeration
576 /// value. See class TargetOperandInfo.
577 const TargetRegisterClass *getRegClass(unsigned i) const {
578 assert(i < getNumRegClasses() && "Register Class ID out of range");
579 return RegClassBegin[i];
582 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
583 /// values. If a target supports multiple different pointer register classes,
584 /// kind specifies which one is indicated.
585 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
586 assert(0 && "Target didn't implement getPointerRegClass!");
587 return 0; // Must return a value in order to compile with VS 2005
590 /// getCrossCopyRegClass - Returns a legal register class to copy a register
591 /// in the specified class to or from. Returns NULL if it is possible to copy
592 /// between a two registers of the specified class.
593 virtual const TargetRegisterClass *
594 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
598 /// getRegPressureLimit - Return the register pressure "high water mark" for
599 /// the specific register class. The scheduler is in high register pressure
600 /// mode (for the specific register class) if it goes over the limit.
601 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
602 MachineFunction &MF) const {
606 /// getAllocationOrder - Returns the register allocation order for a specified
607 /// register class in the form of a pair of TargetRegisterClass iterators.
608 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
609 getAllocationOrder(const TargetRegisterClass *RC,
610 unsigned HintType, unsigned HintReg,
611 const MachineFunction &MF) const {
612 return std::make_pair(RC->allocation_order_begin(MF),
613 RC->allocation_order_end(MF));
616 /// ResolveRegAllocHint - Resolves the specified register allocation hint
617 /// to a physical register. Returns the physical register if it is successful.
618 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
619 const MachineFunction &MF) const {
620 if (Type == 0 && Reg && isPhysicalRegister(Reg))
625 /// UpdateRegAllocHint - A callback to allow target a chance to update
626 /// register allocation hints when a register is "changed" (e.g. coalesced)
627 /// to another register. e.g. On ARM, some virtual registers should target
628 /// register pairs, if one of pair is coalesced to another register, the
629 /// allocation hint of the other half of the pair should be changed to point
630 /// to the new register.
631 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
632 MachineFunction &MF) const {
636 /// requiresRegisterScavenging - returns true if the target requires (and can
637 /// make use of) the register scavenger.
638 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
642 /// useFPForScavengingIndex - returns true if the target wants to use
643 /// frame pointer based accesses to spill to the scavenger emergency spill
645 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
649 /// requiresFrameIndexScavenging - returns true if the target requires post
650 /// PEI scavenging of registers for materializing frame index constants.
651 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
655 /// requiresVirtualBaseRegisters - Returns true if the target wants the
656 /// LocalStackAllocation pass to be run and virtual base registers
657 /// used for more efficient stack access.
658 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
662 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
663 /// the stack frame of the given function for the specified register. e.g. On
664 /// x86, if the frame register is required, the first fixed stack object is
665 /// reserved as its spill slot. This tells PEI not to create a new stack frame
666 /// object for the given register. It should be called only after
667 /// processFunctionBeforeCalleeSavedScan().
668 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
669 int &FrameIdx) const {
673 /// needsStackRealignment - true if storage within the function requires the
674 /// stack pointer to be aligned more than the normal calling convention calls
676 virtual bool needsStackRealignment(const MachineFunction &MF) const {
680 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
681 /// index in the instruction, if there is one.
682 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
687 /// needsFrameBaseReg - Returns true if the instruction's frame index
688 /// reference would be better served by a base register other than FP
689 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
690 /// references it should create new base registers for.
691 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
695 /// materializeFrameBaseRegister - Insert defining instruction(s) for
696 /// BaseReg to be a pointer to FrameIdx before insertion point I.
697 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
698 unsigned BaseReg, int FrameIdx,
699 int64_t Offset) const {
700 assert(0 && "materializeFrameBaseRegister does not exist on this target");
703 /// resolveFrameIndex - Resolve a frame index operand of an instruction
704 /// to reference the indicated base register plus offset instead.
705 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
706 unsigned BaseReg, int64_t Offset) const {
707 assert(0 && "resolveFrameIndex does not exist on this target");
710 /// isFrameOffsetLegal - Determine whether a given offset immediate is
711 /// encodable to resolve a frame index.
712 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
713 int64_t Offset) const {
714 assert(0 && "isFrameOffsetLegal does not exist on this target");
715 return false; // Must return a value in order to compile with VS 2005
718 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
719 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
720 /// targets use pseudo instructions in order to abstract away the difference
721 /// between operating with a frame pointer and operating without, through the
722 /// use of these two instructions.
724 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
725 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
727 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
728 /// code insertion to eliminate call frame setup and destroy pseudo
729 /// instructions (but only if the Target is using them). It is responsible
730 /// for eliminating these instructions, replacing them with concrete
731 /// instructions. This method need only be implemented if using call frame
732 /// setup/destroy pseudo instructions.
735 eliminateCallFramePseudoInstr(MachineFunction &MF,
736 MachineBasicBlock &MBB,
737 MachineBasicBlock::iterator MI) const {
738 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
739 "eliminateCallFramePseudoInstr must be implemented if using"
740 " call frame setup/destroy pseudo instructions!");
741 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
745 /// saveScavengerRegister - Spill the register so it can be used by the
746 /// register scavenger. Return true if the register was spilled, false
747 /// otherwise. If this function does not spill the register, the scavenger
748 /// will instead spill it to the emergency spill slot.
750 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
751 MachineBasicBlock::iterator I,
752 MachineBasicBlock::iterator &UseMI,
753 const TargetRegisterClass *RC,
754 unsigned Reg) const {
758 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
759 /// frame indices from instructions which may use them. The instruction
760 /// referenced by the iterator contains an MO_FrameIndex operand which must be
761 /// eliminated by this method. This method may modify or replace the
762 /// specified instruction, as long as it keeps the iterator pointing at the
763 /// finished product. SPAdj is the SP adjustment due to call frame setup
765 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
766 int SPAdj, RegScavenger *RS=NULL) const = 0;
768 //===--------------------------------------------------------------------===//
769 /// Debug information queries.
771 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
772 /// number. Returns -1 if there is no equivalent value. The second
773 /// parameter allows targets to use different numberings for EH info and
775 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
777 /// getFrameRegister - This method should return the register used as a base
778 /// for values allocated in the current stack frame.
779 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
781 /// getRARegister - This method should return the register where the return
782 /// address can be found.
783 virtual unsigned getRARegister() const = 0;
787 // This is useful when building IndexedMaps keyed on virtual registers
788 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
789 unsigned operator()(unsigned Reg) const {
790 return TargetRegisterInfo::virtReg2Index(Reg);
794 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
795 /// if there is no common subclass.
796 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
797 const TargetRegisterClass *B);
799 /// PrintReg - Helper class for printing registers on a raw_ostream.
800 /// Prints virtual and physical registers with or without a TRI instance.
803 /// %noreg - NoRegister
804 /// %vreg5 - a virtual register.
805 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
806 /// %EAX - a physical register
807 /// %physreg17 - a physical register when no TRI instance given.
809 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
812 const TargetRegisterInfo *TRI;
816 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
817 : TRI(tri), Reg(reg), SubIdx(subidx) {}
818 void print(raw_ostream&) const;
821 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
826 } // End llvm namespace