1 //===-- llvm/Target/TargetMachine.h - General Target Information -*- C++ -*-==//
3 // This file describes the general parts of a Target machine.
5 //===----------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_TARGETMACHINE_H
8 #define LLVM_TARGET_TARGETMACHINE_H
10 #include "llvm/Target/TargetData.h"
11 #include "Support/NonCopyable.h"
13 class TargetInstrInfo;
14 class TargetInstrDescriptor;
15 class TargetSchedInfo;
17 class TargetFrameInfo;
18 class TargetCacheInfo;
20 class MachineCodeEmitter;
25 //===----------------------------------------------------------------------===//
27 /// TargetMachine - Primary interface to the complete machine description for
28 /// the target machine. All target-specific information should be accessible
29 /// through this interface.
32 const std::string Name;
33 const TargetData DataLayout; // Calculates type size & alignment
35 TargetMachine(const TargetMachine&); // DO NOT IMPLEMENT
36 void operator=(const TargetMachine&); // DO NOT IMPLEMENT
38 TargetMachine(const std::string &name, // Can only create subclasses...
39 bool LittleEndian = false,
40 unsigned char PtrSize = 8, unsigned char PtrAl = 8,
41 unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
42 unsigned char LongAl = 8, unsigned char IntAl = 4,
43 unsigned char ShortAl = 2, unsigned char ByteAl = 1)
44 : Name(name), DataLayout(name, LittleEndian,
45 PtrSize, PtrAl, DoubleAl, FloatAl, LongAl,
46 IntAl, ShortAl, ByteAl) {}
48 virtual ~TargetMachine() {}
50 const std::string &getName() const { return Name; }
52 // Interfaces to the major aspects of target machine information:
53 // -- Instruction opcode and operand information
54 // -- Pipelines and scheduling information
55 // -- Register information
56 // -- Stack frame information
57 // -- Cache hierarchy information
58 // -- Machine-level optimization information (peephole only)
60 virtual const TargetInstrInfo& getInstrInfo() const = 0;
61 virtual const TargetSchedInfo& getSchedInfo() const = 0;
62 virtual const TargetRegInfo& getRegInfo() const = 0;
63 virtual const TargetFrameInfo& getFrameInfo() const = 0;
64 virtual const TargetCacheInfo& getCacheInfo() const = 0;
65 virtual const TargetOptInfo& getOptInfo() const = 0;
66 const TargetData &getTargetData() const { return DataLayout; }
68 /// getRegisterInfo - If register information is available, return it. If
69 /// not, return null. This is kept separate from RegInfo until RegInfo has
70 /// details of graph coloring register allocation removed from it.
72 virtual const MRegisterInfo* getRegisterInfo() const { return 0; }
74 // Data storage information
76 virtual unsigned findOptimalStorageSize(const Type* ty) const;
78 /// addPassesToJITCompile - Add passes to the specified pass manager to
79 /// implement a fast dynamic compiler for this target. Return true if this is
80 /// not supported for this target.
82 virtual bool addPassesToJITCompile(PassManager &PM) { return true; }
84 /// addPassesToEmitAssembly - Add passes to the specified pass manager to get
85 /// assembly langage code emitted. Typically this will involve several steps
86 /// of code generation. This method should return true if assembly emission
89 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
93 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
94 /// get machine code emitted. This uses a MAchineCodeEmitter object to handle
95 /// actually outputting the machine code and resolving things like the address
96 /// of functions. This method should returns true if machine code emission is
99 virtual bool addPassesToEmitMachineCode(PassManager &PM,
100 MachineCodeEmitter &MCE) {