1 //===-- llvm/Target/TargetMachine.h - General Target Information -*- C++ -*-==//
3 // This file describes the general parts of a Target machine.
5 //===----------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_TARGETMACHINE_H
8 #define LLVM_TARGET_TARGETMACHINE_H
10 #include "llvm/Target/TargetData.h"
11 #include "Support/NonCopyable.h"
13 class TargetInstrInfo;
14 class TargetInstrDescriptor;
15 class TargetSchedInfo;
17 class TargetFrameInfo;
18 class TargetCacheInfo;
20 class MachineCodeEmitter;
22 class FunctionPassManager;
26 //===----------------------------------------------------------------------===//
28 /// TargetMachine - Primary interface to the complete machine description for
29 /// the target machine. All target-specific information should be accessible
30 /// through this interface.
33 const std::string Name;
34 const TargetData DataLayout; // Calculates type size & alignment
36 TargetMachine(const TargetMachine&); // DO NOT IMPLEMENT
37 void operator=(const TargetMachine&); // DO NOT IMPLEMENT
39 TargetMachine(const std::string &name, // Can only create subclasses...
40 bool LittleEndian = false,
41 unsigned char PtrSize = 8, unsigned char PtrAl = 8,
42 unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
43 unsigned char LongAl = 8, unsigned char IntAl = 4,
44 unsigned char ShortAl = 2, unsigned char ByteAl = 1)
45 : Name(name), DataLayout(name, LittleEndian,
46 PtrSize, PtrAl, DoubleAl, FloatAl, LongAl,
47 IntAl, ShortAl, ByteAl) {}
49 virtual ~TargetMachine() {}
51 const std::string &getName() const { return Name; }
53 // Interfaces to the major aspects of target machine information:
54 // -- Instruction opcode and operand information
55 // -- Pipelines and scheduling information
56 // -- Register information
57 // -- Stack frame information
58 // -- Cache hierarchy information
59 // -- Machine-level optimization information (peephole only)
61 virtual const TargetInstrInfo& getInstrInfo() const = 0;
62 virtual const TargetSchedInfo& getSchedInfo() const = 0;
63 virtual const TargetRegInfo& getRegInfo() const = 0;
64 virtual const TargetFrameInfo& getFrameInfo() const = 0;
65 virtual const TargetCacheInfo& getCacheInfo() const = 0;
66 virtual const TargetOptInfo& getOptInfo() const = 0;
67 const TargetData &getTargetData() const { return DataLayout; }
69 /// getRegisterInfo - If register information is available, return it. If
70 /// not, return null. This is kept separate from RegInfo until RegInfo has
71 /// details of graph coloring register allocation removed from it.
73 virtual const MRegisterInfo* getRegisterInfo() const { return 0; }
75 // Data storage information
77 virtual unsigned findOptimalStorageSize(const Type* ty) const;
79 /// addPassesToJITCompile - Add passes to the specified pass manager to
80 /// implement a fast dynamic compiler for this target. Return true if this is
81 /// not supported for this target.
83 virtual bool addPassesToJITCompile(FunctionPassManager &PM) { return true; }
85 /// addPassesToEmitAssembly - Add passes to the specified pass manager to get
86 /// assembly langage code emitted. Typically this will involve several steps
87 /// of code generation. This method should return true if assembly emission
90 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
94 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
95 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
96 /// actually outputting the machine code and resolving things like the address
97 /// of functions. This method should returns true if machine code emission is
100 virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
101 MachineCodeEmitter &MCE) {