1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/CodeGen/RuntimeLibcalls.h"
27 #include "llvm/ADT/APFloat.h"
28 #include "llvm/ADT/STLExtras.h"
37 class TargetRegisterClass;
41 class MachineBasicBlock;
45 //===----------------------------------------------------------------------===//
46 /// TargetLowering - This class defines information used to lower LLVM code to
47 /// legal SelectionDAG operators that the target instruction selector can accept
50 /// This class also defines callbacks that targets must implement to lower
51 /// target-specific constructs to SelectionDAG operators.
53 class TargetLowering {
55 /// LegalizeAction - This enum indicates whether operations are valid for a
56 /// target, and if not, what action should be used to make them valid.
58 Legal, // The target natively supports this operation.
59 Promote, // This operation should be executed in a larger type.
60 Expand, // Try to expand this to other ops, otherwise use a libcall.
61 Custom // Use the LowerOperation hook to implement custom lowering.
64 enum OutOfRangeShiftAmount {
65 Undefined, // Oversized shift amounts are undefined (default).
66 Mask, // Shift amounts are auto masked (anded) to value size.
67 Extend // Oversized shift pulls in zeros or sign bits.
70 enum SetCCResultValue {
71 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
72 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
73 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
76 enum SchedPreference {
77 SchedulingForLatency, // Scheduling for shortest total latency.
78 SchedulingForRegPressure // Scheduling for lowest register pressure.
81 explicit TargetLowering(TargetMachine &TM);
82 virtual ~TargetLowering();
84 TargetMachine &getTargetMachine() const { return TM; }
85 const TargetData *getTargetData() const { return TD; }
87 bool isLittleEndian() const { return IsLittleEndian; }
88 MVT::ValueType getPointerTy() const { return PointerTy; }
89 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
90 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
92 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
94 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
96 /// isSelectExpensive - Return true if the select operation is expensive for
98 bool isSelectExpensive() const { return SelectIsExpensive; }
100 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
101 /// a sequence of several shifts, adds, and multiplies for this target.
102 bool isIntDivCheap() const { return IntDivIsCheap; }
104 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
106 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
108 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
110 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
112 /// getSetCCResultContents - For targets without boolean registers, this flag
113 /// returns information about the contents of the high-bits in the setcc
115 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
117 /// getSchedulingPreference - Return target scheduling preference.
118 SchedPreference getSchedulingPreference() const {
119 return SchedPreferenceInfo;
122 /// getRegClassFor - Return the register class that should be used for the
123 /// specified value type. This may only be called on legal types.
124 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
125 assert(!MVT::isExtendedVT(VT));
126 TargetRegisterClass *RC = RegClassForVT[VT];
127 assert(RC && "This value type is not natively supported!");
131 /// isTypeLegal - Return true if the target has native support for the
132 /// specified value type. This means that it has a register that directly
133 /// holds it without promotions or expansions.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
138 class ValueTypeActionImpl {
139 /// ValueTypeActions - This is a bitvector that contains two bits for each
140 /// value type, where the two bits correspond to the LegalizeAction enum.
141 /// This can be queried with "getTypeAction(VT)".
142 uint32_t ValueTypeActions[2];
144 ValueTypeActionImpl() {
145 ValueTypeActions[0] = ValueTypeActions[1] = 0;
147 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
148 ValueTypeActions[0] = RHS.ValueTypeActions[0];
149 ValueTypeActions[1] = RHS.ValueTypeActions[1];
152 LegalizeAction getTypeAction(MVT::ValueType VT) const {
153 if (MVT::isExtendedVT(VT)) return Expand;
154 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
156 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
157 assert(!MVT::isExtendedVT(VT));
158 assert(unsigned(VT >> 4) < array_lengthof(ValueTypeActions));
159 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
163 const ValueTypeActionImpl &getValueTypeActions() const {
164 return ValueTypeActions;
167 /// getTypeAction - Return how we should legalize values of this type, either
168 /// it is already legal (return 'Legal') or we need to promote it to a larger
169 /// type (return 'Promote'), or we need to expand it into multiple registers
170 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
171 LegalizeAction getTypeAction(MVT::ValueType VT) const {
172 return ValueTypeActions.getTypeAction(VT);
175 /// getTypeToTransformTo - For types supported by the target, this is an
176 /// identity function. For types that must be promoted to larger types, this
177 /// returns the larger type to promote to. For integer types that are larger
178 /// than the largest integer register, this contains one step in the expansion
179 /// to get to the smaller register. For illegal floating point types, this
180 /// returns the integer type to transform to.
181 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
182 if (MVT::isExtendedVT(VT))
183 return MVT::getVectorType(MVT::getVectorElementType(VT),
184 MVT::getVectorNumElements(VT) / 2);
186 return TransformToType[VT];
189 /// getTypeToExpandTo - For types supported by the target, this is an
190 /// identity function. For types that must be expanded (i.e. integer types
191 /// that are larger than the largest integer register or illegal floating
192 /// point types), this returns the largest legal type it will be expanded to.
193 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
194 assert(!MVT::isExtendedVT(VT));
196 switch (getTypeAction(VT)) {
200 VT = getTypeToTransformTo(VT);
203 assert(false && "Type is not legal nor is it to be expanded!");
210 /// getVectorTypeBreakdown - Vector types are broken down into some number of
211 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
212 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
213 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
215 /// This method returns the number of registers needed, and the VT for each
216 /// register. It also returns the VT and quantity of the intermediate values
217 /// before they are promoted/expanded.
219 unsigned getVectorTypeBreakdown(MVT::ValueType VT,
220 MVT::ValueType &IntermediateVT,
221 unsigned &NumIntermediates,
222 MVT::ValueType &RegisterVT) const;
224 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
225 legal_fpimm_iterator legal_fpimm_begin() const {
226 return LegalFPImmediates.begin();
228 legal_fpimm_iterator legal_fpimm_end() const {
229 return LegalFPImmediates.end();
232 /// isShuffleMaskLegal - Targets can use this to indicate that they only
233 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
234 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
235 /// are assumed to be legal.
236 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
240 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
241 /// used by Targets can use this to indicate if there is a suitable
242 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
244 virtual bool isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
246 SelectionDAG &DAG) const {
250 /// getOperationAction - Return how this operation should be treated: either
251 /// it is legal, needs to be promoted to a larger size, needs to be
252 /// expanded to some other code sequence, or the target has a custom expander
254 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
255 if (MVT::isExtendedVT(VT)) return Expand;
256 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
259 /// isOperationLegal - Return true if the specified operation is legal on this
261 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
262 return getOperationAction(Op, VT) == Legal ||
263 getOperationAction(Op, VT) == Custom;
266 /// getLoadXAction - Return how this load with extension should be treated:
267 /// either it is legal, needs to be promoted to a larger size, needs to be
268 /// expanded to some other code sequence, or the target has a custom expander
270 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
271 if (MVT::isExtendedVT(VT)) return Expand;
272 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
275 /// isLoadXLegal - Return true if the specified load with extension is legal
277 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
278 return getLoadXAction(LType, VT) == Legal ||
279 getLoadXAction(LType, VT) == Custom;
282 /// getStoreXAction - Return how this store with truncation should be treated:
283 /// either it is legal, needs to be promoted to a larger size, needs to be
284 /// expanded to some other code sequence, or the target has a custom expander
286 LegalizeAction getStoreXAction(MVT::ValueType VT) const {
287 if (MVT::isExtendedVT(VT)) return Expand;
288 return (LegalizeAction)((StoreXActions >> (2*VT)) & 3);
291 /// isStoreXLegal - Return true if the specified store with truncation is
292 /// legal on this target.
293 bool isStoreXLegal(MVT::ValueType VT) const {
294 return getStoreXAction(VT) == Legal || getStoreXAction(VT) == Custom;
297 /// getIndexedLoadAction - Return how the indexed load should be treated:
298 /// either it is legal, needs to be promoted to a larger size, needs to be
299 /// expanded to some other code sequence, or the target has a custom expander
302 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
303 if (MVT::isExtendedVT(VT)) return Expand;
304 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
307 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
309 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
310 return getIndexedLoadAction(IdxMode, VT) == Legal ||
311 getIndexedLoadAction(IdxMode, VT) == Custom;
314 /// getIndexedStoreAction - Return how the indexed store should be treated:
315 /// either it is legal, needs to be promoted to a larger size, needs to be
316 /// expanded to some other code sequence, or the target has a custom expander
319 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
320 if (MVT::isExtendedVT(VT)) return Expand;
321 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
324 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
326 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
327 return getIndexedStoreAction(IdxMode, VT) == Legal ||
328 getIndexedStoreAction(IdxMode, VT) == Custom;
331 /// getConvertAction - Return how the conversion should be treated:
332 /// either it is legal, needs to be promoted to a larger size, needs to be
333 /// expanded to some other code sequence, or the target has a custom expander
336 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
337 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 &&
338 "Table isn't big enough!");
339 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3);
342 /// isConvertLegal - Return true if the specified conversion is legal
344 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
345 return getConvertAction(FromVT, ToVT) == Legal ||
346 getConvertAction(FromVT, ToVT) == Custom;
349 /// getTypeToPromoteTo - If the action for this operation is to promote, this
350 /// method returns the ValueType to promote to.
351 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
352 assert(getOperationAction(Op, VT) == Promote &&
353 "This operation isn't promoted!");
355 // See if this has an explicit type specified.
356 std::map<std::pair<unsigned, MVT::ValueType>,
357 MVT::ValueType>::const_iterator PTTI =
358 PromoteToType.find(std::make_pair(Op, VT));
359 if (PTTI != PromoteToType.end()) return PTTI->second;
361 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
362 "Cannot autopromote this type, add it with AddPromotedToType.");
364 MVT::ValueType NVT = VT;
366 NVT = (MVT::ValueType)(NVT+1);
367 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
368 "Didn't find type to promote to!");
369 } while (!isTypeLegal(NVT) ||
370 getOperationAction(Op, NVT) == Promote);
374 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
375 /// This is fixed by the LLVM operations except for the pointer size. If
376 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
377 /// counterpart (e.g. structs), otherwise it will assert.
378 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
379 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
380 return VT == MVT::iPTR ? PointerTy : VT;
383 /// getRegisterType - Return the type of registers that this ValueType will
384 /// eventually require.
385 MVT::ValueType getRegisterType(MVT::ValueType VT) const {
386 if (!MVT::isExtendedVT(VT))
387 return RegisterTypeForVT[VT];
389 MVT::ValueType VT1, RegisterVT;
390 unsigned NumIntermediates;
391 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
395 /// getNumRegisters - Return the number of registers that this ValueType will
396 /// eventually require. This is one for any types promoted to live in larger
397 /// registers, but may be more than one for types (like i64) that are split
399 unsigned getNumRegisters(MVT::ValueType VT) const {
400 if (!MVT::isExtendedVT(VT))
401 return NumRegistersForVT[VT];
403 MVT::ValueType VT1, VT2;
404 unsigned NumIntermediates;
405 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
408 /// hasTargetDAGCombine - If true, the target has custom DAG combine
409 /// transformations that it can perform for the specified node.
410 bool hasTargetDAGCombine(ISD::NodeType NT) const {
411 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
414 /// This function returns the maximum number of store operations permitted
415 /// to replace a call to llvm.memset. The value is set by the target at the
416 /// performance threshold for such a replacement.
417 /// @brief Get maximum # of store operations permitted for llvm.memset
418 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
420 /// This function returns the maximum number of store operations permitted
421 /// to replace a call to llvm.memcpy. The value is set by the target at the
422 /// performance threshold for such a replacement.
423 /// @brief Get maximum # of store operations permitted for llvm.memcpy
424 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
426 /// This function returns the maximum number of store operations permitted
427 /// to replace a call to llvm.memmove. The value is set by the target at the
428 /// performance threshold for such a replacement.
429 /// @brief Get maximum # of store operations permitted for llvm.memmove
430 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
432 /// This function returns true if the target allows unaligned memory accesses.
433 /// This is used, for example, in situations where an array copy/move/set is
434 /// converted to a sequence of store operations. It's use helps to ensure that
435 /// such replacements don't generate code that causes an alignment error
436 /// (trap) on the target machine.
437 /// @brief Determine if the target supports unaligned memory accesses.
438 bool allowsUnalignedMemoryAccesses() const {
439 return allowUnalignedMemoryAccesses;
442 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
443 /// to implement llvm.setjmp.
444 bool usesUnderscoreSetJmp() const {
445 return UseUnderscoreSetJmp;
448 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
449 /// to implement llvm.longjmp.
450 bool usesUnderscoreLongJmp() const {
451 return UseUnderscoreLongJmp;
454 /// getStackPointerRegisterToSaveRestore - If a physical register, this
455 /// specifies the register that llvm.savestack/llvm.restorestack should save
457 unsigned getStackPointerRegisterToSaveRestore() const {
458 return StackPointerRegisterToSaveRestore;
461 /// getExceptionAddressRegister - If a physical register, this returns
462 /// the register that receives the exception address on entry to a landing
464 unsigned getExceptionAddressRegister() const {
465 return ExceptionPointerRegister;
468 /// getExceptionSelectorRegister - If a physical register, this returns
469 /// the register that receives the exception typeid on entry to a landing
471 unsigned getExceptionSelectorRegister() const {
472 return ExceptionSelectorRegister;
475 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
476 /// set, the default is 200)
477 unsigned getJumpBufSize() const {
481 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
482 /// (if never set, the default is 0)
483 unsigned getJumpBufAlignment() const {
484 return JumpBufAlignment;
487 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
488 /// limit. Any block whose size is greater should not be predicated.
489 virtual unsigned getIfCvtBlockSizeLimit() const {
490 return IfCvtBlockSizeLimit;
493 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
494 /// block to be considered for duplication. Any block whose size is greater
495 /// should not be duplicated to facilitate its predication.
496 virtual unsigned getIfCvtDupBlockSizeLimit() const {
497 return IfCvtDupBlockSizeLimit;
500 /// getPreIndexedAddressParts - returns true by value, base pointer and
501 /// offset pointer and addressing mode by reference if the node's address
502 /// can be legally represented as pre-indexed load / store address.
503 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
505 ISD::MemIndexedMode &AM,
510 /// getPostIndexedAddressParts - returns true by value, base pointer and
511 /// offset pointer and addressing mode by reference if this node can be
512 /// combined with a load / store to form a post-indexed load / store.
513 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
514 SDOperand &Base, SDOperand &Offset,
515 ISD::MemIndexedMode &AM,
520 //===--------------------------------------------------------------------===//
521 // TargetLowering Optimization Methods
524 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
525 /// SDOperands for returning information from TargetLowering to its clients
526 /// that want to combine
527 struct TargetLoweringOpt {
532 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
534 bool CombineTo(SDOperand O, SDOperand N) {
540 /// ShrinkDemandedConstant - Check to see if the specified operand of the
541 /// specified instruction is a constant integer. If so, check to see if there
542 /// are any bits set in the constant that are not demanded. If so, shrink the
543 /// constant and return true.
544 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
547 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
548 /// DemandedMask bits of the result of Op are ever used downstream. If we can
549 /// use this information to simplify Op, create a new simplified DAG node and
550 /// return true, returning the original and new nodes in Old and New.
551 /// Otherwise, analyze the expression and return a mask of KnownOne and
552 /// KnownZero bits for the expression (used to simplify the caller).
553 /// The KnownZero/One bits may only be accurate for those bits in the
555 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
556 uint64_t &KnownZero, uint64_t &KnownOne,
557 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
559 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
560 /// Mask are known to be either zero or one and return them in the
561 /// KnownZero/KnownOne bitsets.
562 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
566 const SelectionDAG &DAG,
567 unsigned Depth = 0) const;
569 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
570 /// targets that want to expose additional information about sign bits to the
572 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
573 unsigned Depth = 0) const;
575 struct DAGCombinerInfo {
576 void *DC; // The DAG Combiner object.
578 bool CalledByLegalizer;
582 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
583 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
585 bool isBeforeLegalize() const { return BeforeLegalize; }
586 bool isCalledByLegalizer() const { return CalledByLegalizer; }
588 void AddToWorklist(SDNode *N);
589 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
590 SDOperand CombineTo(SDNode *N, SDOperand Res);
591 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
594 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
595 /// and cc. If it is unable to simplify it, return a null SDOperand.
596 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
597 ISD::CondCode Cond, bool foldBooleans,
598 DAGCombinerInfo &DCI) const;
600 /// PerformDAGCombine - This method will be invoked for all target nodes and
601 /// for any target-independent nodes that the target has registered with
604 /// The semantics are as follows:
606 /// SDOperand.Val == 0 - No change was made
607 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
608 /// otherwise - N should be replaced by the returned Operand.
610 /// In addition, methods provided by DAGCombinerInfo may be used to perform
611 /// more complex transformations.
613 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
615 //===--------------------------------------------------------------------===//
616 // TargetLowering Configuration Methods - These methods should be invoked by
617 // the derived class constructor to configure this object for the target.
621 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
622 /// GOT for PC-relative code.
623 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
625 /// setShiftAmountType - Describe the type that should be used for shift
626 /// amounts. This type defaults to the pointer type.
627 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
629 /// setSetCCResultType - Describe the type that shoudl be used as the result
630 /// of a setcc operation. This defaults to the pointer type.
631 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
633 /// setSetCCResultContents - Specify how the target extends the result of a
634 /// setcc operation in a register.
635 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
637 /// setSchedulingPreference - Specify the target scheduling preference.
638 void setSchedulingPreference(SchedPreference Pref) {
639 SchedPreferenceInfo = Pref;
642 /// setShiftAmountFlavor - Describe how the target handles out of range shift
644 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
645 ShiftAmtHandling = OORSA;
648 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
649 /// use _setjmp to implement llvm.setjmp or the non _ version.
650 /// Defaults to false.
651 void setUseUnderscoreSetJmp(bool Val) {
652 UseUnderscoreSetJmp = Val;
655 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
656 /// use _longjmp to implement llvm.longjmp or the non _ version.
657 /// Defaults to false.
658 void setUseUnderscoreLongJmp(bool Val) {
659 UseUnderscoreLongJmp = Val;
662 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
663 /// specifies the register that llvm.savestack/llvm.restorestack should save
665 void setStackPointerRegisterToSaveRestore(unsigned R) {
666 StackPointerRegisterToSaveRestore = R;
669 /// setExceptionPointerRegister - If set to a physical register, this sets
670 /// the register that receives the exception address on entry to a landing
672 void setExceptionPointerRegister(unsigned R) {
673 ExceptionPointerRegister = R;
676 /// setExceptionSelectorRegister - If set to a physical register, this sets
677 /// the register that receives the exception typeid on entry to a landing
679 void setExceptionSelectorRegister(unsigned R) {
680 ExceptionSelectorRegister = R;
683 /// SelectIsExpensive - Tells the code generator not to expand operations
684 /// into sequences that use the select operations if possible.
685 void setSelectIsExpensive() { SelectIsExpensive = true; }
687 /// setIntDivIsCheap - Tells the code generator that integer divide is
688 /// expensive, and if possible, should be replaced by an alternate sequence
689 /// of instructions not containing an integer divide.
690 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
692 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
693 /// srl/add/sra for a signed divide by power of two, and let the target handle
695 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
697 /// addRegisterClass - Add the specified register class as an available
698 /// regclass for the specified value type. This indicates the selector can
699 /// handle values of that class natively.
700 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
701 assert(!MVT::isExtendedVT(VT));
702 AvailableRegClasses.push_back(std::make_pair(VT, RC));
703 RegClassForVT[VT] = RC;
706 /// computeRegisterProperties - Once all of the register classes are added,
707 /// this allows us to compute derived properties we expose.
708 void computeRegisterProperties();
710 /// setOperationAction - Indicate that the specified operation does not work
711 /// with the specified type and indicate what to do about it.
712 void setOperationAction(unsigned Op, MVT::ValueType VT,
713 LegalizeAction Action) {
714 assert(VT < 32 && Op < array_lengthof(OpActions) &&
715 "Table isn't big enough!");
716 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
717 OpActions[Op] |= (uint64_t)Action << VT*2;
720 /// setLoadXAction - Indicate that the specified load with extension does not
721 /// work with the with specified type and indicate what to do about it.
722 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
723 LegalizeAction Action) {
724 assert(VT < 32 && ExtType < array_lengthof(LoadXActions) &&
725 "Table isn't big enough!");
726 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
727 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
730 /// setStoreXAction - Indicate that the specified store with truncation does
731 /// not work with the with specified type and indicate what to do about it.
732 void setStoreXAction(MVT::ValueType VT, LegalizeAction Action) {
733 assert(VT < 32 && "Table isn't big enough!");
734 StoreXActions &= ~(uint64_t(3UL) << VT*2);
735 StoreXActions |= (uint64_t)Action << VT*2;
738 /// setIndexedLoadAction - Indicate that the specified indexed load does or
739 /// does not work with the with specified type and indicate what to do abort
740 /// it. NOTE: All indexed mode loads are initialized to Expand in
741 /// TargetLowering.cpp
742 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
743 LegalizeAction Action) {
744 assert(VT < 32 && IdxMode <
745 array_lengthof(IndexedModeActions[0]) &&
746 "Table isn't big enough!");
747 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
748 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
751 /// setIndexedStoreAction - Indicate that the specified indexed store does or
752 /// does not work with the with specified type and indicate what to do about
753 /// it. NOTE: All indexed mode stores are initialized to Expand in
754 /// TargetLowering.cpp
755 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
756 LegalizeAction Action) {
757 assert(VT < 32 && IdxMode <
758 array_lengthof(IndexedModeActions[1]) &&
759 "Table isn't big enough!");
760 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
761 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
764 /// setConvertAction - Indicate that the specified conversion does or does
765 /// not work with the with specified type and indicate what to do about it.
766 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT,
767 LegalizeAction Action) {
768 assert(FromVT < MVT::LAST_VALUETYPE && ToVT < 32 &&
769 "Table isn't big enough!");
770 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
771 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
774 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
775 /// promotion code defaults to trying a larger integer/fp until it can find
776 /// one that works. If that default is insufficient, this method can be used
777 /// by the target to override the default.
778 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
779 MVT::ValueType DestVT) {
780 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
783 /// addLegalFPImmediate - Indicate that this target can instruction select
784 /// the specified FP immediate natively.
785 void addLegalFPImmediate(const APFloat& Imm) {
786 LegalFPImmediates.push_back(Imm);
789 /// setTargetDAGCombine - Targets should invoke this method for each target
790 /// independent node that they want to provide a custom DAG combiner for by
791 /// implementing the PerformDAGCombine virtual method.
792 void setTargetDAGCombine(ISD::NodeType NT) {
793 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
796 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
797 /// bytes); default is 200
798 void setJumpBufSize(unsigned Size) {
802 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
803 /// alignment (in bytes); default is 0
804 void setJumpBufAlignment(unsigned Align) {
805 JumpBufAlignment = Align;
808 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
809 /// limit (in number of instructions); default is 2.
810 void setIfCvtBlockSizeLimit(unsigned Limit) {
811 IfCvtBlockSizeLimit = Limit;
814 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
815 /// of instructions) to be considered for code duplication during
816 /// if-conversion; default is 2.
817 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
818 IfCvtDupBlockSizeLimit = Limit;
823 //===--------------------------------------------------------------------===//
824 // Lowering methods - These methods must be implemented by targets so that
825 // the SelectionDAGLowering code knows how to lower these.
828 /// LowerArguments - This hook must be implemented to indicate how we should
829 /// lower the arguments for the specified function, into the specified DAG.
830 virtual std::vector<SDOperand>
831 LowerArguments(Function &F, SelectionDAG &DAG);
833 /// LowerCallTo - This hook lowers an abstract call to a function into an
834 /// actual call. This returns a pair of operands. The first element is the
835 /// return value for the function (if RetTy is not VoidTy). The second
836 /// element is the outgoing token chain.
837 struct ArgListEntry {
847 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
848 isSRet(false), isNest(false), isByVal(false) { }
850 typedef std::vector<ArgListEntry> ArgListTy;
851 virtual std::pair<SDOperand, SDOperand>
852 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned,
853 bool isVarArg, unsigned CallingConv, bool isTailCall,
854 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
856 /// LowerOperation - This callback is invoked for operations that are
857 /// unsupported by the target, which are registered to use 'custom' lowering,
858 /// and whose defined values are all legal.
859 /// If the target has no operations that require custom lowering, it need not
860 /// implement this. The default implementation of this aborts.
861 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
863 /// CustomPromoteOperation - This callback is invoked for operations that are
864 /// unsupported by the target, are registered to use 'custom' lowering, and
865 /// whose type needs to be promoted.
866 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
868 /// getTargetNodeName() - This method returns the name of a target specific
870 virtual const char *getTargetNodeName(unsigned Opcode) const;
872 //===--------------------------------------------------------------------===//
873 // Inline Asm Support hooks
876 enum ConstraintType {
877 C_Register, // Constraint represents a single register.
878 C_RegisterClass, // Constraint represents one or more registers.
879 C_Memory, // Memory constraint.
880 C_Other, // Something else.
881 C_Unknown // Unsupported constraint.
884 /// getConstraintType - Given a constraint, return the type of constraint it
885 /// is for this target.
886 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
889 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
890 /// return a list of registers that can be used to satisfy the constraint.
891 /// This should only be used for C_RegisterClass constraints.
892 virtual std::vector<unsigned>
893 getRegClassForInlineAsmConstraint(const std::string &Constraint,
894 MVT::ValueType VT) const;
896 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
897 /// {edx}), return the register number and the register class for the
900 /// Given a register class constraint, like 'r', if this corresponds directly
901 /// to an LLVM register class, return a register of 0 and the register class
904 /// This should only be used for C_Register constraints. On error,
905 /// this returns a register number of 0 and a null register class pointer..
906 virtual std::pair<unsigned, const TargetRegisterClass*>
907 getRegForInlineAsmConstraint(const std::string &Constraint,
908 MVT::ValueType VT) const;
911 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
912 /// vector. If it is invalid, don't add anything to Ops.
913 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
914 std::vector<SDOperand> &Ops,
917 //===--------------------------------------------------------------------===//
921 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
922 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
923 // instructions are special in various ways, which require special support to
924 // insert. The specified MachineInstr is created but not inserted into any
925 // basic blocks, and the scheduler passes ownership of it to this method.
926 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
927 MachineBasicBlock *MBB);
929 //===--------------------------------------------------------------------===//
930 // Addressing mode description hooks (used by LSR etc).
933 /// AddrMode - This represents an addressing mode of:
934 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
935 /// If BaseGV is null, there is no BaseGV.
936 /// If BaseOffs is zero, there is no base offset.
937 /// If HasBaseReg is false, there is no base register.
938 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
946 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
949 /// isLegalAddressingMode - Return true if the addressing mode represented by
950 /// AM is legal for this target, for a load/store of the specified type.
951 /// TODO: Handle pre/postinc as well.
952 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
954 //===--------------------------------------------------------------------===//
955 // Div utility functions
957 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
958 std::vector<SDNode*>* Created) const;
959 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
960 std::vector<SDNode*>* Created) const;
963 //===--------------------------------------------------------------------===//
964 // Runtime Library hooks
967 /// setLibcallName - Rename the default libcall routine name for the specified
969 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
970 LibcallRoutineNames[Call] = Name;
973 /// getLibcallName - Get the libcall routine name for the specified libcall.
975 const char *getLibcallName(RTLIB::Libcall Call) const {
976 return LibcallRoutineNames[Call];
979 /// setCmpLibcallCC - Override the default CondCode to be used to test the
980 /// result of the comparison libcall against zero.
981 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
982 CmpLibcallCCs[Call] = CC;
985 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
986 /// the comparison libcall against zero.
987 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
988 return CmpLibcallCCs[Call];
993 const TargetData *TD;
995 /// IsLittleEndian - True if this is a little endian target.
999 /// PointerTy - The type to use for pointers, usually i32 or i64.
1001 MVT::ValueType PointerTy;
1003 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1005 bool UsesGlobalOffsetTable;
1007 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1009 MVT::ValueType ShiftAmountTy;
1011 OutOfRangeShiftAmount ShiftAmtHandling;
1013 /// SelectIsExpensive - Tells the code generator not to expand operations
1014 /// into sequences that use the select operations if possible.
1015 bool SelectIsExpensive;
1017 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1018 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1019 /// a real cost model is in place. If we ever optimize for size, this will be
1020 /// set to true unconditionally.
1023 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1024 /// srl/add/sra for a signed divide by power of two, and let the target handle
1026 bool Pow2DivIsCheap;
1028 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
1030 MVT::ValueType SetCCResultTy;
1032 /// SetCCResultContents - Information about the contents of the high-bits in
1033 /// the result of a setcc comparison operation.
1034 SetCCResultValue SetCCResultContents;
1036 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1037 /// total cycles or lowest register usage.
1038 SchedPreference SchedPreferenceInfo;
1040 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1041 /// llvm.setjmp. Defaults to false.
1042 bool UseUnderscoreSetJmp;
1044 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1045 /// llvm.longjmp. Defaults to false.
1046 bool UseUnderscoreLongJmp;
1048 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1049 unsigned JumpBufSize;
1051 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1053 unsigned JumpBufAlignment;
1055 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1057 unsigned IfCvtBlockSizeLimit;
1059 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1060 /// duplicated during if-conversion.
1061 unsigned IfCvtDupBlockSizeLimit;
1063 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1064 /// specifies the register that llvm.savestack/llvm.restorestack should save
1066 unsigned StackPointerRegisterToSaveRestore;
1068 /// ExceptionPointerRegister - If set to a physical register, this specifies
1069 /// the register that receives the exception address on entry to a landing
1071 unsigned ExceptionPointerRegister;
1073 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1074 /// the register that receives the exception typeid on entry to a landing
1076 unsigned ExceptionSelectorRegister;
1078 /// RegClassForVT - This indicates the default register class to use for
1079 /// each ValueType the target supports natively.
1080 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1081 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1082 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
1084 /// TransformToType - For any value types we are promoting or expanding, this
1085 /// contains the value type that we are changing to. For Expanded types, this
1086 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1087 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1088 /// by the system, this holds the same type (e.g. i32 -> i32).
1089 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1091 /// OpActions - For each operation and each value type, keep a LegalizeAction
1092 /// that indicates how instruction selection should deal with the operation.
1093 /// Most operations are Legal (aka, supported natively by the target), but
1094 /// operations that are not should be described. Note that operations on
1095 /// non-legal value types are not described here.
1096 uint64_t OpActions[156];
1098 /// LoadXActions - For each load of load extension type and each value type,
1099 /// keep a LegalizeAction that indicates how instruction selection should deal
1101 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
1103 /// StoreXActions - For each store with truncation of each value type, keep a
1104 /// LegalizeAction that indicates how instruction selection should deal with
1106 uint64_t StoreXActions;
1108 /// IndexedModeActions - For each indexed mode and each value type, keep a
1109 /// pair of LegalizeAction that indicates how instruction selection should
1110 /// deal with the load / store.
1111 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1113 /// ConvertActions - For each conversion from source type to destination type,
1114 /// keep a LegalizeAction that indicates how instruction selection should
1115 /// deal with the conversion.
1116 /// Currently, this is used only for floating->floating conversions
1117 /// (FP_EXTEND and FP_ROUND).
1118 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1120 ValueTypeActionImpl ValueTypeActions;
1122 std::vector<APFloat> LegalFPImmediates;
1124 std::vector<std::pair<MVT::ValueType,
1125 TargetRegisterClass*> > AvailableRegClasses;
1127 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1128 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1129 /// which sets a bit in this array.
1130 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
1132 /// PromoteToType - For operations that must be promoted to a specific type,
1133 /// this holds the destination type. This map should be sparse, so don't hold
1136 /// Targets add entries to this map with AddPromotedToType(..), clients access
1137 /// this with getTypeToPromoteTo(..).
1138 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
1140 /// LibcallRoutineNames - Stores the name each libcall.
1142 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1144 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1145 /// of each of the comparison libcall against zero.
1146 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1149 /// When lowering %llvm.memset this field specifies the maximum number of
1150 /// store operations that may be substituted for the call to memset. Targets
1151 /// must set this value based on the cost threshold for that target. Targets
1152 /// should assume that the memset will be done using as many of the largest
1153 /// store operations first, followed by smaller ones, if necessary, per
1154 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1155 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1156 /// store. This only applies to setting a constant array of a constant size.
1157 /// @brief Specify maximum number of store instructions per memset call.
1158 unsigned maxStoresPerMemset;
1160 /// When lowering %llvm.memcpy this field specifies the maximum number of
1161 /// store operations that may be substituted for a call to memcpy. Targets
1162 /// must set this value based on the cost threshold for that target. Targets
1163 /// should assume that the memcpy will be done using as many of the largest
1164 /// store operations first, followed by smaller ones, if necessary, per
1165 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1166 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1167 /// and one 1-byte store. This only applies to copying a constant array of
1169 /// @brief Specify maximum bytes of store instructions per memcpy call.
1170 unsigned maxStoresPerMemcpy;
1172 /// When lowering %llvm.memmove this field specifies the maximum number of
1173 /// store instructions that may be substituted for a call to memmove. Targets
1174 /// must set this value based on the cost threshold for that target. Targets
1175 /// should assume that the memmove will be done using as many of the largest
1176 /// store operations first, followed by smaller ones, if necessary, per
1177 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1178 /// with 8-bit alignment would result in nine 1-byte stores. This only
1179 /// applies to copying a constant array of constant size.
1180 /// @brief Specify maximum bytes of store instructions per memmove call.
1181 unsigned maxStoresPerMemmove;
1183 /// This field specifies whether the target machine permits unaligned memory
1184 /// accesses. This is used, for example, to determine the size of store
1185 /// operations when copying small arrays and other similar tasks.
1186 /// @brief Indicate whether the target permits unaligned memory accesses.
1187 bool allowUnalignedMemoryAccesses;
1189 } // end llvm namespace