1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetMachine.h"
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineFrameInfo;
49 class MachineJumpTableInfo;
50 class MachineModuleInfo;
59 class TargetRegisterClass;
60 class TargetSubtarget;
61 class TargetLoweringObjectFile;
64 // FIXME: should this be here?
73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
76 //===----------------------------------------------------------------------===//
77 /// TargetLowering - This class defines information used to lower LLVM code to
78 /// legal SelectionDAG operators that the target instruction selector can accept
81 /// This class also defines callbacks that targets must implement to lower
82 /// target-specific constructs to SelectionDAG operators.
84 class TargetLowering {
85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
88 /// LegalizeAction - This enum indicates whether operations are valid for a
89 /// target, and if not, what action should be used to make them valid.
91 Legal, // The target natively supports this operation.
92 Promote, // This operation should be executed in a larger type.
93 Expand, // Try to expand this to other ops, otherwise use a libcall.
94 Custom // Use the LowerOperation hook to implement custom lowering.
97 enum BooleanContent { // How the target represents true/false values.
98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
99 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
103 enum SchedPreference {
104 SchedulingForLatency, // Scheduling for shortest total latency.
105 SchedulingForRegPressure // Scheduling for lowest register pressure.
108 /// NOTE: The constructor takes ownership of TLOF.
109 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF);
110 virtual ~TargetLowering();
112 TargetMachine &getTargetMachine() const { return TM; }
113 const TargetData *getTargetData() const { return TD; }
114 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
116 bool isBigEndian() const { return !IsLittleEndian; }
117 bool isLittleEndian() const { return IsLittleEndian; }
118 MVT getPointerTy() const { return PointerTy; }
119 MVT getShiftAmountTy() const { return ShiftAmountTy; }
121 /// isSelectExpensive - Return true if the select operation is expensive for
123 bool isSelectExpensive() const { return SelectIsExpensive; }
125 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
126 /// a sequence of several shifts, adds, and multiplies for this target.
127 bool isIntDivCheap() const { return IntDivIsCheap; }
129 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
131 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
133 /// getSetCCResultType - Return the ValueType of the result of SETCC
134 /// operations. Also used to obtain the target's preferred type for
135 /// the condition operand of SELECT and BRCOND nodes. In the case of
136 /// BRCOND the argument passed is MVT::Other since there are no other
137 /// operands to get a type hint from.
139 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
141 /// getCmpLibcallReturnType - Return the ValueType for comparison
142 /// libcalls. Comparions libcalls include floating point comparion calls,
143 /// and Ordered/Unordered check calls on floating point numbers.
145 MVT::SimpleValueType getCmpLibcallReturnType() const;
147 /// getBooleanContents - For targets without i1 registers, this gives the
148 /// nature of the high-bits of boolean values held in types wider than i1.
149 /// "Boolean values" are special true/false values produced by nodes like
150 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
151 /// Not to be confused with general values promoted from i1.
152 BooleanContent getBooleanContents() const { return BooleanContents;}
154 /// getSchedulingPreference - Return target scheduling preference.
155 SchedPreference getSchedulingPreference() const {
156 return SchedPreferenceInfo;
159 /// getRegClassFor - Return the register class that should be used for the
160 /// specified value type. This may only be called on legal types.
161 TargetRegisterClass *getRegClassFor(EVT VT) const {
162 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
163 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
164 assert(RC && "This value type is not natively supported!");
168 /// isTypeLegal - Return true if the target has native support for the
169 /// specified value type. This means that it has a register that directly
170 /// holds it without promotions or expansions.
171 bool isTypeLegal(EVT VT) const {
172 assert(!VT.isSimple() ||
173 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
174 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
177 class ValueTypeActionImpl {
178 /// ValueTypeActions - This is a bitvector that contains two bits for each
179 /// value type, where the two bits correspond to the LegalizeAction enum.
180 /// This can be queried with "getTypeAction(VT)".
181 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
182 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
184 ValueTypeActionImpl() {
185 ValueTypeActions[0] = ValueTypeActions[1] = 0;
186 ValueTypeActions[2] = ValueTypeActions[3] = 0;
188 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
189 ValueTypeActions[0] = RHS.ValueTypeActions[0];
190 ValueTypeActions[1] = RHS.ValueTypeActions[1];
191 ValueTypeActions[2] = RHS.ValueTypeActions[2];
192 ValueTypeActions[3] = RHS.ValueTypeActions[3];
195 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
196 if (VT.isExtended()) {
198 return VT.isPow2VectorType() ? Expand : Promote;
201 // First promote to a power-of-two size, then expand if necessary.
202 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
203 assert(0 && "Unsupported extended type!");
206 unsigned I = VT.getSimpleVT().SimpleTy;
207 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
208 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
210 void setTypeAction(EVT VT, LegalizeAction Action) {
211 unsigned I = VT.getSimpleVT().SimpleTy;
212 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
213 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
217 const ValueTypeActionImpl &getValueTypeActions() const {
218 return ValueTypeActions;
221 /// getTypeAction - Return how we should legalize values of this type, either
222 /// it is already legal (return 'Legal') or we need to promote it to a larger
223 /// type (return 'Promote'), or we need to expand it into multiple registers
224 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
225 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
226 return ValueTypeActions.getTypeAction(Context, VT);
229 /// getTypeToTransformTo - For types supported by the target, this is an
230 /// identity function. For types that must be promoted to larger types, this
231 /// returns the larger type to promote to. For integer types that are larger
232 /// than the largest integer register, this contains one step in the expansion
233 /// to get to the smaller register. For illegal floating point types, this
234 /// returns the integer type to transform to.
235 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
237 assert((unsigned)VT.getSimpleVT().SimpleTy <
238 array_lengthof(TransformToType));
239 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
240 assert(getTypeAction(Context, NVT) != Promote &&
241 "Promote may not follow Expand or Promote");
246 EVT NVT = VT.getPow2VectorType(Context);
248 // Vector length is a power of 2 - split to half the size.
249 unsigned NumElts = VT.getVectorNumElements();
250 EVT EltVT = VT.getVectorElementType();
251 return (NumElts == 1) ?
252 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
254 // Promote to a power of two size, avoiding multi-step promotion.
255 return getTypeAction(Context, NVT) == Promote ?
256 getTypeToTransformTo(Context, NVT) : NVT;
257 } else if (VT.isInteger()) {
258 EVT NVT = VT.getRoundIntegerType(Context);
260 // Size is a power of two - expand to half the size.
261 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
263 // Promote to a power of two size, avoiding multi-step promotion.
264 return getTypeAction(Context, NVT) == Promote ?
265 getTypeToTransformTo(Context, NVT) : NVT;
267 assert(0 && "Unsupported extended type!");
268 return MVT(MVT::Other); // Not reached
271 /// getTypeToExpandTo - For types supported by the target, this is an
272 /// identity function. For types that must be expanded (i.e. integer types
273 /// that are larger than the largest integer register or illegal floating
274 /// point types), this returns the largest legal type it will be expanded to.
275 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
276 assert(!VT.isVector());
278 switch (getTypeAction(Context, VT)) {
282 VT = getTypeToTransformTo(Context, VT);
285 assert(false && "Type is not legal nor is it to be expanded!");
292 /// getVectorTypeBreakdown - Vector types are broken down into some number of
293 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
294 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
295 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
297 /// This method returns the number of registers needed, and the VT for each
298 /// register. It also returns the VT and quantity of the intermediate values
299 /// before they are promoted/expanded.
301 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
303 unsigned &NumIntermediates,
304 EVT &RegisterVT) const;
306 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
307 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
308 /// this is the case, it returns true and store the intrinsic
309 /// information into the IntrinsicInfo that was passed to the function.
310 typedef struct IntrinsicInfo {
311 unsigned opc; // target opcode
312 EVT memVT; // memory VT
313 const Value* ptrVal; // value representing memory location
314 int offset; // offset off of ptrVal
315 unsigned align; // alignment
316 bool vol; // is volatile?
317 bool readMem; // reads memory?
318 bool writeMem; // writes memory?
321 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
322 CallInst &I, unsigned Intrinsic) {
326 /// getWidenVectorType: given a vector type, returns the type to widen to
327 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
328 /// If there is no vector type that we want to widen to, returns MVT::Other
329 /// When and were to widen is target dependent based on the cost of
330 /// scalarizing vs using the wider vector type.
331 virtual EVT getWidenVectorType(EVT VT) const;
333 /// isFPImmLegal - Returns true if the target can instruction select the
334 /// specified FP immediate natively. If false, the legalizer will materialize
335 /// the FP immediate as a load from a constant pool.
336 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
340 /// isShuffleMaskLegal - Targets can use this to indicate that they only
341 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
342 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
343 /// are assumed to be legal.
344 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
349 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
350 /// used by Targets can use this to indicate if there is a suitable
351 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
353 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
358 /// getOperationAction - Return how this operation should be treated: either
359 /// it is legal, needs to be promoted to a larger size, needs to be
360 /// expanded to some other code sequence, or the target has a custom expander
362 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
363 if (VT.isExtended()) return Expand;
364 assert(Op < array_lengthof(OpActions[0]) &&
365 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
366 "Table isn't big enough!");
367 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
370 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
373 /// isOperationLegalOrCustom - Return true if the specified operation is
374 /// legal on this target or can be made legal with custom lowering. This
375 /// is used to help guide high-level lowering decisions.
376 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
377 return (VT == MVT::Other || isTypeLegal(VT)) &&
378 (getOperationAction(Op, VT) == Legal ||
379 getOperationAction(Op, VT) == Custom);
382 /// isOperationLegal - Return true if the specified operation is legal on this
384 bool isOperationLegal(unsigned Op, EVT VT) const {
385 return (VT == MVT::Other || isTypeLegal(VT)) &&
386 getOperationAction(Op, VT) == Legal;
389 /// getLoadExtAction - Return how this load with extension should be treated:
390 /// either it is legal, needs to be promoted to a larger size, needs to be
391 /// expanded to some other code sequence, or the target has a custom expander
393 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
394 assert(LType < array_lengthof(LoadExtActions) &&
395 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
396 "Table isn't big enough!");
397 return (LegalizeAction)((LoadExtActions[LType] >>
398 (2*VT.getSimpleVT().SimpleTy)) & 3);
401 /// isLoadExtLegal - Return true if the specified load with extension is legal
403 bool isLoadExtLegal(unsigned LType, EVT VT) const {
404 return VT.isSimple() &&
405 (getLoadExtAction(LType, VT) == Legal ||
406 getLoadExtAction(LType, VT) == Custom);
409 /// getTruncStoreAction - Return how this store with truncation should be
410 /// treated: either it is legal, needs to be promoted to a larger size, needs
411 /// to be expanded to some other code sequence, or the target has a custom
413 LegalizeAction getTruncStoreAction(EVT ValVT,
415 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
416 array_lengthof(TruncStoreActions) &&
417 (unsigned)MemVT.getSimpleVT().SimpleTy <
418 sizeof(TruncStoreActions[0])*4 &&
419 "Table isn't big enough!");
420 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
421 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
424 /// isTruncStoreLegal - Return true if the specified store with truncation is
425 /// legal on this target.
426 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
427 return isTypeLegal(ValVT) && MemVT.isSimple() &&
428 (getTruncStoreAction(ValVT, MemVT) == Legal ||
429 getTruncStoreAction(ValVT, MemVT) == Custom);
432 /// getIndexedLoadAction - Return how the indexed load should be treated:
433 /// either it is legal, needs to be promoted to a larger size, needs to be
434 /// expanded to some other code sequence, or the target has a custom expander
437 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
438 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
439 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
440 "Table isn't big enough!");
441 return (LegalizeAction)((IndexedModeActions[
442 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
445 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
447 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
448 return VT.isSimple() &&
449 (getIndexedLoadAction(IdxMode, VT) == Legal ||
450 getIndexedLoadAction(IdxMode, VT) == Custom);
453 /// getIndexedStoreAction - Return how the indexed store should be treated:
454 /// either it is legal, needs to be promoted to a larger size, needs to be
455 /// expanded to some other code sequence, or the target has a custom expander
458 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
459 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
460 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
461 "Table isn't big enough!");
462 return (LegalizeAction)((IndexedModeActions[
463 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
466 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
468 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
469 return VT.isSimple() &&
470 (getIndexedStoreAction(IdxMode, VT) == Legal ||
471 getIndexedStoreAction(IdxMode, VT) == Custom);
474 /// getConvertAction - Return how the conversion should be treated:
475 /// either it is legal, needs to be promoted to a larger size, needs to be
476 /// expanded to some other code sequence, or the target has a custom expander
479 getConvertAction(EVT FromVT, EVT ToVT) const {
480 assert((unsigned)FromVT.getSimpleVT().SimpleTy <
481 array_lengthof(ConvertActions) &&
482 (unsigned)ToVT.getSimpleVT().SimpleTy <
483 sizeof(ConvertActions[0])*4 &&
484 "Table isn't big enough!");
485 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
486 (2*ToVT.getSimpleVT().SimpleTy)) & 3);
489 /// isConvertLegal - Return true if the specified conversion is legal
491 bool isConvertLegal(EVT FromVT, EVT ToVT) const {
492 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
493 (getConvertAction(FromVT, ToVT) == Legal ||
494 getConvertAction(FromVT, ToVT) == Custom);
497 /// getCondCodeAction - Return how the condition code should be treated:
498 /// either it is legal, needs to be expanded to some other code sequence,
499 /// or the target has a custom expander for it.
501 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
502 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
503 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
504 "Table isn't big enough!");
505 LegalizeAction Action = (LegalizeAction)
506 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
507 assert(Action != Promote && "Can't promote condition code!");
511 /// isCondCodeLegal - Return true if the specified condition code is legal
513 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
514 return getCondCodeAction(CC, VT) == Legal ||
515 getCondCodeAction(CC, VT) == Custom;
519 /// getTypeToPromoteTo - If the action for this operation is to promote, this
520 /// method returns the ValueType to promote to.
521 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
522 assert(getOperationAction(Op, VT) == Promote &&
523 "This operation isn't promoted!");
525 // See if this has an explicit type specified.
526 std::map<std::pair<unsigned, MVT::SimpleValueType>,
527 MVT::SimpleValueType>::const_iterator PTTI =
528 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
529 if (PTTI != PromoteToType.end()) return PTTI->second;
531 assert((VT.isInteger() || VT.isFloatingPoint()) &&
532 "Cannot autopromote this type, add it with AddPromotedToType.");
536 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
537 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
538 "Didn't find type to promote to!");
539 } while (!isTypeLegal(NVT) ||
540 getOperationAction(Op, NVT) == Promote);
544 /// getValueType - Return the EVT corresponding to this LLVM type.
545 /// This is fixed by the LLVM operations except for the pointer size. If
546 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
547 /// counterpart (e.g. structs), otherwise it will assert.
548 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
549 EVT VT = EVT::getEVT(Ty, AllowUnknown);
550 return VT == MVT:: iPTR ? PointerTy : VT;
553 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
554 /// function arguments in the caller parameter area. This is the actual
555 /// alignment, not its logarithm.
556 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
558 /// getRegisterType - Return the type of registers that this ValueType will
559 /// eventually require.
560 EVT getRegisterType(MVT VT) const {
561 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
562 return RegisterTypeForVT[VT.SimpleTy];
565 /// getRegisterType - Return the type of registers that this ValueType will
566 /// eventually require.
567 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
569 assert((unsigned)VT.getSimpleVT().SimpleTy <
570 array_lengthof(RegisterTypeForVT));
571 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
575 unsigned NumIntermediates;
576 (void)getVectorTypeBreakdown(Context, VT, VT1,
577 NumIntermediates, RegisterVT);
580 if (VT.isInteger()) {
581 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
583 assert(0 && "Unsupported extended type!");
584 return EVT(MVT::Other); // Not reached
587 /// getNumRegisters - Return the number of registers that this ValueType will
588 /// eventually require. This is one for any types promoted to live in larger
589 /// registers, but may be more than one for types (like i64) that are split
590 /// into pieces. For types like i140, which are first promoted then expanded,
591 /// it is the number of registers needed to hold all the bits of the original
592 /// type. For an i140 on a 32 bit machine this means 5 registers.
593 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
595 assert((unsigned)VT.getSimpleVT().SimpleTy <
596 array_lengthof(NumRegistersForVT));
597 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
601 unsigned NumIntermediates;
602 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
604 if (VT.isInteger()) {
605 unsigned BitWidth = VT.getSizeInBits();
606 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
607 return (BitWidth + RegWidth - 1) / RegWidth;
609 assert(0 && "Unsupported extended type!");
610 return 0; // Not reached
613 /// ShouldShrinkFPConstant - If true, then instruction selection should
614 /// seek to shrink the FP constant of the specified type to a smaller type
615 /// in order to save space and / or reduce runtime.
616 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
618 /// hasTargetDAGCombine - If true, the target has custom DAG combine
619 /// transformations that it can perform for the specified node.
620 bool hasTargetDAGCombine(ISD::NodeType NT) const {
621 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
622 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
625 /// This function returns the maximum number of store operations permitted
626 /// to replace a call to llvm.memset. The value is set by the target at the
627 /// performance threshold for such a replacement.
628 /// @brief Get maximum # of store operations permitted for llvm.memset
629 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
631 /// This function returns the maximum number of store operations permitted
632 /// to replace a call to llvm.memcpy. The value is set by the target at the
633 /// performance threshold for such a replacement.
634 /// @brief Get maximum # of store operations permitted for llvm.memcpy
635 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
637 /// This function returns the maximum number of store operations permitted
638 /// to replace a call to llvm.memmove. The value is set by the target at the
639 /// performance threshold for such a replacement.
640 /// @brief Get maximum # of store operations permitted for llvm.memmove
641 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
643 /// This function returns true if the target allows unaligned memory accesses.
644 /// of the specified type. This is used, for example, in situations where an
645 /// array copy/move/set is converted to a sequence of store operations. It's
646 /// use helps to ensure that such replacements don't generate code that causes
647 /// an alignment error (trap) on the target machine.
648 /// @brief Determine if the target supports unaligned memory accesses.
649 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
653 /// This function returns true if the target would benefit from code placement
655 /// @brief Determine if the target should perform code placement optimization.
656 bool shouldOptimizeCodePlacement() const {
657 return benefitFromCodePlacementOpt;
660 /// getOptimalMemOpType - Returns the target specific optimal type for load
661 /// and store operations as a result of memset, memcpy, and memmove lowering.
662 /// It returns EVT::iAny if SelectionDAG should be responsible for
664 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
665 bool isSrcConst, bool isSrcStr,
666 SelectionDAG &DAG) const {
670 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
671 /// to implement llvm.setjmp.
672 bool usesUnderscoreSetJmp() const {
673 return UseUnderscoreSetJmp;
676 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
677 /// to implement llvm.longjmp.
678 bool usesUnderscoreLongJmp() const {
679 return UseUnderscoreLongJmp;
682 /// getStackPointerRegisterToSaveRestore - If a physical register, this
683 /// specifies the register that llvm.savestack/llvm.restorestack should save
685 unsigned getStackPointerRegisterToSaveRestore() const {
686 return StackPointerRegisterToSaveRestore;
689 /// getExceptionAddressRegister - If a physical register, this returns
690 /// the register that receives the exception address on entry to a landing
692 unsigned getExceptionAddressRegister() const {
693 return ExceptionPointerRegister;
696 /// getExceptionSelectorRegister - If a physical register, this returns
697 /// the register that receives the exception typeid on entry to a landing
699 unsigned getExceptionSelectorRegister() const {
700 return ExceptionSelectorRegister;
703 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
704 /// set, the default is 200)
705 unsigned getJumpBufSize() const {
709 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
710 /// (if never set, the default is 0)
711 unsigned getJumpBufAlignment() const {
712 return JumpBufAlignment;
715 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
716 /// limit. Any block whose size is greater should not be predicated.
717 unsigned getIfCvtBlockSizeLimit() const {
718 return IfCvtBlockSizeLimit;
721 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
722 /// block to be considered for duplication. Any block whose size is greater
723 /// should not be duplicated to facilitate its predication.
724 unsigned getIfCvtDupBlockSizeLimit() const {
725 return IfCvtDupBlockSizeLimit;
728 /// getPrefLoopAlignment - return the preferred loop alignment.
730 unsigned getPrefLoopAlignment() const {
731 return PrefLoopAlignment;
734 /// getPreIndexedAddressParts - returns true by value, base pointer and
735 /// offset pointer and addressing mode by reference if the node's address
736 /// can be legally represented as pre-indexed load / store address.
737 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
739 ISD::MemIndexedMode &AM,
740 SelectionDAG &DAG) const {
744 /// getPostIndexedAddressParts - returns true by value, base pointer and
745 /// offset pointer and addressing mode by reference if this node can be
746 /// combined with a load / store to form a post-indexed load / store.
747 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
748 SDValue &Base, SDValue &Offset,
749 ISD::MemIndexedMode &AM,
750 SelectionDAG &DAG) const {
754 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
755 /// current function. The returned value is a member of the
756 /// MachineJumpTableInfo::JTEntryKind enum.
757 virtual unsigned getJumpTableEncoding() const;
759 virtual const MCExpr *
760 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
761 const MachineBasicBlock *MBB, unsigned uid,
762 MCContext &Ctx) const {
763 assert(0 && "Need to implement this hook if target has custom JTIs");
766 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
768 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
769 SelectionDAG &DAG) const;
771 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
772 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
774 virtual const MCExpr *
775 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
776 unsigned JTI, MCContext &Ctx) const;
778 /// isOffsetFoldingLegal - Return true if folding a constant offset
779 /// with the given GlobalAddress is legal. It is frequently not legal in
780 /// PIC relocation models.
781 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
783 /// getFunctionAlignment - Return the Log2 alignment of this function.
784 virtual unsigned getFunctionAlignment(const Function *) const = 0;
786 //===--------------------------------------------------------------------===//
787 // TargetLowering Optimization Methods
790 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
791 /// SDValues for returning information from TargetLowering to its clients
792 /// that want to combine
793 struct TargetLoweringOpt {
799 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool Shrink = false) :
800 DAG(InDAG), ShrinkOps(Shrink) {}
802 bool CombineTo(SDValue O, SDValue N) {
808 /// ShrinkDemandedConstant - Check to see if the specified operand of the
809 /// specified instruction is a constant integer. If so, check to see if
810 /// there are any bits set in the constant that are not demanded. If so,
811 /// shrink the constant and return true.
812 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
814 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
815 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
816 /// cast, but it could be generalized for targets with other types of
817 /// implicit widening casts.
818 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
822 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
823 /// DemandedMask bits of the result of Op are ever used downstream. If we can
824 /// use this information to simplify Op, create a new simplified DAG node and
825 /// return true, returning the original and new nodes in Old and New.
826 /// Otherwise, analyze the expression and return a mask of KnownOne and
827 /// KnownZero bits for the expression (used to simplify the caller).
828 /// The KnownZero/One bits may only be accurate for those bits in the
830 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
831 APInt &KnownZero, APInt &KnownOne,
832 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
834 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
835 /// Mask are known to be either zero or one and return them in the
836 /// KnownZero/KnownOne bitsets.
837 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
841 const SelectionDAG &DAG,
842 unsigned Depth = 0) const;
844 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
845 /// targets that want to expose additional information about sign bits to the
847 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
848 unsigned Depth = 0) const;
850 struct DAGCombinerInfo {
851 void *DC; // The DAG Combiner object.
853 bool BeforeLegalizeOps;
854 bool CalledByLegalizer;
858 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
859 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
860 CalledByLegalizer(cl), DAG(dag) {}
862 bool isBeforeLegalize() const { return BeforeLegalize; }
863 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
864 bool isCalledByLegalizer() const { return CalledByLegalizer; }
866 void AddToWorklist(SDNode *N);
867 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
869 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
870 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
872 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
875 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
876 /// and cc. If it is unable to simplify it, return a null SDValue.
877 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
878 ISD::CondCode Cond, bool foldBooleans,
879 DAGCombinerInfo &DCI, DebugLoc dl) const;
881 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
882 /// node is a GlobalAddress + offset.
884 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
886 /// PerformDAGCombine - This method will be invoked for all target nodes and
887 /// for any target-independent nodes that the target has registered with
890 /// The semantics are as follows:
892 /// SDValue.Val == 0 - No change was made
893 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
894 /// otherwise - N should be replaced by the returned Operand.
896 /// In addition, methods provided by DAGCombinerInfo may be used to perform
897 /// more complex transformations.
899 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
901 //===--------------------------------------------------------------------===//
902 // TargetLowering Configuration Methods - These methods should be invoked by
903 // the derived class constructor to configure this object for the target.
907 /// setShiftAmountType - Describe the type that should be used for shift
908 /// amounts. This type defaults to the pointer type.
909 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
911 /// setBooleanContents - Specify how the target extends the result of a
912 /// boolean value from i1 to a wider type. See getBooleanContents.
913 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
915 /// setSchedulingPreference - Specify the target scheduling preference.
916 void setSchedulingPreference(SchedPreference Pref) {
917 SchedPreferenceInfo = Pref;
920 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
921 /// use _setjmp to implement llvm.setjmp or the non _ version.
922 /// Defaults to false.
923 void setUseUnderscoreSetJmp(bool Val) {
924 UseUnderscoreSetJmp = Val;
927 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
928 /// use _longjmp to implement llvm.longjmp or the non _ version.
929 /// Defaults to false.
930 void setUseUnderscoreLongJmp(bool Val) {
931 UseUnderscoreLongJmp = Val;
934 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
935 /// specifies the register that llvm.savestack/llvm.restorestack should save
937 void setStackPointerRegisterToSaveRestore(unsigned R) {
938 StackPointerRegisterToSaveRestore = R;
941 /// setExceptionPointerRegister - If set to a physical register, this sets
942 /// the register that receives the exception address on entry to a landing
944 void setExceptionPointerRegister(unsigned R) {
945 ExceptionPointerRegister = R;
948 /// setExceptionSelectorRegister - If set to a physical register, this sets
949 /// the register that receives the exception typeid on entry to a landing
951 void setExceptionSelectorRegister(unsigned R) {
952 ExceptionSelectorRegister = R;
955 /// SelectIsExpensive - Tells the code generator not to expand operations
956 /// into sequences that use the select operations if possible.
957 void setSelectIsExpensive() { SelectIsExpensive = true; }
959 /// setIntDivIsCheap - Tells the code generator that integer divide is
960 /// expensive, and if possible, should be replaced by an alternate sequence
961 /// of instructions not containing an integer divide.
962 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
964 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
965 /// srl/add/sra for a signed divide by power of two, and let the target handle
967 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
969 /// addRegisterClass - Add the specified register class as an available
970 /// regclass for the specified value type. This indicates the selector can
971 /// handle values of that class natively.
972 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
973 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
974 AvailableRegClasses.push_back(std::make_pair(VT, RC));
975 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
978 /// computeRegisterProperties - Once all of the register classes are added,
979 /// this allows us to compute derived properties we expose.
980 void computeRegisterProperties();
982 /// setOperationAction - Indicate that the specified operation does not work
983 /// with the specified type and indicate what to do about it.
984 void setOperationAction(unsigned Op, MVT VT,
985 LegalizeAction Action) {
986 unsigned I = (unsigned)VT.SimpleTy;
989 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
990 OpActions[I][Op] |= (uint64_t)Action << (J*2);
993 /// setLoadExtAction - Indicate that the specified load with extension does
994 /// not work with the with specified type and indicate what to do about it.
995 void setLoadExtAction(unsigned ExtType, MVT VT,
996 LegalizeAction Action) {
997 assert((unsigned)VT.SimpleTy*2 < 63 &&
998 ExtType < array_lengthof(LoadExtActions) &&
999 "Table isn't big enough!");
1000 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1001 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
1004 /// setTruncStoreAction - Indicate that the specified truncating store does
1005 /// not work with the with specified type and indicate what to do about it.
1006 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1007 LegalizeAction Action) {
1008 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
1009 (unsigned)MemVT.SimpleTy*2 < 63 &&
1010 "Table isn't big enough!");
1011 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
1012 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
1015 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1016 /// does not work with the with specified type and indicate what to do abort
1017 /// it. NOTE: All indexed mode loads are initialized to Expand in
1018 /// TargetLowering.cpp
1019 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1020 LegalizeAction Action) {
1021 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1022 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
1023 "Table isn't big enough!");
1024 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
1027 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1028 /// does not work with the with specified type and indicate what to do about
1029 /// it. NOTE: All indexed mode stores are initialized to Expand in
1030 /// TargetLowering.cpp
1031 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1032 LegalizeAction Action) {
1033 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1034 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1035 "Table isn't big enough!");
1036 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
1039 /// setConvertAction - Indicate that the specified conversion does or does
1040 /// not work with the with specified type and indicate what to do about it.
1041 void setConvertAction(MVT FromVT, MVT ToVT,
1042 LegalizeAction Action) {
1043 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
1044 (unsigned)ToVT.SimpleTy < MVT::LAST_VALUETYPE &&
1045 "Table isn't big enough!");
1046 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
1047 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
1050 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1051 /// supported on the target and indicate what to do about it.
1052 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1053 LegalizeAction Action) {
1054 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1055 (unsigned)CC < array_lengthof(CondCodeActions) &&
1056 "Table isn't big enough!");
1057 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1058 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1061 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1062 /// promotion code defaults to trying a larger integer/fp until it can find
1063 /// one that works. If that default is insufficient, this method can be used
1064 /// by the target to override the default.
1065 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1066 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1069 /// setTargetDAGCombine - Targets should invoke this method for each target
1070 /// independent node that they want to provide a custom DAG combiner for by
1071 /// implementing the PerformDAGCombine virtual method.
1072 void setTargetDAGCombine(ISD::NodeType NT) {
1073 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1074 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1077 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1078 /// bytes); default is 200
1079 void setJumpBufSize(unsigned Size) {
1083 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1084 /// alignment (in bytes); default is 0
1085 void setJumpBufAlignment(unsigned Align) {
1086 JumpBufAlignment = Align;
1089 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1090 /// limit (in number of instructions); default is 2.
1091 void setIfCvtBlockSizeLimit(unsigned Limit) {
1092 IfCvtBlockSizeLimit = Limit;
1095 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1096 /// of instructions) to be considered for code duplication during
1097 /// if-conversion; default is 2.
1098 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1099 IfCvtDupBlockSizeLimit = Limit;
1102 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1103 /// alignment is zero, it means the target does not care about loop alignment.
1104 void setPrefLoopAlignment(unsigned Align) {
1105 PrefLoopAlignment = Align;
1110 virtual const TargetSubtarget *getSubtarget() {
1111 assert(0 && "Not Implemented");
1112 return NULL; // this is here to silence compiler errors
1115 //===--------------------------------------------------------------------===//
1116 // Lowering methods - These methods must be implemented by targets so that
1117 // the SelectionDAGLowering code knows how to lower these.
1120 /// LowerFormalArguments - This hook must be implemented to lower the
1121 /// incoming (formal) arguments, described by the Ins array, into the
1122 /// specified DAG. The implementation should fill in the InVals array
1123 /// with legal-type argument values, and return the resulting token
1127 LowerFormalArguments(SDValue Chain,
1128 CallingConv::ID CallConv, bool isVarArg,
1129 const SmallVectorImpl<ISD::InputArg> &Ins,
1130 DebugLoc dl, SelectionDAG &DAG,
1131 SmallVectorImpl<SDValue> &InVals) {
1132 assert(0 && "Not Implemented");
1133 return SDValue(); // this is here to silence compiler errors
1136 /// LowerCallTo - This function lowers an abstract call to a function into an
1137 /// actual call. This returns a pair of operands. The first element is the
1138 /// return value for the function (if RetTy is not VoidTy). The second
1139 /// element is the outgoing token chain. It calls LowerCall to do the actual
1141 struct ArgListEntry {
1152 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1153 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1155 typedef std::vector<ArgListEntry> ArgListTy;
1156 std::pair<SDValue, SDValue>
1157 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1158 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1159 CallingConv::ID CallConv, bool isTailCall,
1160 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1161 SelectionDAG &DAG, DebugLoc dl, unsigned Order);
1163 /// LowerCall - This hook must be implemented to lower calls into the
1164 /// the specified DAG. The outgoing arguments to the call are described
1165 /// by the Outs array, and the values to be returned by the call are
1166 /// described by the Ins array. The implementation should fill in the
1167 /// InVals array with legal-type return values from the call, and return
1168 /// the resulting token chain value.
1170 /// The isTailCall flag here is normative. If it is true, the
1171 /// implementation must emit a tail call. The
1172 /// IsEligibleForTailCallOptimization hook should be used to catch
1173 /// cases that cannot be handled.
1176 LowerCall(SDValue Chain, SDValue Callee,
1177 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
1178 const SmallVectorImpl<ISD::OutputArg> &Outs,
1179 const SmallVectorImpl<ISD::InputArg> &Ins,
1180 DebugLoc dl, SelectionDAG &DAG,
1181 SmallVectorImpl<SDValue> &InVals) {
1182 assert(0 && "Not Implemented");
1183 return SDValue(); // this is here to silence compiler errors
1186 /// CanLowerReturn - This hook should be implemented to check whether the
1187 /// return values described by the Outs array can fit into the return
1188 /// registers. If false is returned, an sret-demotion is performed.
1190 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1191 const SmallVectorImpl<EVT> &OutTys,
1192 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1195 // Return true by default to get preexisting behavior.
1198 /// LowerReturn - This hook must be implemented to lower outgoing
1199 /// return values, described by the Outs array, into the specified
1200 /// DAG. The implementation should return the resulting token chain
1204 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1205 const SmallVectorImpl<ISD::OutputArg> &Outs,
1206 DebugLoc dl, SelectionDAG &DAG) {
1207 assert(0 && "Not Implemented");
1208 return SDValue(); // this is here to silence compiler errors
1211 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1212 /// memcpy. This can be used by targets to provide code sequences for cases
1213 /// that don't fit the target's parameters for simple loads/stores and can be
1214 /// more efficient than using a library call. This function can return a null
1215 /// SDValue if the target declines to use custom code and a different
1216 /// lowering strategy should be used.
1218 /// If AlwaysInline is true, the size is constant and the target should not
1219 /// emit any calls and is strongly encouraged to attempt to emit inline code
1220 /// even if it is beyond the usual threshold because this intrinsic is being
1221 /// expanded in a place where calls are not feasible (e.g. within the prologue
1222 /// for another call). If the target chooses to decline an AlwaysInline
1223 /// request here, legalize will resort to using simple loads and stores.
1225 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1227 SDValue Op1, SDValue Op2,
1228 SDValue Op3, unsigned Align,
1230 const Value *DstSV, uint64_t DstOff,
1231 const Value *SrcSV, uint64_t SrcOff) {
1235 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1236 /// memmove. This can be used by targets to provide code sequences for cases
1237 /// that don't fit the target's parameters for simple loads/stores and can be
1238 /// more efficient than using a library call. This function can return a null
1239 /// SDValue if the target declines to use custom code and a different
1240 /// lowering strategy should be used.
1242 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1244 SDValue Op1, SDValue Op2,
1245 SDValue Op3, unsigned Align,
1246 const Value *DstSV, uint64_t DstOff,
1247 const Value *SrcSV, uint64_t SrcOff) {
1251 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1252 /// memset. This can be used by targets to provide code sequences for cases
1253 /// that don't fit the target's parameters for simple stores and can be more
1254 /// efficient than using a library call. This function can return a null
1255 /// SDValue if the target declines to use custom code and a different
1256 /// lowering strategy should be used.
1258 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1260 SDValue Op1, SDValue Op2,
1261 SDValue Op3, unsigned Align,
1262 const Value *DstSV, uint64_t DstOff) {
1266 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1267 /// to legalize nodes with an illegal operand type but legal result types.
1268 /// It replaces the LowerOperation callback in the type Legalizer.
1269 /// The reason we can not do away with LowerOperation entirely is that
1270 /// LegalizeDAG isn't yet ready to use this callback.
1271 /// TODO: Consider merging with ReplaceNodeResults.
1273 /// The target places new result values for the node in Results (their number
1274 /// and types must exactly match those of the original return values of
1275 /// the node), or leaves Results empty, which indicates that the node is not
1276 /// to be custom lowered after all.
1277 /// The default implementation calls LowerOperation.
1278 virtual void LowerOperationWrapper(SDNode *N,
1279 SmallVectorImpl<SDValue> &Results,
1282 /// LowerOperation - This callback is invoked for operations that are
1283 /// unsupported by the target, which are registered to use 'custom' lowering,
1284 /// and whose defined values are all legal.
1285 /// If the target has no operations that require custom lowering, it need not
1286 /// implement this. The default implementation of this aborts.
1287 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1289 /// ReplaceNodeResults - This callback is invoked when a node result type is
1290 /// illegal for the target, and the operation was registered to use 'custom'
1291 /// lowering for that result type. The target places new result values for
1292 /// the node in Results (their number and types must exactly match those of
1293 /// the original return values of the node), or leaves Results empty, which
1294 /// indicates that the node is not to be custom lowered after all.
1296 /// If the target has no operations that require custom lowering, it need not
1297 /// implement this. The default implementation aborts.
1298 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1299 SelectionDAG &DAG) {
1300 assert(0 && "ReplaceNodeResults not implemented for this target!");
1303 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1304 /// tail call optimization. Targets which want to do tail call optimization
1305 /// should override this function.
1307 IsEligibleForTailCallOptimization(SDValue Callee,
1308 CallingConv::ID CalleeCC,
1310 const SmallVectorImpl<ISD::InputArg> &Ins,
1311 SelectionDAG& DAG) const {
1312 // Conservative default: no calls are eligible.
1316 /// getTargetNodeName() - This method returns the name of a target specific
1318 virtual const char *getTargetNodeName(unsigned Opcode) const;
1320 /// createFastISel - This method returns a target specific FastISel object,
1321 /// or null if the target does not support "fast" ISel.
1323 createFastISel(MachineFunction &,
1324 MachineModuleInfo *, DwarfWriter *,
1325 DenseMap<const Value *, unsigned> &,
1326 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1327 DenseMap<const AllocaInst *, int> &
1329 , SmallSet<Instruction*, 8> &CatchInfoLost
1335 //===--------------------------------------------------------------------===//
1336 // Inline Asm Support hooks
1339 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1340 /// call to be explicit llvm code if it wants to. This is useful for
1341 /// turning simple inline asms into LLVM intrinsics, which gives the
1342 /// compiler more information about the behavior of the code.
1343 virtual bool ExpandInlineAsm(CallInst *CI) const {
1347 enum ConstraintType {
1348 C_Register, // Constraint represents specific register(s).
1349 C_RegisterClass, // Constraint represents any of register(s) in class.
1350 C_Memory, // Memory constraint.
1351 C_Other, // Something else.
1352 C_Unknown // Unsupported constraint.
1355 /// AsmOperandInfo - This contains information for each constraint that we are
1357 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1358 /// ConstraintCode - This contains the actual string for the code, like "m".
1359 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1360 /// most closely matches the operand.
1361 std::string ConstraintCode;
1363 /// ConstraintType - Information about the constraint code, e.g. Register,
1364 /// RegisterClass, Memory, Other, Unknown.
1365 TargetLowering::ConstraintType ConstraintType;
1367 /// CallOperandval - If this is the result output operand or a
1368 /// clobber, this is null, otherwise it is the incoming operand to the
1369 /// CallInst. This gets modified as the asm is processed.
1370 Value *CallOperandVal;
1372 /// ConstraintVT - The ValueType for the operand value.
1375 /// isMatchingInputConstraint - Return true of this is an input operand that
1376 /// is a matching constraint like "4".
1377 bool isMatchingInputConstraint() const;
1379 /// getMatchedOperand - If this is an input matching constraint, this method
1380 /// returns the output operand it matches.
1381 unsigned getMatchedOperand() const;
1383 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1384 : InlineAsm::ConstraintInfo(info),
1385 ConstraintType(TargetLowering::C_Unknown),
1386 CallOperandVal(0), ConstraintVT(MVT::Other) {
1390 /// ComputeConstraintToUse - Determines the constraint code and constraint
1391 /// type to use for the specific AsmOperandInfo, setting
1392 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1393 /// being passed in is available, it can be passed in as Op, otherwise an
1394 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1395 /// constraint of the inline asm instruction being processed is 'm'.
1396 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1399 SelectionDAG *DAG = 0) const;
1401 /// getConstraintType - Given a constraint, return the type of constraint it
1402 /// is for this target.
1403 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1405 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1406 /// return a list of registers that can be used to satisfy the constraint.
1407 /// This should only be used for C_RegisterClass constraints.
1408 virtual std::vector<unsigned>
1409 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1412 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1413 /// {edx}), return the register number and the register class for the
1416 /// Given a register class constraint, like 'r', if this corresponds directly
1417 /// to an LLVM register class, return a register of 0 and the register class
1420 /// This should only be used for C_Register constraints. On error,
1421 /// this returns a register number of 0 and a null register class pointer..
1422 virtual std::pair<unsigned, const TargetRegisterClass*>
1423 getRegForInlineAsmConstraint(const std::string &Constraint,
1426 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1427 /// with another that has more specific requirements based on the type of the
1428 /// corresponding operand. This returns null if there is no replacement to
1430 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1432 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1433 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1434 /// it means one of the asm constraint of the inline asm instruction being
1435 /// processed is 'm'.
1436 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1438 std::vector<SDValue> &Ops,
1439 SelectionDAG &DAG) const;
1441 //===--------------------------------------------------------------------===//
1442 // Instruction Emitting Hooks
1445 // EmitInstrWithCustomInserter - This method should be implemented by targets
1446 // that mark instructions with the 'usesCustomInserter' flag. These
1447 // instructions are special in various ways, which require special support to
1448 // insert. The specified MachineInstr is created but not inserted into any
1449 // basic blocks, and this method is called to expand it into a sequence of
1450 // instructions, potentially also creating new basic blocks and control flow.
1451 // When new basic blocks are inserted and the edges from MBB to its successors
1452 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
1454 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1455 MachineBasicBlock *MBB,
1456 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
1458 //===--------------------------------------------------------------------===//
1459 // Addressing mode description hooks (used by LSR etc).
1462 /// AddrMode - This represents an addressing mode of:
1463 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1464 /// If BaseGV is null, there is no BaseGV.
1465 /// If BaseOffs is zero, there is no base offset.
1466 /// If HasBaseReg is false, there is no base register.
1467 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1471 GlobalValue *BaseGV;
1475 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1478 /// isLegalAddressingMode - Return true if the addressing mode represented by
1479 /// AM is legal for this target, for a load/store of the specified type.
1480 /// The type may be VoidTy, in which case only return true if the addressing
1481 /// mode is legal for a load/store of any legal type.
1482 /// TODO: Handle pre/postinc as well.
1483 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1485 /// isTruncateFree - Return true if it's free to truncate a value of
1486 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1487 /// register EAX to i16 by referencing its sub-register AX.
1488 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1492 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1496 /// isZExtFree - Return true if any actual instruction that defines a
1497 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1498 /// register. This does not necessarily include registers defined in
1499 /// unknown ways, such as incoming arguments, or copies from unknown
1500 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1501 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1502 /// all instructions that define 32-bit values implicit zero-extend the
1503 /// result out to 64 bits.
1504 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1508 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1512 /// isNarrowingProfitable - Return true if it's profitable to narrow
1513 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1514 /// from i32 to i8 but not from i32 to i16.
1515 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1519 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1520 /// icmp immediate, that is the target has icmp instructions which can compare
1521 /// a register against the immediate without having to materialize the
1522 /// immediate into a register.
1523 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1527 //===--------------------------------------------------------------------===//
1528 // Div utility functions
1530 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1531 std::vector<SDNode*>* Created) const;
1532 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1533 std::vector<SDNode*>* Created) const;
1536 //===--------------------------------------------------------------------===//
1537 // Runtime Library hooks
1540 /// setLibcallName - Rename the default libcall routine name for the specified
1542 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1543 LibcallRoutineNames[Call] = Name;
1546 /// getLibcallName - Get the libcall routine name for the specified libcall.
1548 const char *getLibcallName(RTLIB::Libcall Call) const {
1549 return LibcallRoutineNames[Call];
1552 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1553 /// result of the comparison libcall against zero.
1554 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1555 CmpLibcallCCs[Call] = CC;
1558 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1559 /// the comparison libcall against zero.
1560 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1561 return CmpLibcallCCs[Call];
1564 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1565 /// specified libcall.
1566 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1567 LibcallCallingConvs[Call] = CC;
1570 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1571 /// specified libcall.
1572 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1573 return LibcallCallingConvs[Call];
1578 const TargetData *TD;
1579 TargetLoweringObjectFile &TLOF;
1581 /// PointerTy - The type to use for pointers, usually i32 or i64.
1585 /// IsLittleEndian - True if this is a little endian target.
1587 bool IsLittleEndian;
1589 /// SelectIsExpensive - Tells the code generator not to expand operations
1590 /// into sequences that use the select operations if possible.
1591 bool SelectIsExpensive;
1593 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1594 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1595 /// a real cost model is in place. If we ever optimize for size, this will be
1596 /// set to true unconditionally.
1599 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1600 /// srl/add/sra for a signed divide by power of two, and let the target handle
1602 bool Pow2DivIsCheap;
1604 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1605 /// llvm.setjmp. Defaults to false.
1606 bool UseUnderscoreSetJmp;
1608 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1609 /// llvm.longjmp. Defaults to false.
1610 bool UseUnderscoreLongJmp;
1612 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1616 /// BooleanContents - Information about the contents of the high-bits in
1617 /// boolean values held in a type wider than i1. See getBooleanContents.
1618 BooleanContent BooleanContents;
1620 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1621 /// total cycles or lowest register usage.
1622 SchedPreference SchedPreferenceInfo;
1624 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1625 unsigned JumpBufSize;
1627 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1629 unsigned JumpBufAlignment;
1631 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1633 unsigned IfCvtBlockSizeLimit;
1635 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1636 /// duplicated during if-conversion.
1637 unsigned IfCvtDupBlockSizeLimit;
1639 /// PrefLoopAlignment - The perferred loop alignment.
1641 unsigned PrefLoopAlignment;
1643 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1644 /// specifies the register that llvm.savestack/llvm.restorestack should save
1646 unsigned StackPointerRegisterToSaveRestore;
1648 /// ExceptionPointerRegister - If set to a physical register, this specifies
1649 /// the register that receives the exception address on entry to a landing
1651 unsigned ExceptionPointerRegister;
1653 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1654 /// the register that receives the exception typeid on entry to a landing
1656 unsigned ExceptionSelectorRegister;
1658 /// RegClassForVT - This indicates the default register class to use for
1659 /// each ValueType the target supports natively.
1660 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1661 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1662 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1664 /// TransformToType - For any value types we are promoting or expanding, this
1665 /// contains the value type that we are changing to. For Expanded types, this
1666 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1667 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1668 /// by the system, this holds the same type (e.g. i32 -> i32).
1669 EVT TransformToType[MVT::LAST_VALUETYPE];
1671 /// OpActions - For each operation and each value type, keep a LegalizeAction
1672 /// that indicates how instruction selection should deal with the operation.
1673 /// Most operations are Legal (aka, supported natively by the target), but
1674 /// operations that are not should be described. Note that operations on
1675 /// non-legal value types are not described here.
1676 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1677 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1678 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1680 /// LoadExtActions - For each load of load extension type and each value type,
1681 /// keep a LegalizeAction that indicates how instruction selection should deal
1683 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1685 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1686 /// indicates how instruction selection should deal with the store.
1687 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1689 /// IndexedModeActions - For each indexed mode and each value type,
1690 /// keep a pair of LegalizeAction that indicates how instruction
1691 /// selection should deal with the load / store. The first
1692 /// dimension is now the value_type for the reference. The second
1693 /// dimension is the load [0] vs. store[1]. The third dimension
1694 /// represents the various modes for load store.
1695 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1697 /// ConvertActions - For each conversion from source type to destination type,
1698 /// keep a LegalizeAction that indicates how instruction selection should
1699 /// deal with the conversion.
1700 /// Currently, this is used only for floating->floating conversions
1701 /// (FP_EXTEND and FP_ROUND).
1702 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1704 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1705 /// LegalizeAction that indicates how instruction selection should
1706 /// deal with the condition code.
1707 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1709 ValueTypeActionImpl ValueTypeActions;
1711 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1713 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1714 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1715 /// which sets a bit in this array.
1717 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1719 /// PromoteToType - For operations that must be promoted to a specific type,
1720 /// this holds the destination type. This map should be sparse, so don't hold
1723 /// Targets add entries to this map with AddPromotedToType(..), clients access
1724 /// this with getTypeToPromoteTo(..).
1725 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1728 /// LibcallRoutineNames - Stores the name each libcall.
1730 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1732 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1733 /// of each of the comparison libcall against zero.
1734 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1736 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1738 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1741 /// When lowering \@llvm.memset this field specifies the maximum number of
1742 /// store operations that may be substituted for the call to memset. Targets
1743 /// must set this value based on the cost threshold for that target. Targets
1744 /// should assume that the memset will be done using as many of the largest
1745 /// store operations first, followed by smaller ones, if necessary, per
1746 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1747 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1748 /// store. This only applies to setting a constant array of a constant size.
1749 /// @brief Specify maximum number of store instructions per memset call.
1750 unsigned maxStoresPerMemset;
1752 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1753 /// store operations that may be substituted for a call to memcpy. Targets
1754 /// must set this value based on the cost threshold for that target. Targets
1755 /// should assume that the memcpy will be done using as many of the largest
1756 /// store operations first, followed by smaller ones, if necessary, per
1757 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1758 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1759 /// and one 1-byte store. This only applies to copying a constant array of
1761 /// @brief Specify maximum bytes of store instructions per memcpy call.
1762 unsigned maxStoresPerMemcpy;
1764 /// When lowering \@llvm.memmove this field specifies the maximum number of
1765 /// store instructions that may be substituted for a call to memmove. Targets
1766 /// must set this value based on the cost threshold for that target. Targets
1767 /// should assume that the memmove will be done using as many of the largest
1768 /// store operations first, followed by smaller ones, if necessary, per
1769 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1770 /// with 8-bit alignment would result in nine 1-byte stores. This only
1771 /// applies to copying a constant array of constant size.
1772 /// @brief Specify maximum bytes of store instructions per memmove call.
1773 unsigned maxStoresPerMemmove;
1775 /// This field specifies whether the target can benefit from code placement
1777 bool benefitFromCodePlacementOpt;
1779 } // end llvm namespace