1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/IRBuilder.h"
35 #include "llvm/MC/MCRegisterInfo.h"
36 #include "llvm/Target/TargetCallingConv.h"
37 #include "llvm/Target/TargetMachine.h"
46 class FunctionLoweringInfo;
47 class ImmutableCallSite;
49 class MachineBasicBlock;
50 class MachineFunction;
52 class MachineJumpTableInfo;
57 template<typename T> class SmallVectorImpl;
59 class TargetRegisterClass;
60 class TargetLibraryInfo;
61 class TargetLoweringObjectFile;
66 None, // No preference
67 Source, // Follow source order.
68 RegPressure, // Scheduling for lowest register pressure.
69 Hybrid, // Scheduling for both latency and register pressure.
70 ILP, // Scheduling for ILP in low register pressure mode.
71 VLIW // Scheduling for VLIW targets.
75 /// This base class for TargetLowering contains the SelectionDAG-independent
76 /// parts that can be used from the rest of CodeGen.
77 class TargetLoweringBase {
78 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
79 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
82 /// This enum indicates whether operations are valid for a target, and if not,
83 /// what action should be used to make them valid.
85 Legal, // The target natively supports this operation.
86 Promote, // This operation should be executed in a larger type.
87 Expand, // Try to expand this to other ops, otherwise use a libcall.
88 Custom // Use the LowerOperation hook to implement custom lowering.
91 /// This enum indicates whether a types are legal for a target, and if not,
92 /// what action should be used to make them valid.
93 enum LegalizeTypeAction {
94 TypeLegal, // The target natively supports this type.
95 TypePromoteInteger, // Replace this integer with a larger one.
96 TypeExpandInteger, // Split this integer into two of half the size.
97 TypeSoftenFloat, // Convert this float to a same size integer type.
98 TypeExpandFloat, // Split this float into two of half the size.
99 TypeScalarizeVector, // Replace this one-element vector with its element.
100 TypeSplitVector, // Split this vector into two of half the size.
101 TypeWidenVector // This vector should be widened into a larger vector.
104 /// LegalizeKind holds the legalization kind that needs to happen to EVT
105 /// in order to type-legalize it.
106 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
108 /// Enum that describes how the target represents true/false values.
109 enum BooleanContent {
110 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
111 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
112 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
115 /// Enum that describes what type of support for selects the target has.
116 enum SelectSupportKind {
117 ScalarValSelect, // The target supports scalar selects (ex: cmov).
118 ScalarCondVectorVal, // The target supports selects with a scalar condition
119 // and vector values (ex: cmov).
120 VectorMaskSelect // The target supports vector selects with a vector
121 // mask (ex: x86 blends).
124 static ISD::NodeType getExtendForContent(BooleanContent Content) {
126 case UndefinedBooleanContent:
127 // Extend by adding rubbish bits.
128 return ISD::ANY_EXTEND;
129 case ZeroOrOneBooleanContent:
130 // Extend by adding zero bits.
131 return ISD::ZERO_EXTEND;
132 case ZeroOrNegativeOneBooleanContent:
133 // Extend by copying the sign bit.
134 return ISD::SIGN_EXTEND;
136 llvm_unreachable("Invalid content kind");
139 /// NOTE: The constructor takes ownership of TLOF.
140 explicit TargetLoweringBase(const TargetMachine &TM,
141 const TargetLoweringObjectFile *TLOF);
142 virtual ~TargetLoweringBase();
145 /// \brief Initialize all of the actions to default values.
149 const TargetMachine &getTargetMachine() const { return TM; }
150 const DataLayout *getDataLayout() const { return DL; }
151 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
153 bool isBigEndian() const { return !IsLittleEndian; }
154 bool isLittleEndian() const { return IsLittleEndian; }
156 /// Return the pointer type for the given address space, defaults to
157 /// the pointer type from the data layout.
158 /// FIXME: The default needs to be removed once all the code is updated.
159 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
160 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
161 unsigned getPointerTypeSizeInBits(Type *Ty) const;
162 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
164 EVT getShiftAmountTy(EVT LHSTy) const;
166 /// Returns the type to be used for the index operand of:
167 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
168 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
169 virtual MVT getVectorIdxTy() const {
170 return getPointerTy();
173 /// Return true if the select operation is expensive for this target.
174 bool isSelectExpensive() const { return SelectIsExpensive; }
176 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
180 /// Return true if multiple condition registers are available.
181 bool hasMultipleConditionRegisters() const {
182 return HasMultipleConditionRegisters;
185 /// Return true if the target has BitExtract instructions.
186 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
188 /// Return the preferred vector type legalization action.
189 virtual TargetLoweringBase::LegalizeTypeAction
190 getPreferredVectorAction(EVT VT) const {
191 // The default action for one element vectors is to scalarize
192 if (VT.getVectorNumElements() == 1)
193 return TypeScalarizeVector;
194 // The default action for other vectors is to promote
195 return TypePromoteInteger;
198 // There are two general methods for expanding a BUILD_VECTOR node:
199 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
201 // 2. Build the vector on the stack and then load it.
202 // If this function returns true, then method (1) will be used, subject to
203 // the constraint that all of the necessary shuffles are legal (as determined
204 // by isShuffleMaskLegal). If this function returns false, then method (2) is
205 // always used. The vector type, and the number of defined values, are
208 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
209 unsigned DefinedValues) const {
210 return DefinedValues < 3;
213 /// Return true if integer divide is usually cheaper than a sequence of
214 /// several shifts, adds, and multiplies for this target.
215 bool isIntDivCheap() const { return IntDivIsCheap; }
217 /// Returns true if target has indicated at least one type should be bypassed.
218 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
220 /// Returns map of slow types for division or remainder with corresponding
222 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
223 return BypassSlowDivWidths;
226 /// Return true if pow2 div is cheaper than a chain of srl/add/sra.
227 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
229 /// Return true if Flow Control is an expensive operation that should be
231 bool isJumpExpensive() const { return JumpIsExpensive; }
233 /// Return true if selects are only cheaper than branches if the branch is
234 /// unlikely to be predicted right.
235 bool isPredictableSelectExpensive() const {
236 return PredictableSelectIsExpensive;
239 /// isLoadBitCastBeneficial() - Return true if the following transform
241 /// fold (conv (load x)) -> (load (conv*)x)
242 /// On architectures that don't natively support some vector loads efficiently,
243 /// casting the load to a smaller vector of larger types and loading
244 /// is more efficient, however, this can be undone by optimizations in
246 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
250 /// \brief Return if the target supports combining a
253 /// %andResult = and %val1, #imm-with-one-bit-set;
254 /// %icmpResult = icmp %andResult, 0
255 /// br i1 %icmpResult, label %dest1, label %dest2
257 /// into a single machine instruction of a form like:
259 /// brOnBitSet %register, #bitNumber, dest
261 bool isMaskAndBranchFoldingLegal() const {
262 return MaskAndBranchFoldingIsLegal;
265 /// Return true if target supports floating point exceptions.
266 bool hasFloatingPointExceptions() const {
267 return HasFloatingPointExceptions;
270 /// Return the ValueType of the result of SETCC operations. Also used to
271 /// obtain the target's preferred type for the condition operand of SELECT and
272 /// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Other
273 /// since there are no other operands to get a type hint from.
274 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
276 /// Return the ValueType for comparison libcalls. Comparions libcalls include
277 /// floating point comparion calls, and Ordered/Unordered check calls on
278 /// floating point numbers.
280 MVT::SimpleValueType getCmpLibcallReturnType() const;
282 /// For targets without i1 registers, this gives the nature of the high-bits
283 /// of boolean values held in types wider than i1.
285 /// "Boolean values" are special true/false values produced by nodes like
286 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
287 /// Not to be confused with general values promoted from i1. Some cpus
288 /// distinguish between vectors of boolean and scalars; the isVec parameter
289 /// selects between the two kinds. For example on X86 a scalar boolean should
290 /// be zero extended from i1, while the elements of a vector of booleans
291 /// should be sign extended from i1.
293 /// Some cpus also treat floating point types the same way as they treat
294 /// vectors instead of the way they treat scalars.
295 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
297 return BooleanVectorContents;
298 return isFloat ? BooleanFloatContents : BooleanContents;
301 BooleanContent getBooleanContents(EVT Type) const {
302 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
305 /// Return target scheduling preference.
306 Sched::Preference getSchedulingPreference() const {
307 return SchedPreferenceInfo;
310 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
311 /// for different nodes. This function returns the preference (or none) for
313 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
317 /// Return the register class that should be used for the specified value
319 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
320 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
321 assert(RC && "This value type is not natively supported!");
325 /// Return the 'representative' register class for the specified value
328 /// The 'representative' register class is the largest legal super-reg
329 /// register class for the register class of the value type. For example, on
330 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
331 /// register class is GR64 on x86_64.
332 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
333 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
337 /// Return the cost of the 'representative' register class for the specified
339 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
340 return RepRegClassCostForVT[VT.SimpleTy];
343 /// Return true if the target has native support for the specified value type.
344 /// This means that it has a register that directly holds it without
345 /// promotions or expansions.
346 bool isTypeLegal(EVT VT) const {
347 assert(!VT.isSimple() ||
348 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
349 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
352 class ValueTypeActionImpl {
353 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
354 /// that indicates how instruction selection should deal with the type.
355 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
358 ValueTypeActionImpl() {
359 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
362 LegalizeTypeAction getTypeAction(MVT VT) const {
363 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
366 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
367 unsigned I = VT.SimpleTy;
368 ValueTypeActions[I] = Action;
372 const ValueTypeActionImpl &getValueTypeActions() const {
373 return ValueTypeActions;
376 /// Return how we should legalize values of this type, either it is already
377 /// legal (return 'Legal') or we need to promote it to a larger type (return
378 /// 'Promote'), or we need to expand it into multiple registers of smaller
379 /// integer type (return 'Expand'). 'Custom' is not an option.
380 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
381 return getTypeConversion(Context, VT).first;
383 LegalizeTypeAction getTypeAction(MVT VT) const {
384 return ValueTypeActions.getTypeAction(VT);
387 /// For types supported by the target, this is an identity function. For
388 /// types that must be promoted to larger types, this returns the larger type
389 /// to promote to. For integer types that are larger than the largest integer
390 /// register, this contains one step in the expansion to get to the smaller
391 /// register. For illegal floating point types, this returns the integer type
393 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
394 return getTypeConversion(Context, VT).second;
397 /// For types supported by the target, this is an identity function. For
398 /// types that must be expanded (i.e. integer types that are larger than the
399 /// largest integer register or illegal floating point types), this returns
400 /// the largest legal type it will be expanded to.
401 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
402 assert(!VT.isVector());
404 switch (getTypeAction(Context, VT)) {
407 case TypeExpandInteger:
408 VT = getTypeToTransformTo(Context, VT);
411 llvm_unreachable("Type is not legal nor is it to be expanded!");
416 /// Vector types are broken down into some number of legal first class types.
417 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
418 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
419 /// turns into 4 EVT::i32 values with both PPC and X86.
421 /// This method returns the number of registers needed, and the VT for each
422 /// register. It also returns the VT and quantity of the intermediate values
423 /// before they are promoted/expanded.
424 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
426 unsigned &NumIntermediates,
427 MVT &RegisterVT) const;
429 struct IntrinsicInfo {
430 unsigned opc; // target opcode
431 EVT memVT; // memory VT
432 const Value* ptrVal; // value representing memory location
433 int offset; // offset off of ptrVal
434 unsigned size; // the size of the memory location
435 // (taken from memVT if zero)
436 unsigned align; // alignment
437 bool vol; // is volatile?
438 bool readMem; // reads memory?
439 bool writeMem; // writes memory?
441 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
442 vol(false), readMem(false), writeMem(false) {}
445 /// Given an intrinsic, checks if on the target the intrinsic will need to map
446 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
447 /// true and store the intrinsic information into the IntrinsicInfo that was
448 /// passed to the function.
449 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
450 unsigned /*Intrinsic*/) const {
454 /// Returns true if the target can instruction select the specified FP
455 /// immediate natively. If false, the legalizer will materialize the FP
456 /// immediate as a load from a constant pool.
457 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
461 /// Targets can use this to indicate that they only support *some*
462 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
463 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
465 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
470 /// Returns true if the operation can trap for the value type.
472 /// VT must be a legal type. By default, we optimistically assume most
473 /// operations don't trap except for divide and remainder.
474 virtual bool canOpTrap(unsigned Op, EVT VT) const;
476 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
477 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
478 /// a VAND with a constant pool entry.
479 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
484 /// Return how this operation should be treated: either it is legal, needs to
485 /// be promoted to a larger size, needs to be expanded to some other code
486 /// sequence, or the target has a custom expander for it.
487 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
488 if (VT.isExtended()) return Expand;
489 // If a target-specific SDNode requires legalization, require the target
490 // to provide custom legalization for it.
491 if (Op > array_lengthof(OpActions[0])) return Custom;
492 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
493 return (LegalizeAction)OpActions[I][Op];
496 /// Return true if the specified operation is legal on this target or can be
497 /// made legal with custom lowering. This is used to help guide high-level
498 /// lowering decisions.
499 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
500 return (VT == MVT::Other || isTypeLegal(VT)) &&
501 (getOperationAction(Op, VT) == Legal ||
502 getOperationAction(Op, VT) == Custom);
505 /// Return true if the specified operation is legal on this target or can be
506 /// made legal using promotion. This is used to help guide high-level lowering
508 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
509 return (VT == MVT::Other || isTypeLegal(VT)) &&
510 (getOperationAction(Op, VT) == Legal ||
511 getOperationAction(Op, VT) == Promote);
514 /// Return true if the specified operation is illegal on this target or
515 /// unlikely to be made legal with custom lowering. This is used to help guide
516 /// high-level lowering decisions.
517 bool isOperationExpand(unsigned Op, EVT VT) const {
518 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
521 /// Return true if the specified operation is legal on this target.
522 bool isOperationLegal(unsigned Op, EVT VT) const {
523 return (VT == MVT::Other || isTypeLegal(VT)) &&
524 getOperationAction(Op, VT) == Legal;
527 /// Return how this load with extension should be treated: either it is legal,
528 /// needs to be promoted to a larger size, needs to be expanded to some other
529 /// code sequence, or the target has a custom expander for it.
530 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
531 if (VT.isExtended()) return Expand;
532 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
533 assert(ExtType < ISD::LAST_LOADEXT_TYPE && I < MVT::LAST_VALUETYPE &&
534 "Table isn't big enough!");
535 return (LegalizeAction)LoadExtActions[I][ExtType];
538 /// Return true if the specified load with extension is legal on this target.
539 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
540 return VT.isSimple() &&
541 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
544 /// Return how this store with truncation should be treated: either it is
545 /// legal, needs to be promoted to a larger size, needs to be expanded to some
546 /// other code sequence, or the target has a custom expander for it.
547 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
548 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
549 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
550 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
551 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
552 "Table isn't big enough!");
553 return (LegalizeAction)TruncStoreActions[ValI][MemI];
556 /// Return true if the specified store with truncation is legal on this
558 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
559 return isTypeLegal(ValVT) && MemVT.isSimple() &&
560 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
563 /// Return how the indexed load should be treated: either it is legal, needs
564 /// to be promoted to a larger size, needs to be expanded to some other code
565 /// sequence, or the target has a custom expander for it.
567 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
568 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
569 "Table isn't big enough!");
570 unsigned Ty = (unsigned)VT.SimpleTy;
571 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
574 /// Return true if the specified indexed load is legal on this target.
575 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
576 return VT.isSimple() &&
577 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
578 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
581 /// Return how the indexed store should be treated: either it is legal, needs
582 /// to be promoted to a larger size, needs to be expanded to some other code
583 /// sequence, or the target has a custom expander for it.
585 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
586 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
587 "Table isn't big enough!");
588 unsigned Ty = (unsigned)VT.SimpleTy;
589 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
592 /// Return true if the specified indexed load is legal on this target.
593 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
594 return VT.isSimple() &&
595 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
596 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
599 /// Return how the condition code should be treated: either it is legal, needs
600 /// to be expanded to some other code sequence, or the target has a custom
603 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
604 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
605 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
606 "Table isn't big enough!");
607 // See setCondCodeAction for how this is encoded.
608 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
609 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
610 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
611 assert(Action != Promote && "Can't promote condition code!");
615 /// Return true if the specified condition code is legal on this target.
616 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
618 getCondCodeAction(CC, VT) == Legal ||
619 getCondCodeAction(CC, VT) == Custom;
623 /// If the action for this operation is to promote, this method returns the
624 /// ValueType to promote to.
625 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
626 assert(getOperationAction(Op, VT) == Promote &&
627 "This operation isn't promoted!");
629 // See if this has an explicit type specified.
630 std::map<std::pair<unsigned, MVT::SimpleValueType>,
631 MVT::SimpleValueType>::const_iterator PTTI =
632 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
633 if (PTTI != PromoteToType.end()) return PTTI->second;
635 assert((VT.isInteger() || VT.isFloatingPoint()) &&
636 "Cannot autopromote this type, add it with AddPromotedToType.");
640 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
641 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
642 "Didn't find type to promote to!");
643 } while (!isTypeLegal(NVT) ||
644 getOperationAction(Op, NVT) == Promote);
648 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
649 /// operations except for the pointer size. If AllowUnknown is true, this
650 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
651 /// otherwise it will assert.
652 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
653 // Lower scalar pointers to native pointer types.
654 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
655 return getPointerTy(PTy->getAddressSpace());
657 if (Ty->isVectorTy()) {
658 VectorType *VTy = cast<VectorType>(Ty);
659 Type *Elm = VTy->getElementType();
660 // Lower vectors of pointers to native pointer types.
661 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
662 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
663 Elm = PointerTy.getTypeForEVT(Ty->getContext());
666 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
667 VTy->getNumElements());
669 return EVT::getEVT(Ty, AllowUnknown);
672 /// Return the MVT corresponding to this LLVM type. See getValueType.
673 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
674 return getValueType(Ty, AllowUnknown).getSimpleVT();
677 /// Return the desired alignment for ByVal or InAlloca aggregate function
678 /// arguments in the caller parameter area. This is the actual alignment, not
680 virtual unsigned getByValTypeAlignment(Type *Ty) const;
682 /// Return the type of registers that this ValueType will eventually require.
683 MVT getRegisterType(MVT VT) const {
684 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
685 return RegisterTypeForVT[VT.SimpleTy];
688 /// Return the type of registers that this ValueType will eventually require.
689 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
691 assert((unsigned)VT.getSimpleVT().SimpleTy <
692 array_lengthof(RegisterTypeForVT));
693 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
698 unsigned NumIntermediates;
699 (void)getVectorTypeBreakdown(Context, VT, VT1,
700 NumIntermediates, RegisterVT);
703 if (VT.isInteger()) {
704 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
706 llvm_unreachable("Unsupported extended type!");
709 /// Return the number of registers that this ValueType will eventually
712 /// This is one for any types promoted to live in larger registers, but may be
713 /// more than one for types (like i64) that are split into pieces. For types
714 /// like i140, which are first promoted then expanded, it is the number of
715 /// registers needed to hold all the bits of the original type. For an i140
716 /// on a 32 bit machine this means 5 registers.
717 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
719 assert((unsigned)VT.getSimpleVT().SimpleTy <
720 array_lengthof(NumRegistersForVT));
721 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
726 unsigned NumIntermediates;
727 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
729 if (VT.isInteger()) {
730 unsigned BitWidth = VT.getSizeInBits();
731 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
732 return (BitWidth + RegWidth - 1) / RegWidth;
734 llvm_unreachable("Unsupported extended type!");
737 /// If true, then instruction selection should seek to shrink the FP constant
738 /// of the specified type to a smaller type in order to save space and / or
740 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
742 /// When splitting a value of the specified type into parts, does the Lo
743 /// or Hi part come first? This usually follows the endianness, except
744 /// for ppcf128, where the Hi part always comes first.
745 bool hasBigEndianPartOrdering(EVT VT) const {
746 return isBigEndian() || VT == MVT::ppcf128;
749 /// If true, the target has custom DAG combine transformations that it can
750 /// perform for the specified node.
751 bool hasTargetDAGCombine(ISD::NodeType NT) const {
752 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
753 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
756 /// \brief Get maximum # of store operations permitted for llvm.memset
758 /// This function returns the maximum number of store operations permitted
759 /// to replace a call to llvm.memset. The value is set by the target at the
760 /// performance threshold for such a replacement. If OptSize is true,
761 /// return the limit for functions that have OptSize attribute.
762 unsigned getMaxStoresPerMemset(bool OptSize) const {
763 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
766 /// \brief Get maximum # of store operations permitted for llvm.memcpy
768 /// This function returns the maximum number of store operations permitted
769 /// to replace a call to llvm.memcpy. The value is set by the target at the
770 /// performance threshold for such a replacement. If OptSize is true,
771 /// return the limit for functions that have OptSize attribute.
772 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
773 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
776 /// \brief Get maximum # of store operations permitted for llvm.memmove
778 /// This function returns the maximum number of store operations permitted
779 /// to replace a call to llvm.memmove. The value is set by the target at the
780 /// performance threshold for such a replacement. If OptSize is true,
781 /// return the limit for functions that have OptSize attribute.
782 unsigned getMaxStoresPerMemmove(bool OptSize) const {
783 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
786 /// \brief Determine if the target supports unaligned memory accesses.
788 /// This function returns true if the target allows unaligned memory accesses
789 /// of the specified type in the given address space. If true, it also returns
790 /// whether the unaligned memory access is "fast" in the last argument by
791 /// reference. This is used, for example, in situations where an array
792 /// copy/move/set is converted to a sequence of store operations. Its use
793 /// helps to ensure that such replacements don't generate code that causes an
794 /// alignment error (trap) on the target machine.
795 virtual bool allowsMisalignedMemoryAccesses(EVT,
796 unsigned AddrSpace = 0,
798 bool * /*Fast*/ = nullptr) const {
802 /// Returns the target specific optimal type for load and store operations as
803 /// a result of memset, memcpy, and memmove lowering.
805 /// If DstAlign is zero that means it's safe to destination alignment can
806 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
807 /// a need to check it against alignment requirement, probably because the
808 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
809 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
810 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
811 /// does not need to be loaded. It returns EVT::Other if the type should be
812 /// determined using generic target-independent logic.
813 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
814 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
817 bool /*MemcpyStrSrc*/,
818 MachineFunction &/*MF*/) const {
822 /// Returns true if it's safe to use load / store of the specified type to
823 /// expand memcpy / memset inline.
825 /// This is mostly true for all types except for some special cases. For
826 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
827 /// fstpl which also does type conversion. Note the specified type doesn't
828 /// have to be legal as the hook is used before type legalization.
829 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
831 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
832 bool usesUnderscoreSetJmp() const {
833 return UseUnderscoreSetJmp;
836 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
837 bool usesUnderscoreLongJmp() const {
838 return UseUnderscoreLongJmp;
841 /// Return whether the target can generate code for jump tables.
842 bool supportJumpTables() const {
843 return SupportJumpTables;
846 /// Return integer threshold on number of blocks to use jump tables rather
847 /// than if sequence.
848 int getMinimumJumpTableEntries() const {
849 return MinimumJumpTableEntries;
852 /// If a physical register, this specifies the register that
853 /// llvm.savestack/llvm.restorestack should save and restore.
854 unsigned getStackPointerRegisterToSaveRestore() const {
855 return StackPointerRegisterToSaveRestore;
858 /// If a physical register, this returns the register that receives the
859 /// exception address on entry to a landing pad.
860 unsigned getExceptionPointerRegister() const {
861 return ExceptionPointerRegister;
864 /// If a physical register, this returns the register that receives the
865 /// exception typeid on entry to a landing pad.
866 unsigned getExceptionSelectorRegister() const {
867 return ExceptionSelectorRegister;
870 /// Returns the target's jmp_buf size in bytes (if never set, the default is
872 unsigned getJumpBufSize() const {
876 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
878 unsigned getJumpBufAlignment() const {
879 return JumpBufAlignment;
882 /// Return the minimum stack alignment of an argument.
883 unsigned getMinStackArgumentAlignment() const {
884 return MinStackArgumentAlignment;
887 /// Return the minimum function alignment.
888 unsigned getMinFunctionAlignment() const {
889 return MinFunctionAlignment;
892 /// Return the preferred function alignment.
893 unsigned getPrefFunctionAlignment() const {
894 return PrefFunctionAlignment;
897 /// Return the preferred loop alignment.
898 unsigned getPrefLoopAlignment() const {
899 return PrefLoopAlignment;
902 /// Return whether the DAG builder should automatically insert fences and
903 /// reduce ordering for atomics.
904 bool getInsertFencesForAtomic() const {
905 return InsertFencesForAtomic;
908 /// Return true if the target stores stack protector cookies at a fixed offset
909 /// in some non-standard address space, and populates the address space and
910 /// offset as appropriate.
911 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
912 unsigned &/*Offset*/) const {
916 /// Returns the maximal possible offset which can be used for loads / stores
918 virtual unsigned getMaximalGlobalOffset() const {
922 /// Returns true if a cast between SrcAS and DestAS is a noop.
923 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
927 //===--------------------------------------------------------------------===//
928 /// \name Helpers for TargetTransformInfo implementations
931 /// Get the ISD node that corresponds to the Instruction class opcode.
932 int InstructionOpcodeToISD(unsigned Opcode) const;
934 /// Estimate the cost of type-legalization and the legalized type.
935 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
939 //===--------------------------------------------------------------------===//
940 /// \name Helpers for atomic expansion.
943 /// Perform a load-linked operation on Addr, returning a "Value *" with the
944 /// corresponding pointee type. This may entail some non-trivial operations to
945 /// truncate or reconstruct types that will be illegal in the backend. See
946 /// ARMISelLowering for an example implementation.
947 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
948 AtomicOrdering Ord) const {
949 llvm_unreachable("Load linked unimplemented on this target");
952 /// Perform a store-conditional operation to Addr. Return the status of the
953 /// store. This should be 0 if the store succeeded, non-zero otherwise.
954 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
955 Value *Addr, AtomicOrdering Ord) const {
956 llvm_unreachable("Store conditional unimplemented on this target");
959 /// Inserts in the IR a target-specific intrinsic specifying a fence.
960 /// It is called by AtomicExpandPass before expanding an
961 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
962 /// RMW and CmpXchg set both IsStore and IsLoad to true.
963 /// Backends with !getInsertFencesForAtomic() should keep a no-op here
964 virtual void emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
965 bool IsStore, bool IsLoad) const {
966 assert(!getInsertFencesForAtomic());
969 /// Inserts in the IR a target-specific intrinsic specifying a fence.
970 /// It is called by AtomicExpandPass after expanding an
971 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
972 /// RMW and CmpXchg set both IsStore and IsLoad to true.
973 /// Backends with !getInsertFencesForAtomic() should keep a no-op here
974 virtual void emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
975 bool IsStore, bool IsLoad) const {
976 assert(!getInsertFencesForAtomic());
979 /// Return true if the given (atomic) instruction should be expanded by the
980 /// IR-level AtomicExpand pass into a loop involving
981 /// load-linked/store-conditional pairs. Atomic stores will be expanded in the
982 /// same way as "atomic xchg" operations which ignore their output if needed.
983 virtual bool shouldExpandAtomicInIR(Instruction *Inst) const {
988 //===--------------------------------------------------------------------===//
989 // TargetLowering Configuration Methods - These methods should be invoked by
990 // the derived class constructor to configure this object for the target.
993 /// \brief Reset the operation actions based on target options.
994 virtual void resetOperationActions() {}
997 /// Specify how the target extends the result of integer and floating point
998 /// boolean values from i1 to a wider type. See getBooleanContents.
999 void setBooleanContents(BooleanContent Ty) {
1000 BooleanContents = Ty;
1001 BooleanFloatContents = Ty;
1004 /// Specify how the target extends the result of integer and floating point
1005 /// boolean values from i1 to a wider type. See getBooleanContents.
1006 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1007 BooleanContents = IntTy;
1008 BooleanFloatContents = FloatTy;
1011 /// Specify how the target extends the result of a vector boolean value from a
1012 /// vector of i1 to a wider type. See getBooleanContents.
1013 void setBooleanVectorContents(BooleanContent Ty) {
1014 BooleanVectorContents = Ty;
1017 /// Specify the target scheduling preference.
1018 void setSchedulingPreference(Sched::Preference Pref) {
1019 SchedPreferenceInfo = Pref;
1022 /// Indicate whether this target prefers to use _setjmp to implement
1023 /// llvm.setjmp or the version without _. Defaults to false.
1024 void setUseUnderscoreSetJmp(bool Val) {
1025 UseUnderscoreSetJmp = Val;
1028 /// Indicate whether this target prefers to use _longjmp to implement
1029 /// llvm.longjmp or the version without _. Defaults to false.
1030 void setUseUnderscoreLongJmp(bool Val) {
1031 UseUnderscoreLongJmp = Val;
1034 /// Indicate whether the target can generate code for jump tables.
1035 void setSupportJumpTables(bool Val) {
1036 SupportJumpTables = Val;
1039 /// Indicate the number of blocks to generate jump tables rather than if
1041 void setMinimumJumpTableEntries(int Val) {
1042 MinimumJumpTableEntries = Val;
1045 /// If set to a physical register, this specifies the register that
1046 /// llvm.savestack/llvm.restorestack should save and restore.
1047 void setStackPointerRegisterToSaveRestore(unsigned R) {
1048 StackPointerRegisterToSaveRestore = R;
1051 /// If set to a physical register, this sets the register that receives the
1052 /// exception address on entry to a landing pad.
1053 void setExceptionPointerRegister(unsigned R) {
1054 ExceptionPointerRegister = R;
1057 /// If set to a physical register, this sets the register that receives the
1058 /// exception typeid on entry to a landing pad.
1059 void setExceptionSelectorRegister(unsigned R) {
1060 ExceptionSelectorRegister = R;
1063 /// Tells the code generator not to expand operations into sequences that use
1064 /// the select operations if possible.
1065 void setSelectIsExpensive(bool isExpensive = true) {
1066 SelectIsExpensive = isExpensive;
1069 /// Tells the code generator that the target has multiple (allocatable)
1070 /// condition registers that can be used to store the results of comparisons
1071 /// for use by selects and conditional branches. With multiple condition
1072 /// registers, the code generator will not aggressively sink comparisons into
1073 /// the blocks of their users.
1074 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1075 HasMultipleConditionRegisters = hasManyRegs;
1078 /// Tells the code generator that the target has BitExtract instructions.
1079 /// The code generator will aggressively sink "shift"s into the blocks of
1080 /// their users if the users will generate "and" instructions which can be
1081 /// combined with "shift" to BitExtract instructions.
1082 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1083 HasExtractBitsInsn = hasExtractInsn;
1086 /// Tells the code generator not to expand sequence of operations into a
1087 /// separate sequences that increases the amount of flow control.
1088 void setJumpIsExpensive(bool isExpensive = true) {
1089 JumpIsExpensive = isExpensive;
1092 /// Tells the code generator that integer divide is expensive, and if
1093 /// possible, should be replaced by an alternate sequence of instructions not
1094 /// containing an integer divide.
1095 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1097 /// Tells the code generator that this target supports floating point
1098 /// exceptions and cares about preserving floating point exception behavior.
1099 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1100 HasFloatingPointExceptions = FPExceptions;
1103 /// Tells the code generator which bitwidths to bypass.
1104 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1105 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1108 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1109 /// signed divide by power of two, and let the target handle it.
1110 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
1112 /// Add the specified register class as an available regclass for the
1113 /// specified value type. This indicates the selector can handle values of
1114 /// that class natively.
1115 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1116 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1117 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1118 RegClassForVT[VT.SimpleTy] = RC;
1121 /// Remove all register classes.
1122 void clearRegisterClasses() {
1123 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1125 AvailableRegClasses.clear();
1128 /// \brief Remove all operation actions.
1129 void clearOperationActions() {
1132 /// Return the largest legal super-reg register class of the register class
1133 /// for the specified type and its associated "cost".
1134 virtual std::pair<const TargetRegisterClass*, uint8_t>
1135 findRepresentativeClass(MVT VT) const;
1137 /// Once all of the register classes are added, this allows us to compute
1138 /// derived properties we expose.
1139 void computeRegisterProperties();
1141 /// Indicate that the specified operation does not work with the specified
1142 /// type and indicate what to do about it.
1143 void setOperationAction(unsigned Op, MVT VT,
1144 LegalizeAction Action) {
1145 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1146 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1149 /// Indicate that the specified load with extension does not work with the
1150 /// specified type and indicate what to do about it.
1151 void setLoadExtAction(unsigned ExtType, MVT VT,
1152 LegalizeAction Action) {
1153 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
1154 "Table isn't big enough!");
1155 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1158 /// Indicate that the specified truncating store does not work with the
1159 /// specified type and indicate what to do about it.
1160 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1161 LegalizeAction Action) {
1162 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
1163 "Table isn't big enough!");
1164 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1167 /// Indicate that the specified indexed load does or does not work with the
1168 /// specified type and indicate what to do abort it.
1170 /// NOTE: All indexed mode loads are initialized to Expand in
1171 /// TargetLowering.cpp
1172 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1173 LegalizeAction Action) {
1174 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1175 (unsigned)Action < 0xf && "Table isn't big enough!");
1176 // Load action are kept in the upper half.
1177 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1178 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1181 /// Indicate that the specified indexed store does or does not work with the
1182 /// specified type and indicate what to do about it.
1184 /// NOTE: All indexed mode stores are initialized to Expand in
1185 /// TargetLowering.cpp
1186 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1187 LegalizeAction Action) {
1188 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1189 (unsigned)Action < 0xf && "Table isn't big enough!");
1190 // Store action are kept in the lower half.
1191 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1192 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1195 /// Indicate that the specified condition code is or isn't supported on the
1196 /// target and indicate what to do about it.
1197 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1198 LegalizeAction Action) {
1199 assert(VT < MVT::LAST_VALUETYPE &&
1200 (unsigned)CC < array_lengthof(CondCodeActions) &&
1201 "Table isn't big enough!");
1202 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1203 /// value and the upper 27 bits index into the second dimension of the array
1204 /// to select what 32-bit value to use.
1205 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1206 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1207 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1210 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1211 /// to trying a larger integer/fp until it can find one that works. If that
1212 /// default is insufficient, this method can be used by the target to override
1214 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1215 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1218 /// Targets should invoke this method for each target independent node that
1219 /// they want to provide a custom DAG combiner for by implementing the
1220 /// PerformDAGCombine virtual method.
1221 void setTargetDAGCombine(ISD::NodeType NT) {
1222 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1223 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1226 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1227 void setJumpBufSize(unsigned Size) {
1231 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1233 void setJumpBufAlignment(unsigned Align) {
1234 JumpBufAlignment = Align;
1237 /// Set the target's minimum function alignment (in log2(bytes))
1238 void setMinFunctionAlignment(unsigned Align) {
1239 MinFunctionAlignment = Align;
1242 /// Set the target's preferred function alignment. This should be set if
1243 /// there is a performance benefit to higher-than-minimum alignment (in
1245 void setPrefFunctionAlignment(unsigned Align) {
1246 PrefFunctionAlignment = Align;
1249 /// Set the target's preferred loop alignment. Default alignment is zero, it
1250 /// means the target does not care about loop alignment. The alignment is
1251 /// specified in log2(bytes).
1252 void setPrefLoopAlignment(unsigned Align) {
1253 PrefLoopAlignment = Align;
1256 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1257 void setMinStackArgumentAlignment(unsigned Align) {
1258 MinStackArgumentAlignment = Align;
1261 /// Set if the DAG builder should automatically insert fences and reduce the
1262 /// order of atomic memory operations to Monotonic.
1263 void setInsertFencesForAtomic(bool fence) {
1264 InsertFencesForAtomic = fence;
1268 //===--------------------------------------------------------------------===//
1269 // Addressing mode description hooks (used by LSR etc).
1272 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1273 /// instructions reading the address. This allows as much computation as
1274 /// possible to be done in the address mode for that operand. This hook lets
1275 /// targets also pass back when this should be done on intrinsics which
1277 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1278 SmallVectorImpl<Value*> &/*Ops*/,
1279 Type *&/*AccessTy*/) const {
1283 /// This represents an addressing mode of:
1284 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1285 /// If BaseGV is null, there is no BaseGV.
1286 /// If BaseOffs is zero, there is no base offset.
1287 /// If HasBaseReg is false, there is no base register.
1288 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1291 GlobalValue *BaseGV;
1295 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1298 /// Return true if the addressing mode represented by AM is legal for this
1299 /// target, for a load/store of the specified type.
1301 /// The type may be VoidTy, in which case only return true if the addressing
1302 /// mode is legal for a load/store of any legal type. TODO: Handle
1303 /// pre/postinc as well.
1304 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1306 /// \brief Return the cost of the scaling factor used in the addressing mode
1307 /// represented by AM for this target, for a load/store of the specified type.
1309 /// If the AM is supported, the return value must be >= 0.
1310 /// If the AM is not supported, it returns a negative value.
1311 /// TODO: Handle pre/postinc as well.
1312 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1313 // Default: assume that any scaling factor used in a legal AM is free.
1314 if (isLegalAddressingMode(AM, Ty)) return 0;
1318 /// Return true if the specified immediate is legal icmp immediate, that is
1319 /// the target has icmp instructions which can compare a register against the
1320 /// immediate without having to materialize the immediate into a register.
1321 virtual bool isLegalICmpImmediate(int64_t) const {
1325 /// Return true if the specified immediate is legal add immediate, that is the
1326 /// target has add instructions which can add a register with the immediate
1327 /// without having to materialize the immediate into a register.
1328 virtual bool isLegalAddImmediate(int64_t) const {
1332 /// Return true if it's significantly cheaper to shift a vector by a uniform
1333 /// scalar than by an amount which will vary across each lane. On x86, for
1334 /// example, there is a "psllw" instruction for the former case, but no simple
1335 /// instruction for a general "a << b" operation on vectors.
1336 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1340 /// Return true if it's free to truncate a value of type Ty1 to type
1341 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1342 /// by referencing its sub-register AX.
1343 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1347 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1348 /// whether a call is in tail position. Typically this means that both results
1349 /// would be assigned to the same register or stack slot, but it could mean
1350 /// the target performs adequate checks of its own before proceeding with the
1352 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1356 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1360 /// Return true if any actual instruction that defines a value of type Ty1
1361 /// implicitly zero-extends the value to Ty2 in the result register.
1363 /// This does not necessarily include registers defined in unknown ways, such
1364 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1365 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1366 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1367 /// values implicit zero-extend the result out to 64 bits.
1368 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1372 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1376 /// Return true if the target supplies and combines to a paired load
1377 /// two loaded values of type LoadedType next to each other in memory.
1378 /// RequiredAlignment gives the minimal alignment constraints that must be met
1379 /// to be able to select this paired load.
1381 /// This information is *not* used to generate actual paired loads, but it is
1382 /// used to generate a sequence of loads that is easier to combine into a
1384 /// For instance, something like this:
1385 /// a = load i64* addr
1386 /// b = trunc i64 a to i32
1387 /// c = lshr i64 a, 32
1388 /// d = trunc i64 c to i32
1389 /// will be optimized into:
1390 /// b = load i32* addr1
1391 /// d = load i32* addr2
1392 /// Where addr1 = addr2 +/- sizeof(i32).
1394 /// In other words, unless the target performs a post-isel load combining,
1395 /// this information should not be provided because it will generate more
1397 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1398 unsigned & /*RequiredAligment*/) const {
1402 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1403 unsigned & /*RequiredAligment*/) const {
1407 /// Return true if zero-extending the specific node Val to type VT2 is free
1408 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1409 /// because it's folded such as X86 zero-extending loads).
1410 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1411 return isZExtFree(Val.getValueType(), VT2);
1414 /// Return true if an fneg operation is free to the point where it is never
1415 /// worthwhile to replace it with a bitwise operation.
1416 virtual bool isFNegFree(EVT VT) const {
1417 assert(VT.isFloatingPoint());
1421 /// Return true if an fabs operation is free to the point where it is never
1422 /// worthwhile to replace it with a bitwise operation.
1423 virtual bool isFAbsFree(EVT VT) const {
1424 assert(VT.isFloatingPoint());
1428 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1429 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1430 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1432 /// NOTE: This may be called before legalization on types for which FMAs are
1433 /// not legal, but should return true if those types will eventually legalize
1434 /// to types that support FMAs. After legalization, it will only be called on
1435 /// types that support FMAs (via Legal or Custom actions)
1436 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1440 /// Return true if it's profitable to narrow operations of type VT1 to
1441 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1443 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1447 /// \brief Return true if it is beneficial to convert a load of a constant to
1448 /// just the constant itself.
1449 /// On some targets it might be more efficient to use a combination of
1450 /// arithmetic instructions to materialize the constant instead of loading it
1451 /// from a constant pool.
1452 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1456 //===--------------------------------------------------------------------===//
1457 // Runtime Library hooks
1460 /// Rename the default libcall routine name for the specified libcall.
1461 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1462 LibcallRoutineNames[Call] = Name;
1465 /// Get the libcall routine name for the specified libcall.
1466 const char *getLibcallName(RTLIB::Libcall Call) const {
1467 return LibcallRoutineNames[Call];
1470 /// Override the default CondCode to be used to test the result of the
1471 /// comparison libcall against zero.
1472 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1473 CmpLibcallCCs[Call] = CC;
1476 /// Get the CondCode that's to be used to test the result of the comparison
1477 /// libcall against zero.
1478 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1479 return CmpLibcallCCs[Call];
1482 /// Set the CallingConv that should be used for the specified libcall.
1483 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1484 LibcallCallingConvs[Call] = CC;
1487 /// Get the CallingConv that should be used for the specified libcall.
1488 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1489 return LibcallCallingConvs[Call];
1493 const TargetMachine &TM;
1494 const DataLayout *DL;
1495 const TargetLoweringObjectFile &TLOF;
1497 /// True if this is a little endian target.
1498 bool IsLittleEndian;
1500 /// Tells the code generator not to expand operations into sequences that use
1501 /// the select operations if possible.
1502 bool SelectIsExpensive;
1504 /// Tells the code generator that the target has multiple (allocatable)
1505 /// condition registers that can be used to store the results of comparisons
1506 /// for use by selects and conditional branches. With multiple condition
1507 /// registers, the code generator will not aggressively sink comparisons into
1508 /// the blocks of their users.
1509 bool HasMultipleConditionRegisters;
1511 /// Tells the code generator that the target has BitExtract instructions.
1512 /// The code generator will aggressively sink "shift"s into the blocks of
1513 /// their users if the users will generate "and" instructions which can be
1514 /// combined with "shift" to BitExtract instructions.
1515 bool HasExtractBitsInsn;
1517 /// Tells the code generator not to expand integer divides by constants into a
1518 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1519 /// model is in place. If we ever optimize for size, this will be set to true
1520 /// unconditionally.
1523 /// Tells the code generator to bypass slow divide or remainder
1524 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1525 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1526 /// div/rem when the operands are positive and less than 256.
1527 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1529 /// Tells the code generator that it shouldn't generate srl/add/sra for a
1530 /// signed divide by power of two, and let the target handle it.
1531 bool Pow2DivIsCheap;
1533 /// Tells the code generator that it shouldn't generate extra flow control
1534 /// instructions and should attempt to combine flow control instructions via
1536 bool JumpIsExpensive;
1538 /// Whether the target supports or cares about preserving floating point
1539 /// exception behavior.
1540 bool HasFloatingPointExceptions;
1542 /// This target prefers to use _setjmp to implement llvm.setjmp.
1544 /// Defaults to false.
1545 bool UseUnderscoreSetJmp;
1547 /// This target prefers to use _longjmp to implement llvm.longjmp.
1549 /// Defaults to false.
1550 bool UseUnderscoreLongJmp;
1552 /// Whether the target can generate code for jumptables. If it's not true,
1553 /// then each jumptable must be lowered into if-then-else's.
1554 bool SupportJumpTables;
1556 /// Number of blocks threshold to use jump tables.
1557 int MinimumJumpTableEntries;
1559 /// Information about the contents of the high-bits in boolean values held in
1560 /// a type wider than i1. See getBooleanContents.
1561 BooleanContent BooleanContents;
1563 /// Information about the contents of the high-bits in boolean values held in
1564 /// a type wider than i1. See getBooleanContents.
1565 BooleanContent BooleanFloatContents;
1567 /// Information about the contents of the high-bits in boolean vector values
1568 /// when the element type is wider than i1. See getBooleanContents.
1569 BooleanContent BooleanVectorContents;
1571 /// The target scheduling preference: shortest possible total cycles or lowest
1573 Sched::Preference SchedPreferenceInfo;
1575 /// The size, in bytes, of the target's jmp_buf buffers
1576 unsigned JumpBufSize;
1578 /// The alignment, in bytes, of the target's jmp_buf buffers
1579 unsigned JumpBufAlignment;
1581 /// The minimum alignment that any argument on the stack needs to have.
1582 unsigned MinStackArgumentAlignment;
1584 /// The minimum function alignment (used when optimizing for size, and to
1585 /// prevent explicitly provided alignment from leading to incorrect code).
1586 unsigned MinFunctionAlignment;
1588 /// The preferred function alignment (used when alignment unspecified and
1589 /// optimizing for speed).
1590 unsigned PrefFunctionAlignment;
1592 /// The preferred loop alignment.
1593 unsigned PrefLoopAlignment;
1595 /// Whether the DAG builder should automatically insert fences and reduce
1596 /// ordering for atomics. (This will be set for for most architectures with
1597 /// weak memory ordering.)
1598 bool InsertFencesForAtomic;
1600 /// If set to a physical register, this specifies the register that
1601 /// llvm.savestack/llvm.restorestack should save and restore.
1602 unsigned StackPointerRegisterToSaveRestore;
1604 /// If set to a physical register, this specifies the register that receives
1605 /// the exception address on entry to a landing pad.
1606 unsigned ExceptionPointerRegister;
1608 /// If set to a physical register, this specifies the register that receives
1609 /// the exception typeid on entry to a landing pad.
1610 unsigned ExceptionSelectorRegister;
1612 /// This indicates the default register class to use for each ValueType the
1613 /// target supports natively.
1614 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1615 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1616 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1618 /// This indicates the "representative" register class to use for each
1619 /// ValueType the target supports natively. This information is used by the
1620 /// scheduler to track register pressure. By default, the representative
1621 /// register class is the largest legal super-reg register class of the
1622 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1623 /// representative class would be GR32.
1624 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1626 /// This indicates the "cost" of the "representative" register class for each
1627 /// ValueType. The cost is used by the scheduler to approximate register
1629 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1631 /// For any value types we are promoting or expanding, this contains the value
1632 /// type that we are changing to. For Expanded types, this contains one step
1633 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1634 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1635 /// the same type (e.g. i32 -> i32).
1636 MVT TransformToType[MVT::LAST_VALUETYPE];
1638 /// For each operation and each value type, keep a LegalizeAction that
1639 /// indicates how instruction selection should deal with the operation. Most
1640 /// operations are Legal (aka, supported natively by the target), but
1641 /// operations that are not should be described. Note that operations on
1642 /// non-legal value types are not described here.
1643 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1645 /// For each load extension type and each value type, keep a LegalizeAction
1646 /// that indicates how instruction selection should deal with a load of a
1647 /// specific value type and extension type.
1648 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1650 /// For each value type pair keep a LegalizeAction that indicates whether a
1651 /// truncating store of a specific value type and truncating type is legal.
1652 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1654 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1655 /// that indicates how instruction selection should deal with the load /
1658 /// The first dimension is the value_type for the reference. The second
1659 /// dimension represents the various modes for load store.
1660 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1662 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1663 /// indicates how instruction selection should deal with the condition code.
1665 /// Because each CC action takes up 2 bits, we need to have the array size be
1666 /// large enough to fit all of the value types. This can be done by rounding
1667 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1668 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1670 ValueTypeActionImpl ValueTypeActions;
1674 getTypeConversion(LLVMContext &Context, EVT VT) const {
1675 // If this is a simple type, use the ComputeRegisterProp mechanism.
1676 if (VT.isSimple()) {
1677 MVT SVT = VT.getSimpleVT();
1678 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1679 MVT NVT = TransformToType[SVT.SimpleTy];
1680 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1683 (LA == TypeLegal || LA == TypeSoftenFloat ||
1684 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1685 && "Promote may not follow Expand or Promote");
1687 if (LA == TypeSplitVector)
1688 return LegalizeKind(LA, EVT::getVectorVT(Context,
1689 SVT.getVectorElementType(),
1690 SVT.getVectorNumElements()/2));
1691 if (LA == TypeScalarizeVector)
1692 return LegalizeKind(LA, SVT.getVectorElementType());
1693 return LegalizeKind(LA, NVT);
1696 // Handle Extended Scalar Types.
1697 if (!VT.isVector()) {
1698 assert(VT.isInteger() && "Float types must be simple");
1699 unsigned BitSize = VT.getSizeInBits();
1700 // First promote to a power-of-two size, then expand if necessary.
1701 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1702 EVT NVT = VT.getRoundIntegerType(Context);
1703 assert(NVT != VT && "Unable to round integer VT");
1704 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1705 // Avoid multi-step promotion.
1706 if (NextStep.first == TypePromoteInteger) return NextStep;
1707 // Return rounded integer type.
1708 return LegalizeKind(TypePromoteInteger, NVT);
1711 return LegalizeKind(TypeExpandInteger,
1712 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1715 // Handle vector types.
1716 unsigned NumElts = VT.getVectorNumElements();
1717 EVT EltVT = VT.getVectorElementType();
1719 // Vectors with only one element are always scalarized.
1721 return LegalizeKind(TypeScalarizeVector, EltVT);
1723 // Try to widen vector elements until the element type is a power of two and
1724 // promote it to a legal type later on, for example:
1725 // <3 x i8> -> <4 x i8> -> <4 x i32>
1726 if (EltVT.isInteger()) {
1727 // Vectors with a number of elements that is not a power of two are always
1728 // widened, for example <3 x i8> -> <4 x i8>.
1729 if (!VT.isPow2VectorType()) {
1730 NumElts = (unsigned)NextPowerOf2(NumElts);
1731 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1732 return LegalizeKind(TypeWidenVector, NVT);
1735 // Examine the element type.
1736 LegalizeKind LK = getTypeConversion(Context, EltVT);
1738 // If type is to be expanded, split the vector.
1739 // <4 x i140> -> <2 x i140>
1740 if (LK.first == TypeExpandInteger)
1741 return LegalizeKind(TypeSplitVector,
1742 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1744 // Promote the integer element types until a legal vector type is found
1745 // or until the element integer type is too big. If a legal type was not
1746 // found, fallback to the usual mechanism of widening/splitting the
1748 EVT OldEltVT = EltVT;
1750 // Increase the bitwidth of the element to the next pow-of-two
1751 // (which is greater than 8 bits).
1752 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1753 ).getRoundIntegerType(Context);
1755 // Stop trying when getting a non-simple element type.
1756 // Note that vector elements may be greater than legal vector element
1757 // types. Example: X86 XMM registers hold 64bit element on 32bit
1759 if (!EltVT.isSimple()) break;
1761 // Build a new vector type and check if it is legal.
1762 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1763 // Found a legal promoted vector type.
1764 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1765 return LegalizeKind(TypePromoteInteger,
1766 EVT::getVectorVT(Context, EltVT, NumElts));
1769 // Reset the type to the unexpanded type if we did not find a legal vector
1770 // type with a promoted vector element type.
1774 // Try to widen the vector until a legal type is found.
1775 // If there is no wider legal type, split the vector.
1777 // Round up to the next power of 2.
1778 NumElts = (unsigned)NextPowerOf2(NumElts);
1780 // If there is no simple vector type with this many elements then there
1781 // cannot be a larger legal vector type. Note that this assumes that
1782 // there are no skipped intermediate vector types in the simple types.
1783 if (!EltVT.isSimple()) break;
1784 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1785 if (LargerVector == MVT()) break;
1787 // If this type is legal then widen the vector.
1788 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1789 return LegalizeKind(TypeWidenVector, LargerVector);
1792 // Widen odd vectors to next power of two.
1793 if (!VT.isPow2VectorType()) {
1794 EVT NVT = VT.getPow2VectorType(Context);
1795 return LegalizeKind(TypeWidenVector, NVT);
1798 // Vectors with illegal element types are expanded.
1799 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1800 return LegalizeKind(TypeSplitVector, NVT);
1804 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1806 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1807 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1810 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1812 /// For operations that must be promoted to a specific type, this holds the
1813 /// destination type. This map should be sparse, so don't hold it as an
1816 /// Targets add entries to this map with AddPromotedToType(..), clients access
1817 /// this with getTypeToPromoteTo(..).
1818 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1821 /// Stores the name each libcall.
1822 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1824 /// The ISD::CondCode that should be used to test the result of each of the
1825 /// comparison libcall against zero.
1826 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1828 /// Stores the CallingConv that should be used for each libcall.
1829 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1832 /// \brief Specify maximum number of store instructions per memset call.
1834 /// When lowering \@llvm.memset this field specifies the maximum number of
1835 /// store operations that may be substituted for the call to memset. Targets
1836 /// must set this value based on the cost threshold for that target. Targets
1837 /// should assume that the memset will be done using as many of the largest
1838 /// store operations first, followed by smaller ones, if necessary, per
1839 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1840 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1841 /// store. This only applies to setting a constant array of a constant size.
1842 unsigned MaxStoresPerMemset;
1844 /// Maximum number of stores operations that may be substituted for the call
1845 /// to memset, used for functions with OptSize attribute.
1846 unsigned MaxStoresPerMemsetOptSize;
1848 /// \brief Specify maximum bytes of store instructions per memcpy call.
1850 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1851 /// store operations that may be substituted for a call to memcpy. Targets
1852 /// must set this value based on the cost threshold for that target. Targets
1853 /// should assume that the memcpy will be done using as many of the largest
1854 /// store operations first, followed by smaller ones, if necessary, per
1855 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1856 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1857 /// and one 1-byte store. This only applies to copying a constant array of
1859 unsigned MaxStoresPerMemcpy;
1861 /// Maximum number of store operations that may be substituted for a call to
1862 /// memcpy, used for functions with OptSize attribute.
1863 unsigned MaxStoresPerMemcpyOptSize;
1865 /// \brief Specify maximum bytes of store instructions per memmove call.
1867 /// When lowering \@llvm.memmove this field specifies the maximum number of
1868 /// store instructions that may be substituted for a call to memmove. Targets
1869 /// must set this value based on the cost threshold for that target. Targets
1870 /// should assume that the memmove will be done using as many of the largest
1871 /// store operations first, followed by smaller ones, if necessary, per
1872 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1873 /// with 8-bit alignment would result in nine 1-byte stores. This only
1874 /// applies to copying a constant array of constant size.
1875 unsigned MaxStoresPerMemmove;
1877 /// Maximum number of store instructions that may be substituted for a call to
1878 /// memmove, used for functions with OpSize attribute.
1879 unsigned MaxStoresPerMemmoveOptSize;
1881 /// Tells the code generator that select is more expensive than a branch if
1882 /// the branch is usually predicted right.
1883 bool PredictableSelectIsExpensive;
1885 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1886 /// a mask of a single bit, a compare, and a branch into a single instruction.
1887 bool MaskAndBranchFoldingIsLegal;
1890 /// Return true if the value types that can be represented by the specified
1891 /// register class are all legal.
1892 bool isLegalRC(const TargetRegisterClass *RC) const;
1894 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1895 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1896 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1899 /// This class defines information used to lower LLVM code to legal SelectionDAG
1900 /// operators that the target instruction selector can accept natively.
1902 /// This class also defines callbacks that targets must implement to lower
1903 /// target-specific constructs to SelectionDAG operators.
1904 class TargetLowering : public TargetLoweringBase {
1905 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1906 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1909 /// NOTE: The constructor takes ownership of TLOF.
1910 explicit TargetLowering(const TargetMachine &TM,
1911 const TargetLoweringObjectFile *TLOF);
1913 /// Returns true by value, base pointer and offset pointer and addressing mode
1914 /// by reference if the node's address can be legally represented as
1915 /// pre-indexed load / store address.
1916 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1917 SDValue &/*Offset*/,
1918 ISD::MemIndexedMode &/*AM*/,
1919 SelectionDAG &/*DAG*/) const {
1923 /// Returns true by value, base pointer and offset pointer and addressing mode
1924 /// by reference if this node can be combined with a load / store to form a
1925 /// post-indexed load / store.
1926 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1928 SDValue &/*Offset*/,
1929 ISD::MemIndexedMode &/*AM*/,
1930 SelectionDAG &/*DAG*/) const {
1934 /// Return the entry encoding for a jump table in the current function. The
1935 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
1936 virtual unsigned getJumpTableEncoding() const;
1938 virtual const MCExpr *
1939 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1940 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1941 MCContext &/*Ctx*/) const {
1942 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1945 /// Returns relocation base for the given PIC jumptable.
1946 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1947 SelectionDAG &DAG) const;
1949 /// This returns the relocation base for the given PIC jumptable, the same as
1950 /// getPICJumpTableRelocBase, but as an MCExpr.
1951 virtual const MCExpr *
1952 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1953 unsigned JTI, MCContext &Ctx) const;
1955 /// Return true if folding a constant offset with the given GlobalAddress is
1956 /// legal. It is frequently not legal in PIC relocation models.
1957 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1959 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1960 SDValue &Chain) const;
1962 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1963 SDValue &NewLHS, SDValue &NewRHS,
1964 ISD::CondCode &CCCode, SDLoc DL) const;
1966 /// Returns a pair of (return value, chain).
1967 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
1968 EVT RetVT, const SDValue *Ops,
1969 unsigned NumOps, bool isSigned,
1970 SDLoc dl, bool doesNotReturn = false,
1971 bool isReturnValueUsed = true) const;
1973 //===--------------------------------------------------------------------===//
1974 // TargetLowering Optimization Methods
1977 /// A convenience struct that encapsulates a DAG, and two SDValues for
1978 /// returning information from TargetLowering to its clients that want to
1980 struct TargetLoweringOpt {
1987 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1989 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1991 bool LegalTypes() const { return LegalTys; }
1992 bool LegalOperations() const { return LegalOps; }
1994 bool CombineTo(SDValue O, SDValue N) {
2000 /// Check to see if the specified operand of the specified instruction is a
2001 /// constant integer. If so, check to see if there are any bits set in the
2002 /// constant that are not demanded. If so, shrink the constant and return
2004 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2006 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2007 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2008 /// generalized for targets with other types of implicit widening casts.
2009 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2013 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2014 /// result of Op are ever used downstream. If we can use this information to
2015 /// simplify Op, create a new simplified DAG node and return true, returning
2016 /// the original and new nodes in Old and New. Otherwise, analyze the
2017 /// expression and return a mask of KnownOne and KnownZero bits for the
2018 /// expression (used to simplify the caller). The KnownZero/One bits may only
2019 /// be accurate for those bits in the DemandedMask.
2020 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2021 APInt &KnownZero, APInt &KnownOne,
2022 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2024 /// Determine which of the bits specified in Mask are known to be either zero
2025 /// or one and return them in the KnownZero/KnownOne bitsets.
2026 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2029 const SelectionDAG &DAG,
2030 unsigned Depth = 0) const;
2032 /// This method can be implemented by targets that want to expose additional
2033 /// information about sign bits to the DAG Combiner.
2034 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2035 const SelectionDAG &DAG,
2036 unsigned Depth = 0) const;
2038 struct DAGCombinerInfo {
2039 void *DC; // The DAG Combiner object.
2041 bool CalledByLegalizer;
2045 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2046 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2048 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2049 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2050 bool isAfterLegalizeVectorOps() const {
2051 return Level == AfterLegalizeDAG;
2053 CombineLevel getDAGCombineLevel() { return Level; }
2054 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2056 void AddToWorklist(SDNode *N);
2057 void RemoveFromWorklist(SDNode *N);
2058 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
2060 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2061 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2063 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2066 /// Return if the N is a constant or constant vector equal to the true value
2067 /// from getBooleanContents().
2068 bool isConstTrueVal(const SDNode *N) const;
2070 /// Return if the N is a constant or constant vector equal to the false value
2071 /// from getBooleanContents().
2072 bool isConstFalseVal(const SDNode *N) const;
2074 /// Try to simplify a setcc built with the specified operands and cc. If it is
2075 /// unable to simplify it, return a null SDValue.
2076 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2077 ISD::CondCode Cond, bool foldBooleans,
2078 DAGCombinerInfo &DCI, SDLoc dl) const;
2080 /// Returns true (and the GlobalValue and the offset) if the node is a
2081 /// GlobalAddress + offset.
2083 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2085 /// This method will be invoked for all target nodes and for any
2086 /// target-independent nodes that the target has registered with invoke it
2089 /// The semantics are as follows:
2091 /// SDValue.Val == 0 - No change was made
2092 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2093 /// otherwise - N should be replaced by the returned Operand.
2095 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2096 /// more complex transformations.
2098 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2100 /// Return true if it is profitable to move a following shift through this
2101 // node, adjusting any immediate operands as necessary to preserve semantics.
2102 // This transformation may not be desirable if it disrupts a particularly
2103 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2104 // By default, it returns true.
2105 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2109 /// Return true if the target has native support for the specified value type
2110 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2111 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2112 /// and some i16 instructions are slow.
2113 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2114 // By default, assume all legal types are desirable.
2115 return isTypeLegal(VT);
2118 /// Return true if it is profitable for dag combiner to transform a floating
2119 /// point op of specified opcode to a equivalent op of an integer
2120 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2121 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2126 /// This method query the target whether it is beneficial for dag combiner to
2127 /// promote the specified node. If true, it should return the desired
2128 /// promotion type by reference.
2129 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2133 //===--------------------------------------------------------------------===//
2134 // Lowering methods - These methods must be implemented by targets so that
2135 // the SelectionDAGBuilder code knows how to lower these.
2138 /// This hook must be implemented to lower the incoming (formal) arguments,
2139 /// described by the Ins array, into the specified DAG. The implementation
2140 /// should fill in the InVals array with legal-type argument values, and
2141 /// return the resulting token chain value.
2144 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2146 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2147 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2148 SmallVectorImpl<SDValue> &/*InVals*/) const {
2149 llvm_unreachable("Not Implemented");
2152 struct ArgListEntry {
2161 bool isInAlloca : 1;
2162 bool isReturned : 1;
2165 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2166 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2167 isReturned(false), Alignment(0) { }
2169 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2171 typedef std::vector<ArgListEntry> ArgListTy;
2173 /// This structure contains all information that is necessary for lowering
2174 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2175 /// needs to lower a call, and targets will see this struct in their LowerCall
2177 struct CallLoweringInfo {
2184 bool DoesNotReturn : 1;
2185 bool IsReturnValueUsed : 1;
2187 // IsTailCall should be modified by implementations of
2188 // TargetLowering::LowerCall that perform tail call conversions.
2191 unsigned NumFixedArgs;
2192 CallingConv::ID CallConv;
2197 ImmutableCallSite *CS;
2198 SmallVector<ISD::OutputArg, 32> Outs;
2199 SmallVector<SDValue, 32> OutVals;
2200 SmallVector<ISD::InputArg, 32> Ins;
2202 CallLoweringInfo(SelectionDAG &DAG)
2203 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2204 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2205 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2206 DAG(DAG), CS(nullptr) {}
2208 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2213 CallLoweringInfo &setChain(SDValue InChain) {
2218 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2219 SDValue Target, ArgListTy &&ArgsList,
2220 unsigned FixedArgs = -1) {
2225 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2226 Args = std::move(ArgsList);
2230 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2231 SDValue Target, ArgListTy &&ArgsList,
2232 ImmutableCallSite &Call) {
2235 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2236 DoesNotReturn = Call.doesNotReturn();
2237 IsVarArg = FTy->isVarArg();
2238 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2239 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2240 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2244 CallConv = Call.getCallingConv();
2245 NumFixedArgs = FTy->getNumParams();
2246 Args = std::move(ArgsList);
2253 CallLoweringInfo &setInRegister(bool Value = true) {
2258 CallLoweringInfo &setNoReturn(bool Value = true) {
2259 DoesNotReturn = Value;
2263 CallLoweringInfo &setVarArg(bool Value = true) {
2268 CallLoweringInfo &setTailCall(bool Value = true) {
2273 CallLoweringInfo &setDiscardResult(bool Value = true) {
2274 IsReturnValueUsed = !Value;
2278 CallLoweringInfo &setSExtResult(bool Value = true) {
2283 CallLoweringInfo &setZExtResult(bool Value = true) {
2288 ArgListTy &getArgs() {
2293 /// This function lowers an abstract call to a function into an actual call.
2294 /// This returns a pair of operands. The first element is the return value
2295 /// for the function (if RetTy is not VoidTy). The second element is the
2296 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2297 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2299 /// This hook must be implemented to lower calls into the the specified
2300 /// DAG. The outgoing arguments to the call are described by the Outs array,
2301 /// and the values to be returned by the call are described by the Ins
2302 /// array. The implementation should fill in the InVals array with legal-type
2303 /// return values from the call, and return the resulting token chain value.
2305 LowerCall(CallLoweringInfo &/*CLI*/,
2306 SmallVectorImpl<SDValue> &/*InVals*/) const {
2307 llvm_unreachable("Not Implemented");
2310 /// Target-specific cleanup for formal ByVal parameters.
2311 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2313 /// This hook should be implemented to check whether the return values
2314 /// described by the Outs array can fit into the return registers. If false
2315 /// is returned, an sret-demotion is performed.
2316 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2317 MachineFunction &/*MF*/, bool /*isVarArg*/,
2318 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2319 LLVMContext &/*Context*/) const
2321 // Return true by default to get preexisting behavior.
2325 /// This hook must be implemented to lower outgoing return values, described
2326 /// by the Outs array, into the specified DAG. The implementation should
2327 /// return the resulting token chain value.
2329 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2331 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2332 const SmallVectorImpl<SDValue> &/*OutVals*/,
2333 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2334 llvm_unreachable("Not Implemented");
2337 /// Return true if result of the specified node is used by a return node
2338 /// only. It also compute and return the input chain for the tail call.
2340 /// This is used to determine whether it is possible to codegen a libcall as
2341 /// tail call at legalization time.
2342 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2346 /// Return true if the target may be able emit the call instruction as a tail
2347 /// call. This is used by optimization passes to determine if it's profitable
2348 /// to duplicate return instructions to enable tailcall optimization.
2349 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2353 /// Return the builtin name for the __builtin___clear_cache intrinsic
2354 /// Default is to invoke the clear cache library call
2355 virtual const char * getClearCacheBuiltinName() const {
2356 return "__clear_cache";
2359 /// Return the register ID of the name passed in. Used by named register
2360 /// global variables extension. There is no target-independent behaviour
2361 /// so the default action is to bail.
2362 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2363 report_fatal_error("Named registers not implemented for this target");
2366 /// Return the type that should be used to zero or sign extend a
2367 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2368 /// convention requires the return type to be promoted, but this is not true
2369 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2370 /// calling conventions. The frontend should handle this and include all of
2371 /// the necessary information.
2372 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2373 ISD::NodeType /*ExtendKind*/) const {
2374 EVT MinVT = getRegisterType(Context, MVT::i32);
2375 return VT.bitsLT(MinVT) ? MinVT : VT;
2378 /// For some targets, an LLVM struct type must be broken down into multiple
2379 /// simple types, but the calling convention specifies that the entire struct
2380 /// must be passed in a block of consecutive registers.
2382 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2383 bool isVarArg) const {
2387 /// Returns a 0 terminated array of registers that can be safely used as
2388 /// scratch registers.
2389 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2393 /// This callback is used to prepare for a volatile or atomic load.
2394 /// It takes a chain node as input and returns the chain for the load itself.
2396 /// Having a callback like this is necessary for targets like SystemZ,
2397 /// which allows a CPU to reuse the result of a previous load indefinitely,
2398 /// even if a cache-coherent store is performed by another CPU. The default
2399 /// implementation does nothing.
2400 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2401 SelectionDAG &DAG) const {
2405 /// This callback is invoked by the type legalizer to legalize nodes with an
2406 /// illegal operand type but legal result types. It replaces the
2407 /// LowerOperation callback in the type Legalizer. The reason we can not do
2408 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2409 /// use this callback.
2411 /// TODO: Consider merging with ReplaceNodeResults.
2413 /// The target places new result values for the node in Results (their number
2414 /// and types must exactly match those of the original return values of
2415 /// the node), or leaves Results empty, which indicates that the node is not
2416 /// to be custom lowered after all.
2417 /// The default implementation calls LowerOperation.
2418 virtual void LowerOperationWrapper(SDNode *N,
2419 SmallVectorImpl<SDValue> &Results,
2420 SelectionDAG &DAG) const;
2422 /// This callback is invoked for operations that are unsupported by the
2423 /// target, which are registered to use 'custom' lowering, and whose defined
2424 /// values are all legal. If the target has no operations that require custom
2425 /// lowering, it need not implement this. The default implementation of this
2427 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2429 /// This callback is invoked when a node result type is illegal for the
2430 /// target, and the operation was registered to use 'custom' lowering for that
2431 /// result type. The target places new result values for the node in Results
2432 /// (their number and types must exactly match those of the original return
2433 /// values of the node), or leaves Results empty, which indicates that the
2434 /// node is not to be custom lowered after all.
2436 /// If the target has no operations that require custom lowering, it need not
2437 /// implement this. The default implementation aborts.
2438 virtual void ReplaceNodeResults(SDNode * /*N*/,
2439 SmallVectorImpl<SDValue> &/*Results*/,
2440 SelectionDAG &/*DAG*/) const {
2441 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2444 /// This method returns the name of a target specific DAG node.
2445 virtual const char *getTargetNodeName(unsigned Opcode) const;
2447 /// This method returns a target specific FastISel object, or null if the
2448 /// target does not support "fast" ISel.
2449 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2450 const TargetLibraryInfo *) const {
2455 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2456 SelectionDAG &DAG) const;
2458 //===--------------------------------------------------------------------===//
2459 // Inline Asm Support hooks
2462 /// This hook allows the target to expand an inline asm call to be explicit
2463 /// llvm code if it wants to. This is useful for turning simple inline asms
2464 /// into LLVM intrinsics, which gives the compiler more information about the
2465 /// behavior of the code.
2466 virtual bool ExpandInlineAsm(CallInst *) const {
2470 enum ConstraintType {
2471 C_Register, // Constraint represents specific register(s).
2472 C_RegisterClass, // Constraint represents any of register(s) in class.
2473 C_Memory, // Memory constraint.
2474 C_Other, // Something else.
2475 C_Unknown // Unsupported constraint.
2478 enum ConstraintWeight {
2480 CW_Invalid = -1, // No match.
2481 CW_Okay = 0, // Acceptable.
2482 CW_Good = 1, // Good weight.
2483 CW_Better = 2, // Better weight.
2484 CW_Best = 3, // Best weight.
2486 // Well-known weights.
2487 CW_SpecificReg = CW_Okay, // Specific register operands.
2488 CW_Register = CW_Good, // Register operands.
2489 CW_Memory = CW_Better, // Memory operands.
2490 CW_Constant = CW_Best, // Constant operand.
2491 CW_Default = CW_Okay // Default or don't know type.
2494 /// This contains information for each constraint that we are lowering.
2495 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2496 /// This contains the actual string for the code, like "m". TargetLowering
2497 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2498 /// matches the operand.
2499 std::string ConstraintCode;
2501 /// Information about the constraint code, e.g. Register, RegisterClass,
2502 /// Memory, Other, Unknown.
2503 TargetLowering::ConstraintType ConstraintType;
2505 /// If this is the result output operand or a clobber, this is null,
2506 /// otherwise it is the incoming operand to the CallInst. This gets
2507 /// modified as the asm is processed.
2508 Value *CallOperandVal;
2510 /// The ValueType for the operand value.
2513 /// Return true of this is an input operand that is a matching constraint
2515 bool isMatchingInputConstraint() const;
2517 /// If this is an input matching constraint, this method returns the output
2518 /// operand it matches.
2519 unsigned getMatchedOperand() const;
2521 /// Copy constructor for copying from a ConstraintInfo.
2522 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2523 : InlineAsm::ConstraintInfo(info),
2524 ConstraintType(TargetLowering::C_Unknown),
2525 CallOperandVal(nullptr), ConstraintVT(MVT::Other) {
2529 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2531 /// Split up the constraint string from the inline assembly value into the
2532 /// specific constraints and their prefixes, and also tie in the associated
2533 /// operand values. If this returns an empty vector, and if the constraint
2534 /// string itself isn't empty, there was an error parsing.
2535 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2537 /// Examine constraint type and operand type and determine a weight value.
2538 /// The operand object must already have been set up with the operand type.
2539 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2540 AsmOperandInfo &info, int maIndex) const;
2542 /// Examine constraint string and operand type and determine a weight value.
2543 /// The operand object must already have been set up with the operand type.
2544 virtual ConstraintWeight getSingleConstraintMatchWeight(
2545 AsmOperandInfo &info, const char *constraint) const;
2547 /// Determines the constraint code and constraint type to use for the specific
2548 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2549 /// If the actual operand being passed in is available, it can be passed in as
2550 /// Op, otherwise an empty SDValue can be passed.
2551 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2553 SelectionDAG *DAG = nullptr) const;
2555 /// Given a constraint, return the type of constraint it is for this target.
2556 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2558 /// Given a physical register constraint (e.g. {edx}), return the register
2559 /// number and the register class for the register.
2561 /// Given a register class constraint, like 'r', if this corresponds directly
2562 /// to an LLVM register class, return a register of 0 and the register class
2565 /// This should only be used for C_Register constraints. On error, this
2566 /// returns a register number of 0 and a null register class pointer..
2567 virtual std::pair<unsigned, const TargetRegisterClass*>
2568 getRegForInlineAsmConstraint(const std::string &Constraint,
2571 /// Try to replace an X constraint, which matches anything, with another that
2572 /// has more specific requirements based on the type of the corresponding
2573 /// operand. This returns null if there is no replacement to make.
2574 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2576 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2577 /// add anything to Ops.
2578 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2579 std::vector<SDValue> &Ops,
2580 SelectionDAG &DAG) const;
2582 //===--------------------------------------------------------------------===//
2583 // Div utility functions
2585 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2586 SelectionDAG &DAG) const;
2587 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2588 bool IsAfterLegalization,
2589 std::vector<SDNode *> *Created) const;
2590 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2591 bool IsAfterLegalization,
2592 std::vector<SDNode *> *Created) const;
2593 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2595 std::vector<SDNode *> *Created) const {
2599 //===--------------------------------------------------------------------===//
2600 // Legalization utility functions
2603 /// Expand a MUL into two nodes. One that computes the high bits of
2604 /// the result and one that computes the low bits.
2605 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2606 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2607 /// if you want to control how low bits are extracted from the LHS.
2608 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2609 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2610 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2611 /// \returns true if the node has been expanded. false if it has not
2612 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2613 SelectionDAG &DAG, SDValue LL = SDValue(),
2614 SDValue LH = SDValue(), SDValue RL = SDValue(),
2615 SDValue RH = SDValue()) const;
2617 /// Expand float(f32) to SINT(i64) conversion
2618 /// \param N Node to expand
2619 /// \param Result output after conversion
2620 /// \returns True, if the expansion was successful, false otherwise
2621 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2623 //===--------------------------------------------------------------------===//
2624 // Instruction Emitting Hooks
2627 /// This method should be implemented by targets that mark instructions with
2628 /// the 'usesCustomInserter' flag. These instructions are special in various
2629 /// ways, which require special support to insert. The specified MachineInstr
2630 /// is created but not inserted into any basic blocks, and this method is
2631 /// called to expand it into a sequence of instructions, potentially also
2632 /// creating new basic blocks and control flow.
2633 virtual MachineBasicBlock *
2634 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2636 /// This method should be implemented by targets that mark instructions with
2637 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2638 /// instruction selection by target hooks. e.g. To fill in optional defs for
2639 /// ARM 's' setting instructions.
2641 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2643 /// If this function returns true, SelectionDAGBuilder emits a
2644 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2645 virtual bool useLoadStackGuardNode() const {
2650 /// Given an LLVM IR type and return type attributes, compute the return value
2651 /// EVTs and flags, and optionally also the offsets, if the return value is
2652 /// being lowered to memory.
2653 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2654 SmallVectorImpl<ISD::OutputArg> &Outs,
2655 const TargetLowering &TLI);
2657 } // end llvm namespace