1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Constants.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/STLExtras.h"
39 class TargetRegisterClass;
43 class MachineBasicBlock;
46 class TargetSubtarget;
48 //===----------------------------------------------------------------------===//
49 /// TargetLowering - This class defines information used to lower LLVM code to
50 /// legal SelectionDAG operators that the target instruction selector can accept
53 /// This class also defines callbacks that targets must implement to lower
54 /// target-specific constructs to SelectionDAG operators.
56 class TargetLowering {
58 /// LegalizeAction - This enum indicates whether operations are valid for a
59 /// target, and if not, what action should be used to make them valid.
61 Legal, // The target natively supports this operation.
62 Promote, // This operation should be executed in a larger type.
63 Expand, // Try to expand this to other ops, otherwise use a libcall.
64 Custom // Use the LowerOperation hook to implement custom lowering.
67 enum OutOfRangeShiftAmount {
68 Undefined, // Oversized shift amounts are undefined (default).
69 Mask, // Shift amounts are auto masked (anded) to value size.
70 Extend // Oversized shift pulls in zeros or sign bits.
73 enum SetCCResultValue {
74 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
75 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
76 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
79 enum SchedPreference {
80 SchedulingForLatency, // Scheduling for shortest total latency.
81 SchedulingForRegPressure // Scheduling for lowest register pressure.
84 explicit TargetLowering(TargetMachine &TM);
85 virtual ~TargetLowering();
87 TargetMachine &getTargetMachine() const { return TM; }
88 const TargetData *getTargetData() const { return TD; }
90 bool isBigEndian() const { return !IsLittleEndian; }
91 bool isLittleEndian() const { return IsLittleEndian; }
92 MVT::ValueType getPointerTy() const { return PointerTy; }
93 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
94 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
96 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
98 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
100 /// isSelectExpensive - Return true if the select operation is expensive for
102 bool isSelectExpensive() const { return SelectIsExpensive; }
104 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
105 /// a sequence of several shifts, adds, and multiplies for this target.
106 bool isIntDivCheap() const { return IntDivIsCheap; }
108 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
110 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
112 /// getSetCCResultType - Return the ValueType of the result of setcc operations.
113 virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
115 /// getSetCCResultContents - For targets without boolean registers, this flag
116 /// returns information about the contents of the high-bits in the setcc
118 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
120 /// getSchedulingPreference - Return target scheduling preference.
121 SchedPreference getSchedulingPreference() const {
122 return SchedPreferenceInfo;
125 /// getRegClassFor - Return the register class that should be used for the
126 /// specified value type. This may only be called on legal types.
127 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
128 assert(VT < array_lengthof(RegClassForVT));
129 TargetRegisterClass *RC = RegClassForVT[VT];
130 assert(RC && "This value type is not natively supported!");
134 /// isTypeLegal - Return true if the target has native support for the
135 /// specified value type. This means that it has a register that directly
136 /// holds it without promotions or expansions.
137 bool isTypeLegal(MVT::ValueType VT) const {
138 assert(MVT::isExtendedVT(VT) || VT < array_lengthof(RegClassForVT));
139 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
142 class ValueTypeActionImpl {
143 /// ValueTypeActions - This is a bitvector that contains two bits for each
144 /// value type, where the two bits correspond to the LegalizeAction enum.
145 /// This can be queried with "getTypeAction(VT)".
146 uint32_t ValueTypeActions[2];
148 ValueTypeActionImpl() {
149 ValueTypeActions[0] = ValueTypeActions[1] = 0;
151 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
152 ValueTypeActions[0] = RHS.ValueTypeActions[0];
153 ValueTypeActions[1] = RHS.ValueTypeActions[1];
156 LegalizeAction getTypeAction(MVT::ValueType VT) const {
157 if (MVT::isExtendedVT(VT)) {
158 if (MVT::isVector(VT)) return Expand;
159 if (MVT::isInteger(VT))
160 // First promote to a power-of-two size, then expand if necessary.
161 return VT == MVT::RoundIntegerType(VT) ? Expand : Promote;
162 assert(0 && "Unsupported extended type!");
164 assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
165 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
167 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
168 assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
169 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
173 const ValueTypeActionImpl &getValueTypeActions() const {
174 return ValueTypeActions;
177 /// getTypeAction - Return how we should legalize values of this type, either
178 /// it is already legal (return 'Legal') or we need to promote it to a larger
179 /// type (return 'Promote'), or we need to expand it into multiple registers
180 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
181 LegalizeAction getTypeAction(MVT::ValueType VT) const {
182 return ValueTypeActions.getTypeAction(VT);
185 /// getTypeToTransformTo - For types supported by the target, this is an
186 /// identity function. For types that must be promoted to larger types, this
187 /// returns the larger type to promote to. For integer types that are larger
188 /// than the largest integer register, this contains one step in the expansion
189 /// to get to the smaller register. For illegal floating point types, this
190 /// returns the integer type to transform to.
191 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
192 if (!MVT::isExtendedVT(VT)) {
193 assert(VT < array_lengthof(TransformToType));
194 MVT::ValueType NVT = TransformToType[VT];
195 assert(getTypeAction(NVT) != Promote &&
196 "Promote may not follow Expand or Promote");
200 if (MVT::isVector(VT))
201 return MVT::getVectorType(MVT::getVectorElementType(VT),
202 MVT::getVectorNumElements(VT) / 2);
203 if (MVT::isInteger(VT)) {
204 MVT::ValueType NVT = MVT::RoundIntegerType(VT);
206 // Size is a power of two - expand to half the size.
207 return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2);
209 // Promote to a power of two size, avoiding multi-step promotion.
210 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
212 assert(0 && "Unsupported extended type!");
213 return MVT::ValueType(); // Not reached
216 /// getTypeToExpandTo - For types supported by the target, this is an
217 /// identity function. For types that must be expanded (i.e. integer types
218 /// that are larger than the largest integer register or illegal floating
219 /// point types), this returns the largest legal type it will be expanded to.
220 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
221 assert(!MVT::isVector(VT));
223 switch (getTypeAction(VT)) {
227 VT = getTypeToTransformTo(VT);
230 assert(false && "Type is not legal nor is it to be expanded!");
237 /// getVectorTypeBreakdown - Vector types are broken down into some number of
238 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
239 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
240 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
242 /// This method returns the number of registers needed, and the VT for each
243 /// register. It also returns the VT and quantity of the intermediate values
244 /// before they are promoted/expanded.
246 unsigned getVectorTypeBreakdown(MVT::ValueType VT,
247 MVT::ValueType &IntermediateVT,
248 unsigned &NumIntermediates,
249 MVT::ValueType &RegisterVT) const;
251 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
252 legal_fpimm_iterator legal_fpimm_begin() const {
253 return LegalFPImmediates.begin();
255 legal_fpimm_iterator legal_fpimm_end() const {
256 return LegalFPImmediates.end();
259 /// isShuffleMaskLegal - Targets can use this to indicate that they only
260 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
261 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
262 /// are assumed to be legal.
263 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
267 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
268 /// used by Targets can use this to indicate if there is a suitable
269 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
271 virtual bool isVectorClearMaskLegal(const std::vector<SDOperand> &BVOps,
273 SelectionDAG &DAG) const {
277 /// getOperationAction - Return how this operation should be treated: either
278 /// it is legal, needs to be promoted to a larger size, needs to be
279 /// expanded to some other code sequence, or the target has a custom expander
281 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
282 if (MVT::isExtendedVT(VT)) return Expand;
283 assert(Op < array_lengthof(OpActions) &&
284 VT < sizeof(OpActions[0])*4 && "Table isn't big enough!");
285 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
288 /// isOperationLegal - Return true if the specified operation is legal on this
290 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
291 return getOperationAction(Op, VT) == Legal ||
292 getOperationAction(Op, VT) == Custom;
295 /// getLoadXAction - Return how this load with extension should be treated:
296 /// either it is legal, needs to be promoted to a larger size, needs to be
297 /// expanded to some other code sequence, or the target has a custom expander
299 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
300 assert(LType < array_lengthof(LoadXActions) &&
301 VT < sizeof(LoadXActions[0])*4 && "Table isn't big enough!");
302 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
305 /// isLoadXLegal - Return true if the specified load with extension is legal
307 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
308 return !MVT::isExtendedVT(VT) &&
309 (getLoadXAction(LType, VT) == Legal ||
310 getLoadXAction(LType, VT) == Custom);
313 /// getTruncStoreAction - Return how this store with truncation should be
314 /// treated: either it is legal, needs to be promoted to a larger size, needs
315 /// to be expanded to some other code sequence, or the target has a custom
317 LegalizeAction getTruncStoreAction(MVT::ValueType ValVT,
318 MVT::ValueType MemVT) const {
319 assert(ValVT < array_lengthof(TruncStoreActions) &&
320 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!");
321 return (LegalizeAction)((TruncStoreActions[ValVT] >> (2*MemVT)) & 3);
324 /// isTruncStoreLegal - Return true if the specified store with truncation is
325 /// legal on this target.
326 bool isTruncStoreLegal(MVT::ValueType ValVT, MVT::ValueType MemVT) const {
327 return !MVT::isExtendedVT(MemVT) &&
328 (getTruncStoreAction(ValVT, MemVT) == Legal ||
329 getTruncStoreAction(ValVT, MemVT) == Custom);
332 /// getIndexedLoadAction - Return how the indexed load should be treated:
333 /// either it is legal, needs to be promoted to a larger size, needs to be
334 /// expanded to some other code sequence, or the target has a custom expander
337 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
338 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
339 VT < sizeof(IndexedModeActions[0][0])*4 &&
340 "Table isn't big enough!");
341 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
344 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
346 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
347 return getIndexedLoadAction(IdxMode, VT) == Legal ||
348 getIndexedLoadAction(IdxMode, VT) == Custom;
351 /// getIndexedStoreAction - Return how the indexed store should be treated:
352 /// either it is legal, needs to be promoted to a larger size, needs to be
353 /// expanded to some other code sequence, or the target has a custom expander
356 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
357 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
358 VT < sizeof(IndexedModeActions[1][0])*4 &&
359 "Table isn't big enough!");
360 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
363 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
365 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
366 return getIndexedStoreAction(IdxMode, VT) == Legal ||
367 getIndexedStoreAction(IdxMode, VT) == Custom;
370 /// getConvertAction - Return how the conversion should be treated:
371 /// either it is legal, needs to be promoted to a larger size, needs to be
372 /// expanded to some other code sequence, or the target has a custom expander
375 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
376 assert(FromVT < array_lengthof(ConvertActions) &&
377 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!");
378 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3);
381 /// isConvertLegal - Return true if the specified conversion is legal
383 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
384 return getConvertAction(FromVT, ToVT) == Legal ||
385 getConvertAction(FromVT, ToVT) == Custom;
388 /// getTypeToPromoteTo - If the action for this operation is to promote, this
389 /// method returns the ValueType to promote to.
390 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
391 assert(getOperationAction(Op, VT) == Promote &&
392 "This operation isn't promoted!");
394 // See if this has an explicit type specified.
395 std::map<std::pair<unsigned, MVT::ValueType>,
396 MVT::ValueType>::const_iterator PTTI =
397 PromoteToType.find(std::make_pair(Op, VT));
398 if (PTTI != PromoteToType.end()) return PTTI->second;
400 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
401 "Cannot autopromote this type, add it with AddPromotedToType.");
403 MVT::ValueType NVT = VT;
405 NVT = (MVT::ValueType)(NVT+1);
406 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
407 "Didn't find type to promote to!");
408 } while (!isTypeLegal(NVT) ||
409 getOperationAction(Op, NVT) == Promote);
413 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
414 /// This is fixed by the LLVM operations except for the pointer size. If
415 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
416 /// counterpart (e.g. structs), otherwise it will assert.
417 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
418 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
419 return VT == MVT::iPTR ? PointerTy : VT;
422 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
423 /// function arguments in the caller parameter area. This is the actual
424 /// alignment, not its logarithm.
425 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
427 /// getRegisterType - Return the type of registers that this ValueType will
428 /// eventually require.
429 MVT::ValueType getRegisterType(MVT::ValueType VT) const {
430 if (!MVT::isExtendedVT(VT)) {
431 assert(VT < array_lengthof(RegisterTypeForVT));
432 return RegisterTypeForVT[VT];
434 if (MVT::isVector(VT)) {
435 MVT::ValueType VT1, RegisterVT;
436 unsigned NumIntermediates;
437 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
440 if (MVT::isInteger(VT)) {
441 return getRegisterType(getTypeToTransformTo(VT));
443 assert(0 && "Unsupported extended type!");
444 return MVT::ValueType(); // Not reached
447 /// getNumRegisters - Return the number of registers that this ValueType will
448 /// eventually require. This is one for any types promoted to live in larger
449 /// registers, but may be more than one for types (like i64) that are split
450 /// into pieces. For types like i140, which are first promoted then expanded,
451 /// it is the number of registers needed to hold all the bits of the original
452 /// type. For an i140 on a 32 bit machine this means 5 registers.
453 unsigned getNumRegisters(MVT::ValueType VT) const {
454 if (!MVT::isExtendedVT(VT)) {
455 assert(VT < array_lengthof(NumRegistersForVT));
456 return NumRegistersForVT[VT];
458 if (MVT::isVector(VT)) {
459 MVT::ValueType VT1, VT2;
460 unsigned NumIntermediates;
461 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
463 if (MVT::isInteger(VT)) {
464 unsigned BitWidth = MVT::getSizeInBits(VT);
465 unsigned RegWidth = MVT::getSizeInBits(getRegisterType(VT));
466 return (BitWidth + RegWidth - 1) / RegWidth;
468 assert(0 && "Unsupported extended type!");
469 return 0; // Not reached
472 /// ShouldShrinkFPConstant - If true, then instruction selection should
473 /// seek to shrink the FP constant of the specified type to a smaller type
474 /// in order to save space and / or reduce runtime.
475 virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const { return true; }
477 /// hasTargetDAGCombine - If true, the target has custom DAG combine
478 /// transformations that it can perform for the specified node.
479 bool hasTargetDAGCombine(ISD::NodeType NT) const {
480 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
481 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
484 /// This function returns the maximum number of store operations permitted
485 /// to replace a call to llvm.memset. The value is set by the target at the
486 /// performance threshold for such a replacement.
487 /// @brief Get maximum # of store operations permitted for llvm.memset
488 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
490 /// This function returns the maximum number of store operations permitted
491 /// to replace a call to llvm.memcpy. The value is set by the target at the
492 /// performance threshold for such a replacement.
493 /// @brief Get maximum # of store operations permitted for llvm.memcpy
494 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
496 /// This function returns the maximum number of store operations permitted
497 /// to replace a call to llvm.memmove. The value is set by the target at the
498 /// performance threshold for such a replacement.
499 /// @brief Get maximum # of store operations permitted for llvm.memmove
500 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
502 /// This function returns true if the target allows unaligned memory accesses.
503 /// This is used, for example, in situations where an array copy/move/set is
504 /// converted to a sequence of store operations. It's use helps to ensure that
505 /// such replacements don't generate code that causes an alignment error
506 /// (trap) on the target machine.
507 /// @brief Determine if the target supports unaligned memory accesses.
508 bool allowsUnalignedMemoryAccesses() const {
509 return allowUnalignedMemoryAccesses;
512 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
513 /// to implement llvm.setjmp.
514 bool usesUnderscoreSetJmp() const {
515 return UseUnderscoreSetJmp;
518 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
519 /// to implement llvm.longjmp.
520 bool usesUnderscoreLongJmp() const {
521 return UseUnderscoreLongJmp;
524 /// getStackPointerRegisterToSaveRestore - If a physical register, this
525 /// specifies the register that llvm.savestack/llvm.restorestack should save
527 unsigned getStackPointerRegisterToSaveRestore() const {
528 return StackPointerRegisterToSaveRestore;
531 /// getExceptionAddressRegister - If a physical register, this returns
532 /// the register that receives the exception address on entry to a landing
534 unsigned getExceptionAddressRegister() const {
535 return ExceptionPointerRegister;
538 /// getExceptionSelectorRegister - If a physical register, this returns
539 /// the register that receives the exception typeid on entry to a landing
541 unsigned getExceptionSelectorRegister() const {
542 return ExceptionSelectorRegister;
545 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
546 /// set, the default is 200)
547 unsigned getJumpBufSize() const {
551 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
552 /// (if never set, the default is 0)
553 unsigned getJumpBufAlignment() const {
554 return JumpBufAlignment;
557 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
558 /// limit. Any block whose size is greater should not be predicated.
559 unsigned getIfCvtBlockSizeLimit() const {
560 return IfCvtBlockSizeLimit;
563 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
564 /// block to be considered for duplication. Any block whose size is greater
565 /// should not be duplicated to facilitate its predication.
566 unsigned getIfCvtDupBlockSizeLimit() const {
567 return IfCvtDupBlockSizeLimit;
570 /// getPrefLoopAlignment - return the preferred loop alignment.
572 unsigned getPrefLoopAlignment() const {
573 return PrefLoopAlignment;
576 /// getPreIndexedAddressParts - returns true by value, base pointer and
577 /// offset pointer and addressing mode by reference if the node's address
578 /// can be legally represented as pre-indexed load / store address.
579 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
581 ISD::MemIndexedMode &AM,
586 /// getPostIndexedAddressParts - returns true by value, base pointer and
587 /// offset pointer and addressing mode by reference if this node can be
588 /// combined with a load / store to form a post-indexed load / store.
589 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
590 SDOperand &Base, SDOperand &Offset,
591 ISD::MemIndexedMode &AM,
596 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
598 virtual SDOperand getPICJumpTableRelocBase(SDOperand Table,
599 SelectionDAG &DAG) const;
601 //===--------------------------------------------------------------------===//
602 // TargetLowering Optimization Methods
605 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
606 /// SDOperands for returning information from TargetLowering to its clients
607 /// that want to combine
608 struct TargetLoweringOpt {
614 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool afterLegalize)
615 : DAG(InDAG), AfterLegalize(afterLegalize) {}
617 bool CombineTo(SDOperand O, SDOperand N) {
623 /// ShrinkDemandedConstant - Check to see if the specified operand of the
624 /// specified instruction is a constant integer. If so, check to see if
625 /// there are any bits set in the constant that are not demanded. If so,
626 /// shrink the constant and return true.
627 bool ShrinkDemandedConstant(SDOperand Op, const APInt &Demanded);
630 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
631 /// DemandedMask bits of the result of Op are ever used downstream. If we can
632 /// use this information to simplify Op, create a new simplified DAG node and
633 /// return true, returning the original and new nodes in Old and New.
634 /// Otherwise, analyze the expression and return a mask of KnownOne and
635 /// KnownZero bits for the expression (used to simplify the caller).
636 /// The KnownZero/One bits may only be accurate for those bits in the
638 bool SimplifyDemandedBits(SDOperand Op, const APInt &DemandedMask,
639 APInt &KnownZero, APInt &KnownOne,
640 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
642 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
643 /// Mask are known to be either zero or one and return them in the
644 /// KnownZero/KnownOne bitsets.
645 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
649 const SelectionDAG &DAG,
650 unsigned Depth = 0) const;
652 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
653 /// targets that want to expose additional information about sign bits to the
655 virtual unsigned ComputeNumSignBitsForTargetNode(SDOperand Op,
656 unsigned Depth = 0) const;
658 struct DAGCombinerInfo {
659 void *DC; // The DAG Combiner object.
661 bool CalledByLegalizer;
665 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
666 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
668 bool isBeforeLegalize() const { return BeforeLegalize; }
669 bool isCalledByLegalizer() const { return CalledByLegalizer; }
671 void AddToWorklist(SDNode *N);
672 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
673 SDOperand CombineTo(SDNode *N, SDOperand Res);
674 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
677 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
678 /// and cc. If it is unable to simplify it, return a null SDOperand.
679 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
680 ISD::CondCode Cond, bool foldBooleans,
681 DAGCombinerInfo &DCI) const;
683 /// PerformDAGCombine - This method will be invoked for all target nodes and
684 /// for any target-independent nodes that the target has registered with
687 /// The semantics are as follows:
689 /// SDOperand.Val == 0 - No change was made
690 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
691 /// otherwise - N should be replaced by the returned Operand.
693 /// In addition, methods provided by DAGCombinerInfo may be used to perform
694 /// more complex transformations.
696 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
698 //===--------------------------------------------------------------------===//
699 // TargetLowering Configuration Methods - These methods should be invoked by
700 // the derived class constructor to configure this object for the target.
704 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
705 /// GOT for PC-relative code.
706 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
708 /// setShiftAmountType - Describe the type that should be used for shift
709 /// amounts. This type defaults to the pointer type.
710 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
712 /// setSetCCResultContents - Specify how the target extends the result of a
713 /// setcc operation in a register.
714 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
716 /// setSchedulingPreference - Specify the target scheduling preference.
717 void setSchedulingPreference(SchedPreference Pref) {
718 SchedPreferenceInfo = Pref;
721 /// setShiftAmountFlavor - Describe how the target handles out of range shift
723 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
724 ShiftAmtHandling = OORSA;
727 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
728 /// use _setjmp to implement llvm.setjmp or the non _ version.
729 /// Defaults to false.
730 void setUseUnderscoreSetJmp(bool Val) {
731 UseUnderscoreSetJmp = Val;
734 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
735 /// use _longjmp to implement llvm.longjmp or the non _ version.
736 /// Defaults to false.
737 void setUseUnderscoreLongJmp(bool Val) {
738 UseUnderscoreLongJmp = Val;
741 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
742 /// specifies the register that llvm.savestack/llvm.restorestack should save
744 void setStackPointerRegisterToSaveRestore(unsigned R) {
745 StackPointerRegisterToSaveRestore = R;
748 /// setExceptionPointerRegister - If set to a physical register, this sets
749 /// the register that receives the exception address on entry to a landing
751 void setExceptionPointerRegister(unsigned R) {
752 ExceptionPointerRegister = R;
755 /// setExceptionSelectorRegister - If set to a physical register, this sets
756 /// the register that receives the exception typeid on entry to a landing
758 void setExceptionSelectorRegister(unsigned R) {
759 ExceptionSelectorRegister = R;
762 /// SelectIsExpensive - Tells the code generator not to expand operations
763 /// into sequences that use the select operations if possible.
764 void setSelectIsExpensive() { SelectIsExpensive = true; }
766 /// setIntDivIsCheap - Tells the code generator that integer divide is
767 /// expensive, and if possible, should be replaced by an alternate sequence
768 /// of instructions not containing an integer divide.
769 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
771 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
772 /// srl/add/sra for a signed divide by power of two, and let the target handle
774 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
776 /// addRegisterClass - Add the specified register class as an available
777 /// regclass for the specified value type. This indicates the selector can
778 /// handle values of that class natively.
779 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
780 assert(VT < array_lengthof(RegClassForVT));
781 AvailableRegClasses.push_back(std::make_pair(VT, RC));
782 RegClassForVT[VT] = RC;
785 /// computeRegisterProperties - Once all of the register classes are added,
786 /// this allows us to compute derived properties we expose.
787 void computeRegisterProperties();
789 /// setOperationAction - Indicate that the specified operation does not work
790 /// with the specified type and indicate what to do about it.
791 void setOperationAction(unsigned Op, MVT::ValueType VT,
792 LegalizeAction Action) {
793 assert(VT < sizeof(OpActions[0])*4 && Op < array_lengthof(OpActions) &&
794 "Table isn't big enough!");
795 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
796 OpActions[Op] |= (uint64_t)Action << VT*2;
799 /// setLoadXAction - Indicate that the specified load with extension does not
800 /// work with the with specified type and indicate what to do about it.
801 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
802 LegalizeAction Action) {
803 assert(VT < sizeof(LoadXActions[0])*4 &&
804 ExtType < array_lengthof(LoadXActions) &&
805 "Table isn't big enough!");
806 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
807 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
810 /// setTruncStoreAction - Indicate that the specified truncating store does
811 /// not work with the with specified type and indicate what to do about it.
812 void setTruncStoreAction(MVT::ValueType ValVT, MVT::ValueType MemVT,
813 LegalizeAction Action) {
814 assert(ValVT < array_lengthof(TruncStoreActions) &&
815 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!");
816 TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2);
817 TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2;
820 /// setIndexedLoadAction - Indicate that the specified indexed load does or
821 /// does not work with the with specified type and indicate what to do abort
822 /// it. NOTE: All indexed mode loads are initialized to Expand in
823 /// TargetLowering.cpp
824 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
825 LegalizeAction Action) {
826 assert(VT < sizeof(IndexedModeActions[0])*4 && IdxMode <
827 array_lengthof(IndexedModeActions[0]) &&
828 "Table isn't big enough!");
829 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
830 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
833 /// setIndexedStoreAction - Indicate that the specified indexed store does or
834 /// does not work with the with specified type and indicate what to do about
835 /// it. NOTE: All indexed mode stores are initialized to Expand in
836 /// TargetLowering.cpp
837 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
838 LegalizeAction Action) {
839 assert(VT < sizeof(IndexedModeActions[1][0])*4 &&
840 IdxMode < array_lengthof(IndexedModeActions[1]) &&
841 "Table isn't big enough!");
842 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
843 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
846 /// setConvertAction - Indicate that the specified conversion does or does
847 /// not work with the with specified type and indicate what to do about it.
848 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT,
849 LegalizeAction Action) {
850 assert(FromVT < array_lengthof(ConvertActions) &&
851 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!");
852 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
853 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
856 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
857 /// promotion code defaults to trying a larger integer/fp until it can find
858 /// one that works. If that default is insufficient, this method can be used
859 /// by the target to override the default.
860 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
861 MVT::ValueType DestVT) {
862 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
865 /// addLegalFPImmediate - Indicate that this target can instruction select
866 /// the specified FP immediate natively.
867 void addLegalFPImmediate(const APFloat& Imm) {
868 LegalFPImmediates.push_back(Imm);
871 /// setTargetDAGCombine - Targets should invoke this method for each target
872 /// independent node that they want to provide a custom DAG combiner for by
873 /// implementing the PerformDAGCombine virtual method.
874 void setTargetDAGCombine(ISD::NodeType NT) {
875 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
876 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
879 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
880 /// bytes); default is 200
881 void setJumpBufSize(unsigned Size) {
885 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
886 /// alignment (in bytes); default is 0
887 void setJumpBufAlignment(unsigned Align) {
888 JumpBufAlignment = Align;
891 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
892 /// limit (in number of instructions); default is 2.
893 void setIfCvtBlockSizeLimit(unsigned Limit) {
894 IfCvtBlockSizeLimit = Limit;
897 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
898 /// of instructions) to be considered for code duplication during
899 /// if-conversion; default is 2.
900 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
901 IfCvtDupBlockSizeLimit = Limit;
904 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
905 /// alignment is zero, it means the target does not care about loop alignment.
906 void setPrefLoopAlignment(unsigned Align) {
907 PrefLoopAlignment = Align;
912 virtual const TargetSubtarget *getSubtarget() {
913 assert(0 && "Not Implemented");
914 return NULL; // this is here to silence compiler errors
916 //===--------------------------------------------------------------------===//
917 // Lowering methods - These methods must be implemented by targets so that
918 // the SelectionDAGLowering code knows how to lower these.
921 /// LowerArguments - This hook must be implemented to indicate how we should
922 /// lower the arguments for the specified function, into the specified DAG.
923 virtual std::vector<SDOperand>
924 LowerArguments(Function &F, SelectionDAG &DAG);
926 /// LowerCallTo - This hook lowers an abstract call to a function into an
927 /// actual call. This returns a pair of operands. The first element is the
928 /// return value for the function (if RetTy is not VoidTy). The second
929 /// element is the outgoing token chain.
930 struct ArgListEntry {
941 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
942 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
944 typedef std::vector<ArgListEntry> ArgListTy;
945 virtual std::pair<SDOperand, SDOperand>
946 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
947 bool isVarArg, unsigned CallingConv, bool isTailCall,
948 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
951 virtual SDOperand LowerMEMCPY(SDOperand Op, SelectionDAG &DAG);
952 virtual SDOperand LowerMEMCPYCall(SDOperand Chain, SDOperand Dest,
953 SDOperand Source, SDOperand Count,
955 virtual SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest,
956 SDOperand Source, unsigned Size,
957 unsigned Align, SelectionDAG &DAG) {
958 assert(0 && "Not Implemented");
959 return SDOperand(); // this is here to silence compiler errors
963 /// LowerOperation - This callback is invoked for operations that are
964 /// unsupported by the target, which are registered to use 'custom' lowering,
965 /// and whose defined values are all legal.
966 /// If the target has no operations that require custom lowering, it need not
967 /// implement this. The default implementation of this aborts.
968 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
970 /// ExpandOperationResult - This callback is invoked for operations that are
971 /// unsupported by the target, which are registered to use 'custom' lowering,
972 /// and whose result type needs to be expanded. This must return a node whose
973 /// results precisely match the results of the input node. This typically
974 /// involves a MERGE_VALUES node and/or BUILD_PAIR.
976 /// If the target has no operations that require custom lowering, it need not
977 /// implement this. The default implementation of this aborts.
978 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
979 assert(0 && "ExpandOperationResult not implemented for this target!");
983 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
984 /// tail call optimization. Targets which want to do tail call optimization
985 /// should override this function.
986 virtual bool IsEligibleForTailCallOptimization(SDOperand Call,
988 SelectionDAG &DAG) const {
992 /// CustomPromoteOperation - This callback is invoked for operations that are
993 /// unsupported by the target, are registered to use 'custom' lowering, and
994 /// whose type needs to be promoted.
995 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
997 /// getTargetNodeName() - This method returns the name of a target specific
999 virtual const char *getTargetNodeName(unsigned Opcode) const;
1001 //===--------------------------------------------------------------------===//
1002 // Inline Asm Support hooks
1005 enum ConstraintType {
1006 C_Register, // Constraint represents a single register.
1007 C_RegisterClass, // Constraint represents one or more registers.
1008 C_Memory, // Memory constraint.
1009 C_Other, // Something else.
1010 C_Unknown // Unsupported constraint.
1013 /// AsmOperandInfo - This contains information for each constraint that we are
1015 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1016 /// ConstraintCode - This contains the actual string for the code, like "m".
1017 std::string ConstraintCode;
1019 /// ConstraintType - Information about the constraint code, e.g. Register,
1020 /// RegisterClass, Memory, Other, Unknown.
1021 TargetLowering::ConstraintType ConstraintType;
1023 /// CallOperandval - If this is the result output operand or a
1024 /// clobber, this is null, otherwise it is the incoming operand to the
1025 /// CallInst. This gets modified as the asm is processed.
1026 Value *CallOperandVal;
1028 /// ConstraintVT - The ValueType for the operand value.
1029 MVT::ValueType ConstraintVT;
1031 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1032 : InlineAsm::ConstraintInfo(info),
1033 ConstraintType(TargetLowering::C_Unknown),
1034 CallOperandVal(0), ConstraintVT(MVT::Other) {
1037 /// getConstraintGenerality - Return an integer indicating how general CT is.
1038 unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
1040 default: assert(0 && "Unknown constraint type!");
1041 case TargetLowering::C_Other:
1042 case TargetLowering::C_Unknown:
1044 case TargetLowering::C_Register:
1046 case TargetLowering::C_RegisterClass:
1048 case TargetLowering::C_Memory:
1053 /// ComputeConstraintToUse - Determines the constraint code and constraint
1055 void ComputeConstraintToUse(const TargetLowering &TLI) {
1056 assert(!Codes.empty() && "Must have at least one constraint");
1058 std::string *Current = &Codes[0];
1059 TargetLowering::ConstraintType CurType = TLI.getConstraintType(*Current);
1060 if (Codes.size() == 1) { // Single-letter constraints ('r') are very common.
1061 ConstraintCode = *Current;
1062 ConstraintType = CurType;
1064 unsigned CurGenerality = getConstraintGenerality(CurType);
1066 // If we have multiple constraints, try to pick the most general one ahead
1067 // of time. This isn't a wonderful solution, but handles common cases.
1068 for (unsigned j = 1, e = Codes.size(); j != e; ++j) {
1069 TargetLowering::ConstraintType ThisType = TLI.getConstraintType(Codes[j]);
1070 unsigned ThisGenerality = getConstraintGenerality(ThisType);
1071 if (ThisGenerality > CurGenerality) {
1072 // This constraint letter is more general than the previous one,
1075 Current = &Codes[j];
1076 CurGenerality = ThisGenerality;
1080 ConstraintCode = *Current;
1081 ConstraintType = CurType;
1084 if (ConstraintCode == "X" && CallOperandVal) {
1085 if (isa<BasicBlock>(CallOperandVal) || isa<ConstantInt>(CallOperandVal))
1087 // This matches anything. Labels and constants we handle elsewhere
1088 // ('X' is the only thing that matches labels). Otherwise, try to
1089 // resolve it to something we know about by looking at the actual
1092 TLI.lowerXConstraint(ConstraintVT, s);
1095 ConstraintType = TLI.getConstraintType(ConstraintCode);
1101 /// getConstraintType - Given a constraint, return the type of constraint it
1102 /// is for this target.
1103 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1105 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1106 /// return a list of registers that can be used to satisfy the constraint.
1107 /// This should only be used for C_RegisterClass constraints.
1108 virtual std::vector<unsigned>
1109 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1110 MVT::ValueType VT) const;
1112 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1113 /// {edx}), return the register number and the register class for the
1116 /// Given a register class constraint, like 'r', if this corresponds directly
1117 /// to an LLVM register class, return a register of 0 and the register class
1120 /// This should only be used for C_Register constraints. On error,
1121 /// this returns a register number of 0 and a null register class pointer..
1122 virtual std::pair<unsigned, const TargetRegisterClass*>
1123 getRegForInlineAsmConstraint(const std::string &Constraint,
1124 MVT::ValueType VT) const;
1126 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1127 /// with another that has more specific requirements based on the type of the
1128 /// corresponding operand.
1129 virtual void lowerXConstraint(MVT::ValueType ConstraintVT,
1130 std::string&) const;
1132 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1133 /// vector. If it is invalid, don't add anything to Ops.
1134 virtual void LowerAsmOperandForConstraint(SDOperand Op, char ConstraintLetter,
1135 std::vector<SDOperand> &Ops,
1138 //===--------------------------------------------------------------------===//
1142 // EmitInstrWithCustomInserter - This method should be implemented by targets
1143 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1144 // instructions are special in various ways, which require special support to
1145 // insert. The specified MachineInstr is created but not inserted into any
1146 // basic blocks, and the scheduler passes ownership of it to this method.
1147 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1148 MachineBasicBlock *MBB);
1150 //===--------------------------------------------------------------------===//
1151 // Addressing mode description hooks (used by LSR etc).
1154 /// AddrMode - This represents an addressing mode of:
1155 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1156 /// If BaseGV is null, there is no BaseGV.
1157 /// If BaseOffs is zero, there is no base offset.
1158 /// If HasBaseReg is false, there is no base register.
1159 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1163 GlobalValue *BaseGV;
1167 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1170 /// isLegalAddressingMode - Return true if the addressing mode represented by
1171 /// AM is legal for this target, for a load/store of the specified type.
1172 /// TODO: Handle pre/postinc as well.
1173 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1175 /// isTruncateFree - Return true if it's free to truncate a value of
1176 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1177 /// register EAX to i16 by referencing its sub-register AX.
1178 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1182 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const {
1186 //===--------------------------------------------------------------------===//
1187 // Div utility functions
1189 SDOperand BuildSDIV(SDNode *N, SelectionDAG &DAG,
1190 std::vector<SDNode*>* Created) const;
1191 SDOperand BuildUDIV(SDNode *N, SelectionDAG &DAG,
1192 std::vector<SDNode*>* Created) const;
1195 //===--------------------------------------------------------------------===//
1196 // Runtime Library hooks
1199 /// setLibcallName - Rename the default libcall routine name for the specified
1201 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1202 LibcallRoutineNames[Call] = Name;
1205 /// getLibcallName - Get the libcall routine name for the specified libcall.
1207 const char *getLibcallName(RTLIB::Libcall Call) const {
1208 return LibcallRoutineNames[Call];
1211 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1212 /// result of the comparison libcall against zero.
1213 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1214 CmpLibcallCCs[Call] = CC;
1217 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1218 /// the comparison libcall against zero.
1219 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1220 return CmpLibcallCCs[Call];
1225 const TargetData *TD;
1227 /// IsLittleEndian - True if this is a little endian target.
1229 bool IsLittleEndian;
1231 /// PointerTy - The type to use for pointers, usually i32 or i64.
1233 MVT::ValueType PointerTy;
1235 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1237 bool UsesGlobalOffsetTable;
1239 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1241 MVT::ValueType ShiftAmountTy;
1243 OutOfRangeShiftAmount ShiftAmtHandling;
1245 /// SelectIsExpensive - Tells the code generator not to expand operations
1246 /// into sequences that use the select operations if possible.
1247 bool SelectIsExpensive;
1249 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1250 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1251 /// a real cost model is in place. If we ever optimize for size, this will be
1252 /// set to true unconditionally.
1255 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1256 /// srl/add/sra for a signed divide by power of two, and let the target handle
1258 bool Pow2DivIsCheap;
1260 /// SetCCResultContents - Information about the contents of the high-bits in
1261 /// the result of a setcc comparison operation.
1262 SetCCResultValue SetCCResultContents;
1264 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1265 /// total cycles or lowest register usage.
1266 SchedPreference SchedPreferenceInfo;
1268 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1269 /// llvm.setjmp. Defaults to false.
1270 bool UseUnderscoreSetJmp;
1272 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1273 /// llvm.longjmp. Defaults to false.
1274 bool UseUnderscoreLongJmp;
1276 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1277 unsigned JumpBufSize;
1279 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1281 unsigned JumpBufAlignment;
1283 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1285 unsigned IfCvtBlockSizeLimit;
1287 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1288 /// duplicated during if-conversion.
1289 unsigned IfCvtDupBlockSizeLimit;
1291 /// PrefLoopAlignment - The perferred loop alignment.
1293 unsigned PrefLoopAlignment;
1295 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1296 /// specifies the register that llvm.savestack/llvm.restorestack should save
1298 unsigned StackPointerRegisterToSaveRestore;
1300 /// ExceptionPointerRegister - If set to a physical register, this specifies
1301 /// the register that receives the exception address on entry to a landing
1303 unsigned ExceptionPointerRegister;
1305 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1306 /// the register that receives the exception typeid on entry to a landing
1308 unsigned ExceptionSelectorRegister;
1310 /// RegClassForVT - This indicates the default register class to use for
1311 /// each ValueType the target supports natively.
1312 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1313 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1314 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
1316 /// TransformToType - For any value types we are promoting or expanding, this
1317 /// contains the value type that we are changing to. For Expanded types, this
1318 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1319 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1320 /// by the system, this holds the same type (e.g. i32 -> i32).
1321 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1323 /// OpActions - For each operation and each value type, keep a LegalizeAction
1324 /// that indicates how instruction selection should deal with the operation.
1325 /// Most operations are Legal (aka, supported natively by the target), but
1326 /// operations that are not should be described. Note that operations on
1327 /// non-legal value types are not described here.
1328 uint64_t OpActions[156];
1330 /// LoadXActions - For each load of load extension type and each value type,
1331 /// keep a LegalizeAction that indicates how instruction selection should deal
1333 uint64_t LoadXActions[ISD::LAST_LOADX_TYPE];
1335 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1336 /// indicates how instruction selection should deal with the store.
1337 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1339 /// IndexedModeActions - For each indexed mode and each value type, keep a
1340 /// pair of LegalizeAction that indicates how instruction selection should
1341 /// deal with the load / store.
1342 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1344 /// ConvertActions - For each conversion from source type to destination type,
1345 /// keep a LegalizeAction that indicates how instruction selection should
1346 /// deal with the conversion.
1347 /// Currently, this is used only for floating->floating conversions
1348 /// (FP_EXTEND and FP_ROUND).
1349 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1351 ValueTypeActionImpl ValueTypeActions;
1353 std::vector<APFloat> LegalFPImmediates;
1355 std::vector<std::pair<MVT::ValueType,
1356 TargetRegisterClass*> > AvailableRegClasses;
1358 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1359 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1360 /// which sets a bit in this array.
1361 unsigned char TargetDAGCombineArray[160/(sizeof(unsigned char)*8)];
1363 /// PromoteToType - For operations that must be promoted to a specific type,
1364 /// this holds the destination type. This map should be sparse, so don't hold
1367 /// Targets add entries to this map with AddPromotedToType(..), clients access
1368 /// this with getTypeToPromoteTo(..).
1369 std::map<std::pair<unsigned, MVT::ValueType>, MVT::ValueType> PromoteToType;
1371 /// LibcallRoutineNames - Stores the name each libcall.
1373 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1375 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1376 /// of each of the comparison libcall against zero.
1377 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1380 /// When lowering %llvm.memset this field specifies the maximum number of
1381 /// store operations that may be substituted for the call to memset. Targets
1382 /// must set this value based on the cost threshold for that target. Targets
1383 /// should assume that the memset will be done using as many of the largest
1384 /// store operations first, followed by smaller ones, if necessary, per
1385 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1386 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1387 /// store. This only applies to setting a constant array of a constant size.
1388 /// @brief Specify maximum number of store instructions per memset call.
1389 unsigned maxStoresPerMemset;
1391 /// When lowering %llvm.memcpy this field specifies the maximum number of
1392 /// store operations that may be substituted for a call to memcpy. Targets
1393 /// must set this value based on the cost threshold for that target. Targets
1394 /// should assume that the memcpy will be done using as many of the largest
1395 /// store operations first, followed by smaller ones, if necessary, per
1396 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1397 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1398 /// and one 1-byte store. This only applies to copying a constant array of
1400 /// @brief Specify maximum bytes of store instructions per memcpy call.
1401 unsigned maxStoresPerMemcpy;
1403 /// When lowering %llvm.memmove this field specifies the maximum number of
1404 /// store instructions that may be substituted for a call to memmove. Targets
1405 /// must set this value based on the cost threshold for that target. Targets
1406 /// should assume that the memmove will be done using as many of the largest
1407 /// store operations first, followed by smaller ones, if necessary, per
1408 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1409 /// with 8-bit alignment would result in nine 1-byte stores. This only
1410 /// applies to copying a constant array of constant size.
1411 /// @brief Specify maximum bytes of store instructions per memmove call.
1412 unsigned maxStoresPerMemmove;
1414 /// This field specifies whether the target machine permits unaligned memory
1415 /// accesses. This is used, for example, to determine the size of store
1416 /// operations when copying small arrays and other similar tasks.
1417 /// @brief Indicate whether the target permits unaligned memory accesses.
1418 bool allowUnalignedMemoryAccesses;
1420 } // end llvm namespace