1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/InlineAsm.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/STLExtras.h"
41 class MachineBasicBlock;
42 class MachineFunction;
43 class MachineFrameInfo;
45 class MachineModuleInfo;
51 class TargetRegisterClass;
52 class TargetSubtarget;
55 //===----------------------------------------------------------------------===//
56 /// TargetLowering - This class defines information used to lower LLVM code to
57 /// legal SelectionDAG operators that the target instruction selector can accept
60 /// This class also defines callbacks that targets must implement to lower
61 /// target-specific constructs to SelectionDAG operators.
63 class TargetLowering {
65 /// LegalizeAction - This enum indicates whether operations are valid for a
66 /// target, and if not, what action should be used to make them valid.
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand, // Try to expand this to other ops, otherwise use a libcall.
71 Custom // Use the LowerOperation hook to implement custom lowering.
74 enum OutOfRangeShiftAmount {
75 Undefined, // Oversized shift amounts are undefined (default).
76 Mask, // Shift amounts are auto masked (anded) to value size.
77 Extend // Oversized shift pulls in zeros or sign bits.
80 enum BooleanContent { // How the target represents true/false values.
81 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
82 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
83 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
86 enum SchedPreference {
87 SchedulingForLatency, // Scheduling for shortest total latency.
88 SchedulingForRegPressure // Scheduling for lowest register pressure.
91 explicit TargetLowering(TargetMachine &TM);
92 virtual ~TargetLowering();
94 TargetMachine &getTargetMachine() const { return TM; }
95 const TargetData *getTargetData() const { return TD; }
97 bool isBigEndian() const { return !IsLittleEndian; }
98 bool isLittleEndian() const { return IsLittleEndian; }
99 MVT getPointerTy() const { return PointerTy; }
100 MVT getShiftAmountTy() const { return ShiftAmountTy; }
101 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
103 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
105 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
107 /// isSelectExpensive - Return true if the select operation is expensive for
109 bool isSelectExpensive() const { return SelectIsExpensive; }
111 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
112 /// a sequence of several shifts, adds, and multiplies for this target.
113 bool isIntDivCheap() const { return IntDivIsCheap; }
115 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
117 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
119 /// getSetCCResultType - Return the ValueType of the result of SETCC
120 /// operations. Also used to obtain the target's preferred type for
121 /// the condition operand of SELECT and BRCOND nodes. In the case of
122 /// BRCOND the argument passed is MVT::Other since there are no other
123 /// operands to get a type hint from.
124 virtual MVT getSetCCResultType(MVT VT) const;
126 /// getBooleanContents - For targets without i1 registers, this gives the
127 /// nature of the high-bits of boolean values held in types wider than i1.
128 /// "Boolean values" are special true/false values produced by nodes like
129 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
130 /// Not to be confused with general values promoted from i1.
131 BooleanContent getBooleanContents() const { return BooleanContents;}
133 /// getSchedulingPreference - Return target scheduling preference.
134 SchedPreference getSchedulingPreference() const {
135 return SchedPreferenceInfo;
138 /// getRegClassFor - Return the register class that should be used for the
139 /// specified value type. This may only be called on legal types.
140 TargetRegisterClass *getRegClassFor(MVT VT) const {
141 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
142 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
143 assert(RC && "This value type is not natively supported!");
147 /// isTypeLegal - Return true if the target has native support for the
148 /// specified value type. This means that it has a register that directly
149 /// holds it without promotions or expansions.
150 bool isTypeLegal(MVT VT) const {
151 assert(!VT.isSimple() ||
152 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
153 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
156 class ValueTypeActionImpl {
157 /// ValueTypeActions - This is a bitvector that contains two bits for each
158 /// value type, where the two bits correspond to the LegalizeAction enum.
159 /// This can be queried with "getTypeAction(VT)".
160 uint32_t ValueTypeActions[2];
162 ValueTypeActionImpl() {
163 ValueTypeActions[0] = ValueTypeActions[1] = 0;
165 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
166 ValueTypeActions[0] = RHS.ValueTypeActions[0];
167 ValueTypeActions[1] = RHS.ValueTypeActions[1];
170 LegalizeAction getTypeAction(MVT VT) const {
171 if (VT.isExtended()) {
173 return VT.isPow2VectorType() ? Expand : Promote;
176 // First promote to a power-of-two size, then expand if necessary.
177 return VT == VT.getRoundIntegerType() ? Expand : Promote;
178 assert(0 && "Unsupported extended type!");
181 unsigned I = VT.getSimpleVT();
182 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
183 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
185 void setTypeAction(MVT VT, LegalizeAction Action) {
186 unsigned I = VT.getSimpleVT();
187 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
188 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
192 const ValueTypeActionImpl &getValueTypeActions() const {
193 return ValueTypeActions;
196 /// getTypeAction - Return how we should legalize values of this type, either
197 /// it is already legal (return 'Legal') or we need to promote it to a larger
198 /// type (return 'Promote'), or we need to expand it into multiple registers
199 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
200 LegalizeAction getTypeAction(MVT VT) const {
201 return ValueTypeActions.getTypeAction(VT);
204 /// getTypeToTransformTo - For types supported by the target, this is an
205 /// identity function. For types that must be promoted to larger types, this
206 /// returns the larger type to promote to. For integer types that are larger
207 /// than the largest integer register, this contains one step in the expansion
208 /// to get to the smaller register. For illegal floating point types, this
209 /// returns the integer type to transform to.
210 MVT getTypeToTransformTo(MVT VT) const {
212 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
213 MVT NVT = TransformToType[VT.getSimpleVT()];
214 assert(getTypeAction(NVT) != Promote &&
215 "Promote may not follow Expand or Promote");
220 MVT NVT = VT.getPow2VectorType();
222 // Vector length is a power of 2 - split to half the size.
223 unsigned NumElts = VT.getVectorNumElements();
224 MVT EltVT = VT.getVectorElementType();
225 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
227 // Promote to a power of two size, avoiding multi-step promotion.
228 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
229 } else if (VT.isInteger()) {
230 MVT NVT = VT.getRoundIntegerType();
232 // Size is a power of two - expand to half the size.
233 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
235 // Promote to a power of two size, avoiding multi-step promotion.
236 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
238 assert(0 && "Unsupported extended type!");
239 return MVT(); // Not reached
242 /// getTypeToExpandTo - For types supported by the target, this is an
243 /// identity function. For types that must be expanded (i.e. integer types
244 /// that are larger than the largest integer register or illegal floating
245 /// point types), this returns the largest legal type it will be expanded to.
246 MVT getTypeToExpandTo(MVT VT) const {
247 assert(!VT.isVector());
249 switch (getTypeAction(VT)) {
253 VT = getTypeToTransformTo(VT);
256 assert(false && "Type is not legal nor is it to be expanded!");
263 /// getVectorTypeBreakdown - Vector types are broken down into some number of
264 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
265 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
266 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
268 /// This method returns the number of registers needed, and the VT for each
269 /// register. It also returns the VT and quantity of the intermediate values
270 /// before they are promoted/expanded.
272 unsigned getVectorTypeBreakdown(MVT VT,
274 unsigned &NumIntermediates,
275 MVT &RegisterVT) const;
277 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
278 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
279 /// this is the case, it returns true and store the intrinsic
280 /// information into the IntrinsicInfo that was passed to the function.
281 typedef struct IntrinsicInfo {
282 unsigned opc; // target opcode
283 MVT memVT; // memory VT
284 const Value* ptrVal; // value representing memory location
285 int offset; // offset off of ptrVal
286 unsigned align; // alignment
287 bool vol; // is volatile?
288 bool readMem; // reads memory?
289 bool writeMem; // writes memory?
292 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
293 CallInst &I, unsigned Intrinsic) {
297 /// getWidenVectorType: given a vector type, returns the type to widen to
298 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
299 /// If there is no vector type that we want to widen to, returns MVT::Other
300 /// When and were to widen is target dependent based on the cost of
301 /// scalarizing vs using the wider vector type.
302 virtual MVT getWidenVectorType(MVT VT);
304 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
305 legal_fpimm_iterator legal_fpimm_begin() const {
306 return LegalFPImmediates.begin();
308 legal_fpimm_iterator legal_fpimm_end() const {
309 return LegalFPImmediates.end();
312 /// isShuffleMaskLegal - Targets can use this to indicate that they only
313 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
314 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
315 /// are assumed to be legal.
316 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
320 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
321 /// used by Targets can use this to indicate if there is a suitable
322 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
324 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
326 SelectionDAG &DAG) const {
330 /// getOperationAction - Return how this operation should be treated: either
331 /// it is legal, needs to be promoted to a larger size, needs to be
332 /// expanded to some other code sequence, or the target has a custom expander
334 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
335 if (VT.isExtended()) return Expand;
336 assert(Op < array_lengthof(OpActions) &&
337 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
338 "Table isn't big enough!");
339 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
342 /// isOperationLegal - Return true if the specified operation is legal on this
344 bool isOperationLegal(unsigned Op, MVT VT) const {
345 return (VT == MVT::Other || isTypeLegal(VT)) &&
346 (getOperationAction(Op, VT) == Legal ||
347 getOperationAction(Op, VT) == Custom);
350 /// getLoadExtAction - Return how this load with extension should be treated:
351 /// either it is legal, needs to be promoted to a larger size, needs to be
352 /// expanded to some other code sequence, or the target has a custom expander
354 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
355 assert(LType < array_lengthof(LoadExtActions) &&
356 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
357 "Table isn't big enough!");
358 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
361 /// isLoadExtLegal - Return true if the specified load with extension is legal
363 bool isLoadExtLegal(unsigned LType, MVT VT) const {
364 return VT.isSimple() &&
365 (getLoadExtAction(LType, VT) == Legal ||
366 getLoadExtAction(LType, VT) == Custom);
369 /// getTruncStoreAction - Return how this store with truncation should be
370 /// treated: either it is legal, needs to be promoted to a larger size, needs
371 /// to be expanded to some other code sequence, or the target has a custom
373 LegalizeAction getTruncStoreAction(MVT ValVT,
375 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
376 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
377 "Table isn't big enough!");
378 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
379 (2*MemVT.getSimpleVT())) & 3);
382 /// isTruncStoreLegal - Return true if the specified store with truncation is
383 /// legal on this target.
384 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
385 return isTypeLegal(ValVT) && MemVT.isSimple() &&
386 (getTruncStoreAction(ValVT, MemVT) == Legal ||
387 getTruncStoreAction(ValVT, MemVT) == Custom);
390 /// getIndexedLoadAction - Return how the indexed load should be treated:
391 /// either it is legal, needs to be promoted to a larger size, needs to be
392 /// expanded to some other code sequence, or the target has a custom expander
395 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
396 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
397 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
398 "Table isn't big enough!");
399 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
400 (2*VT.getSimpleVT())) & 3);
403 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
405 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
406 return VT.isSimple() &&
407 (getIndexedLoadAction(IdxMode, VT) == Legal ||
408 getIndexedLoadAction(IdxMode, VT) == Custom);
411 /// getIndexedStoreAction - Return how the indexed store should be treated:
412 /// either it is legal, needs to be promoted to a larger size, needs to be
413 /// expanded to some other code sequence, or the target has a custom expander
416 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
417 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
418 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
419 "Table isn't big enough!");
420 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
421 (2*VT.getSimpleVT())) & 3);
424 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
426 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
427 return VT.isSimple() &&
428 (getIndexedStoreAction(IdxMode, VT) == Legal ||
429 getIndexedStoreAction(IdxMode, VT) == Custom);
432 /// getConvertAction - Return how the conversion should be treated:
433 /// either it is legal, needs to be promoted to a larger size, needs to be
434 /// expanded to some other code sequence, or the target has a custom expander
437 getConvertAction(MVT FromVT, MVT ToVT) const {
438 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
439 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
440 "Table isn't big enough!");
441 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
442 (2*ToVT.getSimpleVT())) & 3);
445 /// isConvertLegal - Return true if the specified conversion is legal
447 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
448 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
449 (getConvertAction(FromVT, ToVT) == Legal ||
450 getConvertAction(FromVT, ToVT) == Custom);
453 /// getCondCodeAction - Return how the condition code should be treated:
454 /// either it is legal, needs to be expanded to some other code sequence,
455 /// or the target has a custom expander for it.
457 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
458 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
459 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
460 "Table isn't big enough!");
461 LegalizeAction Action = (LegalizeAction)
462 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
463 assert(Action != Promote && "Can't promote condition code!");
467 /// isCondCodeLegal - Return true if the specified condition code is legal
469 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
470 return getCondCodeAction(CC, VT) == Legal ||
471 getCondCodeAction(CC, VT) == Custom;
475 /// getTypeToPromoteTo - If the action for this operation is to promote, this
476 /// method returns the ValueType to promote to.
477 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
478 assert(getOperationAction(Op, VT) == Promote &&
479 "This operation isn't promoted!");
481 // See if this has an explicit type specified.
482 std::map<std::pair<unsigned, MVT::SimpleValueType>,
483 MVT::SimpleValueType>::const_iterator PTTI =
484 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
485 if (PTTI != PromoteToType.end()) return PTTI->second;
487 assert((VT.isInteger() || VT.isFloatingPoint()) &&
488 "Cannot autopromote this type, add it with AddPromotedToType.");
492 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
493 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
494 "Didn't find type to promote to!");
495 } while (!isTypeLegal(NVT) ||
496 getOperationAction(Op, NVT) == Promote);
500 /// getValueType - Return the MVT corresponding to this LLVM type.
501 /// This is fixed by the LLVM operations except for the pointer size. If
502 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
503 /// counterpart (e.g. structs), otherwise it will assert.
504 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
505 MVT VT = MVT::getMVT(Ty, AllowUnknown);
506 return VT == MVT::iPTR ? PointerTy : VT;
509 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
510 /// function arguments in the caller parameter area. This is the actual
511 /// alignment, not its logarithm.
512 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
514 /// getRegisterType - Return the type of registers that this ValueType will
515 /// eventually require.
516 MVT getRegisterType(MVT VT) const {
518 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
519 return RegisterTypeForVT[VT.getSimpleVT()];
523 unsigned NumIntermediates;
524 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
527 if (VT.isInteger()) {
528 return getRegisterType(getTypeToTransformTo(VT));
530 assert(0 && "Unsupported extended type!");
531 return MVT(); // Not reached
534 /// getNumRegisters - Return the number of registers that this ValueType will
535 /// eventually require. This is one for any types promoted to live in larger
536 /// registers, but may be more than one for types (like i64) that are split
537 /// into pieces. For types like i140, which are first promoted then expanded,
538 /// it is the number of registers needed to hold all the bits of the original
539 /// type. For an i140 on a 32 bit machine this means 5 registers.
540 unsigned getNumRegisters(MVT VT) const {
542 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
543 return NumRegistersForVT[VT.getSimpleVT()];
547 unsigned NumIntermediates;
548 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
550 if (VT.isInteger()) {
551 unsigned BitWidth = VT.getSizeInBits();
552 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
553 return (BitWidth + RegWidth - 1) / RegWidth;
555 assert(0 && "Unsupported extended type!");
556 return 0; // Not reached
559 /// ShouldShrinkFPConstant - If true, then instruction selection should
560 /// seek to shrink the FP constant of the specified type to a smaller type
561 /// in order to save space and / or reduce runtime.
562 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
564 /// hasTargetDAGCombine - If true, the target has custom DAG combine
565 /// transformations that it can perform for the specified node.
566 bool hasTargetDAGCombine(ISD::NodeType NT) const {
567 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
568 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
571 /// This function returns the maximum number of store operations permitted
572 /// to replace a call to llvm.memset. The value is set by the target at the
573 /// performance threshold for such a replacement.
574 /// @brief Get maximum # of store operations permitted for llvm.memset
575 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
577 /// This function returns the maximum number of store operations permitted
578 /// to replace a call to llvm.memcpy. The value is set by the target at the
579 /// performance threshold for such a replacement.
580 /// @brief Get maximum # of store operations permitted for llvm.memcpy
581 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
583 /// This function returns the maximum number of store operations permitted
584 /// to replace a call to llvm.memmove. The value is set by the target at the
585 /// performance threshold for such a replacement.
586 /// @brief Get maximum # of store operations permitted for llvm.memmove
587 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
589 /// This function returns true if the target allows unaligned memory accesses.
590 /// This is used, for example, in situations where an array copy/move/set is
591 /// converted to a sequence of store operations. It's use helps to ensure that
592 /// such replacements don't generate code that causes an alignment error
593 /// (trap) on the target machine.
594 /// @brief Determine if the target supports unaligned memory accesses.
595 bool allowsUnalignedMemoryAccesses() const {
596 return allowUnalignedMemoryAccesses;
599 /// getOptimalMemOpType - Returns the target specific optimal type for load
600 /// and store operations as a result of memset, memcpy, and memmove lowering.
601 /// It returns MVT::iAny if SelectionDAG should be responsible for
603 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
604 bool isSrcConst, bool isSrcStr) const {
608 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
609 /// to implement llvm.setjmp.
610 bool usesUnderscoreSetJmp() const {
611 return UseUnderscoreSetJmp;
614 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
615 /// to implement llvm.longjmp.
616 bool usesUnderscoreLongJmp() const {
617 return UseUnderscoreLongJmp;
620 /// getStackPointerRegisterToSaveRestore - If a physical register, this
621 /// specifies the register that llvm.savestack/llvm.restorestack should save
623 unsigned getStackPointerRegisterToSaveRestore() const {
624 return StackPointerRegisterToSaveRestore;
627 /// getExceptionAddressRegister - If a physical register, this returns
628 /// the register that receives the exception address on entry to a landing
630 unsigned getExceptionAddressRegister() const {
631 return ExceptionPointerRegister;
634 /// getExceptionSelectorRegister - If a physical register, this returns
635 /// the register that receives the exception typeid on entry to a landing
637 unsigned getExceptionSelectorRegister() const {
638 return ExceptionSelectorRegister;
641 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
642 /// set, the default is 200)
643 unsigned getJumpBufSize() const {
647 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
648 /// (if never set, the default is 0)
649 unsigned getJumpBufAlignment() const {
650 return JumpBufAlignment;
653 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
654 /// limit. Any block whose size is greater should not be predicated.
655 unsigned getIfCvtBlockSizeLimit() const {
656 return IfCvtBlockSizeLimit;
659 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
660 /// block to be considered for duplication. Any block whose size is greater
661 /// should not be duplicated to facilitate its predication.
662 unsigned getIfCvtDupBlockSizeLimit() const {
663 return IfCvtDupBlockSizeLimit;
666 /// getPrefLoopAlignment - return the preferred loop alignment.
668 unsigned getPrefLoopAlignment() const {
669 return PrefLoopAlignment;
672 /// getPreIndexedAddressParts - returns true by value, base pointer and
673 /// offset pointer and addressing mode by reference if the node's address
674 /// can be legally represented as pre-indexed load / store address.
675 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
677 ISD::MemIndexedMode &AM,
682 /// getPostIndexedAddressParts - returns true by value, base pointer and
683 /// offset pointer and addressing mode by reference if this node can be
684 /// combined with a load / store to form a post-indexed load / store.
685 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
686 SDValue &Base, SDValue &Offset,
687 ISD::MemIndexedMode &AM,
692 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
694 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
695 SelectionDAG &DAG) const;
697 /// isOffsetFoldingLegal - Return true if folding a constant offset
698 /// with the given GlobalAddress is legal. It is frequently not legal in
699 /// PIC relocation models.
700 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
702 //===--------------------------------------------------------------------===//
703 // TargetLowering Optimization Methods
706 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
707 /// SDValues for returning information from TargetLowering to its clients
708 /// that want to combine
709 struct TargetLoweringOpt {
714 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
716 bool CombineTo(SDValue O, SDValue N) {
722 /// ShrinkDemandedConstant - Check to see if the specified operand of the
723 /// specified instruction is a constant integer. If so, check to see if
724 /// there are any bits set in the constant that are not demanded. If so,
725 /// shrink the constant and return true.
726 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
729 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
730 /// DemandedMask bits of the result of Op are ever used downstream. If we can
731 /// use this information to simplify Op, create a new simplified DAG node and
732 /// return true, returning the original and new nodes in Old and New.
733 /// Otherwise, analyze the expression and return a mask of KnownOne and
734 /// KnownZero bits for the expression (used to simplify the caller).
735 /// The KnownZero/One bits may only be accurate for those bits in the
737 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
738 APInt &KnownZero, APInt &KnownOne,
739 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
741 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
742 /// Mask are known to be either zero or one and return them in the
743 /// KnownZero/KnownOne bitsets.
744 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
748 const SelectionDAG &DAG,
749 unsigned Depth = 0) const;
751 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
752 /// targets that want to expose additional information about sign bits to the
754 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
755 unsigned Depth = 0) const;
757 struct DAGCombinerInfo {
758 void *DC; // The DAG Combiner object.
760 bool CalledByLegalizer;
764 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
765 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
767 bool isBeforeLegalize() const { return BeforeLegalize; }
768 bool isCalledByLegalizer() const { return CalledByLegalizer; }
770 void AddToWorklist(SDNode *N);
771 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To);
772 SDValue CombineTo(SDNode *N, SDValue Res);
773 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
776 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
777 /// and cc. If it is unable to simplify it, return a null SDValue.
778 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
779 ISD::CondCode Cond, bool foldBooleans,
780 DAGCombinerInfo &DCI) const;
782 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
783 /// node is a GlobalAddress + offset.
785 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
787 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
788 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
789 /// location that the 'Base' load is loading from.
790 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
791 const MachineFrameInfo *MFI) const;
793 /// PerformDAGCombine - This method will be invoked for all target nodes and
794 /// for any target-independent nodes that the target has registered with
797 /// The semantics are as follows:
799 /// SDValue.Val == 0 - No change was made
800 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
801 /// otherwise - N should be replaced by the returned Operand.
803 /// In addition, methods provided by DAGCombinerInfo may be used to perform
804 /// more complex transformations.
806 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
808 //===--------------------------------------------------------------------===//
809 // TargetLowering Configuration Methods - These methods should be invoked by
810 // the derived class constructor to configure this object for the target.
814 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
815 /// GOT for PC-relative code.
816 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
818 /// setShiftAmountType - Describe the type that should be used for shift
819 /// amounts. This type defaults to the pointer type.
820 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
822 /// setBooleanContents - Specify how the target extends the result of a
823 /// boolean value from i1 to a wider type. See getBooleanContents.
824 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
826 /// setSchedulingPreference - Specify the target scheduling preference.
827 void setSchedulingPreference(SchedPreference Pref) {
828 SchedPreferenceInfo = Pref;
831 /// setShiftAmountFlavor - Describe how the target handles out of range shift
833 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
834 ShiftAmtHandling = OORSA;
837 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
838 /// use _setjmp to implement llvm.setjmp or the non _ version.
839 /// Defaults to false.
840 void setUseUnderscoreSetJmp(bool Val) {
841 UseUnderscoreSetJmp = Val;
844 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
845 /// use _longjmp to implement llvm.longjmp or the non _ version.
846 /// Defaults to false.
847 void setUseUnderscoreLongJmp(bool Val) {
848 UseUnderscoreLongJmp = Val;
851 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
852 /// specifies the register that llvm.savestack/llvm.restorestack should save
854 void setStackPointerRegisterToSaveRestore(unsigned R) {
855 StackPointerRegisterToSaveRestore = R;
858 /// setExceptionPointerRegister - If set to a physical register, this sets
859 /// the register that receives the exception address on entry to a landing
861 void setExceptionPointerRegister(unsigned R) {
862 ExceptionPointerRegister = R;
865 /// setExceptionSelectorRegister - If set to a physical register, this sets
866 /// the register that receives the exception typeid on entry to a landing
868 void setExceptionSelectorRegister(unsigned R) {
869 ExceptionSelectorRegister = R;
872 /// SelectIsExpensive - Tells the code generator not to expand operations
873 /// into sequences that use the select operations if possible.
874 void setSelectIsExpensive() { SelectIsExpensive = true; }
876 /// setIntDivIsCheap - Tells the code generator that integer divide is
877 /// expensive, and if possible, should be replaced by an alternate sequence
878 /// of instructions not containing an integer divide.
879 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
881 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
882 /// srl/add/sra for a signed divide by power of two, and let the target handle
884 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
886 /// addRegisterClass - Add the specified register class as an available
887 /// regclass for the specified value type. This indicates the selector can
888 /// handle values of that class natively.
889 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
890 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
891 AvailableRegClasses.push_back(std::make_pair(VT, RC));
892 RegClassForVT[VT.getSimpleVT()] = RC;
895 /// computeRegisterProperties - Once all of the register classes are added,
896 /// this allows us to compute derived properties we expose.
897 void computeRegisterProperties();
899 /// setOperationAction - Indicate that the specified operation does not work
900 /// with the specified type and indicate what to do about it.
901 void setOperationAction(unsigned Op, MVT VT,
902 LegalizeAction Action) {
903 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
904 Op < array_lengthof(OpActions) && "Table isn't big enough!");
905 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
906 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
909 /// setLoadExtAction - Indicate that the specified load with extension does
910 /// not work with the with specified type and indicate what to do about it.
911 void setLoadExtAction(unsigned ExtType, MVT VT,
912 LegalizeAction Action) {
913 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
914 ExtType < array_lengthof(LoadExtActions) &&
915 "Table isn't big enough!");
916 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
917 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
920 /// setTruncStoreAction - Indicate that the specified truncating store does
921 /// not work with the with specified type and indicate what to do about it.
922 void setTruncStoreAction(MVT ValVT, MVT MemVT,
923 LegalizeAction Action) {
924 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
925 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
926 "Table isn't big enough!");
927 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
928 MemVT.getSimpleVT()*2);
929 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
930 MemVT.getSimpleVT()*2;
933 /// setIndexedLoadAction - Indicate that the specified indexed load does or
934 /// does not work with the with specified type and indicate what to do abort
935 /// it. NOTE: All indexed mode loads are initialized to Expand in
936 /// TargetLowering.cpp
937 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
938 LegalizeAction Action) {
939 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
940 IdxMode < array_lengthof(IndexedModeActions[0]) &&
941 "Table isn't big enough!");
942 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
943 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
946 /// setIndexedStoreAction - Indicate that the specified indexed store does or
947 /// does not work with the with specified type and indicate what to do about
948 /// it. NOTE: All indexed mode stores are initialized to Expand in
949 /// TargetLowering.cpp
950 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
951 LegalizeAction Action) {
952 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
953 IdxMode < array_lengthof(IndexedModeActions[1]) &&
954 "Table isn't big enough!");
955 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
956 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
959 /// setConvertAction - Indicate that the specified conversion does or does
960 /// not work with the with specified type and indicate what to do about it.
961 void setConvertAction(MVT FromVT, MVT ToVT,
962 LegalizeAction Action) {
963 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
964 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
965 "Table isn't big enough!");
966 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
967 ToVT.getSimpleVT()*2);
968 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
969 ToVT.getSimpleVT()*2;
972 /// setCondCodeAction - Indicate that the specified condition code is or isn't
973 /// supported on the target and indicate what to do about it.
974 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) {
975 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
976 (unsigned)CC < array_lengthof(CondCodeActions) &&
977 "Table isn't big enough!");
978 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
979 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2;
982 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
983 /// promotion code defaults to trying a larger integer/fp until it can find
984 /// one that works. If that default is insufficient, this method can be used
985 /// by the target to override the default.
986 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
987 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
988 DestVT.getSimpleVT();
991 /// addLegalFPImmediate - Indicate that this target can instruction select
992 /// the specified FP immediate natively.
993 void addLegalFPImmediate(const APFloat& Imm) {
994 LegalFPImmediates.push_back(Imm);
997 /// setTargetDAGCombine - Targets should invoke this method for each target
998 /// independent node that they want to provide a custom DAG combiner for by
999 /// implementing the PerformDAGCombine virtual method.
1000 void setTargetDAGCombine(ISD::NodeType NT) {
1001 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1002 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1005 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1006 /// bytes); default is 200
1007 void setJumpBufSize(unsigned Size) {
1011 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1012 /// alignment (in bytes); default is 0
1013 void setJumpBufAlignment(unsigned Align) {
1014 JumpBufAlignment = Align;
1017 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1018 /// limit (in number of instructions); default is 2.
1019 void setIfCvtBlockSizeLimit(unsigned Limit) {
1020 IfCvtBlockSizeLimit = Limit;
1023 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1024 /// of instructions) to be considered for code duplication during
1025 /// if-conversion; default is 2.
1026 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1027 IfCvtDupBlockSizeLimit = Limit;
1030 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1031 /// alignment is zero, it means the target does not care about loop alignment.
1032 void setPrefLoopAlignment(unsigned Align) {
1033 PrefLoopAlignment = Align;
1038 virtual const TargetSubtarget *getSubtarget() {
1039 assert(0 && "Not Implemented");
1040 return NULL; // this is here to silence compiler errors
1042 //===--------------------------------------------------------------------===//
1043 // Lowering methods - These methods must be implemented by targets so that
1044 // the SelectionDAGLowering code knows how to lower these.
1047 /// LowerArguments - This hook must be implemented to indicate how we should
1048 /// lower the arguments for the specified function, into the specified DAG.
1050 LowerArguments(Function &F, SelectionDAG &DAG,
1051 SmallVectorImpl<SDValue>& ArgValues);
1053 /// LowerCallTo - This hook lowers an abstract call to a function into an
1054 /// actual call. This returns a pair of operands. The first element is the
1055 /// return value for the function (if RetTy is not VoidTy). The second
1056 /// element is the outgoing token chain.
1057 struct ArgListEntry {
1068 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1069 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1071 typedef std::vector<ArgListEntry> ArgListTy;
1072 virtual std::pair<SDValue, SDValue>
1073 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1074 bool isVarArg, bool isInreg, unsigned CallingConv,
1075 bool isTailCall, SDValue Callee, ArgListTy &Args,
1078 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1079 /// memcpy. This can be used by targets to provide code sequences for cases
1080 /// that don't fit the target's parameters for simple loads/stores and can be
1081 /// more efficient than using a library call. This function can return a null
1082 /// SDValue if the target declines to use custom code and a different
1083 /// lowering strategy should be used.
1085 /// If AlwaysInline is true, the size is constant and the target should not
1086 /// emit any calls and is strongly encouraged to attempt to emit inline code
1087 /// even if it is beyond the usual threshold because this intrinsic is being
1088 /// expanded in a place where calls are not feasible (e.g. within the prologue
1089 /// for another call). If the target chooses to decline an AlwaysInline
1090 /// request here, legalize will resort to using simple loads and stores.
1092 EmitTargetCodeForMemcpy(SelectionDAG &DAG,
1094 SDValue Op1, SDValue Op2,
1095 SDValue Op3, unsigned Align,
1097 const Value *DstSV, uint64_t DstOff,
1098 const Value *SrcSV, uint64_t SrcOff) {
1102 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1103 /// memmove. This can be used by targets to provide code sequences for cases
1104 /// that don't fit the target's parameters for simple loads/stores and can be
1105 /// more efficient than using a library call. This function can return a null
1106 /// SDValue if the target declines to use custom code and a different
1107 /// lowering strategy should be used.
1109 EmitTargetCodeForMemmove(SelectionDAG &DAG,
1111 SDValue Op1, SDValue Op2,
1112 SDValue Op3, unsigned Align,
1113 const Value *DstSV, uint64_t DstOff,
1114 const Value *SrcSV, uint64_t SrcOff) {
1118 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1119 /// memset. This can be used by targets to provide code sequences for cases
1120 /// that don't fit the target's parameters for simple stores and can be more
1121 /// efficient than using a library call. This function can return a null
1122 /// SDValue if the target declines to use custom code and a different
1123 /// lowering strategy should be used.
1125 EmitTargetCodeForMemset(SelectionDAG &DAG,
1127 SDValue Op1, SDValue Op2,
1128 SDValue Op3, unsigned Align,
1129 const Value *DstSV, uint64_t DstOff) {
1133 /// LowerOperation - This callback is invoked for operations that are
1134 /// unsupported by the target, which are registered to use 'custom' lowering,
1135 /// and whose defined values are all legal.
1136 /// If the target has no operations that require custom lowering, it need not
1137 /// implement this. The default implementation of this aborts.
1138 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1140 /// ReplaceNodeResults - This callback is invoked when a node result type is
1141 /// illegal for the target, and the operation was registered to use 'custom'
1142 /// lowering for that result type. The target places new result values for
1143 /// the node in Results (their number and types must exactly match those of
1144 /// the original return values of the node), or leaves Results empty, which
1145 /// indicates that the node is not to be custom lowered after all.
1147 /// If the target has no operations that require custom lowering, it need not
1148 /// implement this. The default implementation aborts.
1149 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1150 SelectionDAG &DAG) {
1151 assert(0 && "ReplaceNodeResults not implemented for this target!");
1154 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1155 /// tail call optimization. Targets which want to do tail call optimization
1156 /// should override this function.
1157 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call,
1159 SelectionDAG &DAG) const {
1163 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly
1164 /// preceeds the RET node and whether the return uses the result of the node
1165 /// or is a void return. This function can be used by the target to determine
1166 /// eligiblity of tail call optimization.
1167 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret) {
1168 unsigned NumOps = Ret.getNumOperands();
1170 (Ret.getOperand(0) == SDValue(TheCall,1) ||
1171 Ret.getOperand(0) == SDValue(TheCall,0))) ||
1173 Ret.getOperand(0) == SDValue(TheCall,
1174 TheCall->getNumValues()-1) &&
1175 Ret.getOperand(1) == SDValue(TheCall,0)))
1180 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1181 /// it exists. Skip a possible ISD::TokenFactor.
1182 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1183 unsigned TailCallNodeOpCode) {
1184 if (Chain.getOpcode() == TailCallNodeOpCode) {
1186 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1187 if (Chain.getNumOperands() &&
1188 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1189 return Chain.getOperand(0);
1194 /// getTargetNodeName() - This method returns the name of a target specific
1196 virtual const char *getTargetNodeName(unsigned Opcode) const;
1198 /// createFastISel - This method returns a target specific FastISel object,
1199 /// or null if the target does not support "fast" ISel.
1201 createFastISel(MachineFunction &,
1202 MachineModuleInfo *,
1203 DenseMap<const Value *, unsigned> &,
1204 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1205 DenseMap<const AllocaInst *, int> &
1207 , SmallSet<Instruction*, 8> &CatchInfoLost
1213 //===--------------------------------------------------------------------===//
1214 // Inline Asm Support hooks
1217 enum ConstraintType {
1218 C_Register, // Constraint represents specific register(s).
1219 C_RegisterClass, // Constraint represents any of register(s) in class.
1220 C_Memory, // Memory constraint.
1221 C_Other, // Something else.
1222 C_Unknown // Unsupported constraint.
1225 /// AsmOperandInfo - This contains information for each constraint that we are
1227 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1228 /// ConstraintCode - This contains the actual string for the code, like "m".
1229 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1230 /// most closely matches the operand.
1231 std::string ConstraintCode;
1233 /// ConstraintType - Information about the constraint code, e.g. Register,
1234 /// RegisterClass, Memory, Other, Unknown.
1235 TargetLowering::ConstraintType ConstraintType;
1237 /// CallOperandval - If this is the result output operand or a
1238 /// clobber, this is null, otherwise it is the incoming operand to the
1239 /// CallInst. This gets modified as the asm is processed.
1240 Value *CallOperandVal;
1242 /// ConstraintVT - The ValueType for the operand value.
1245 /// isMatchingInputConstraint - Return true of this is an input operand that
1246 /// is a matching constraint like "4".
1247 bool isMatchingInputConstraint() const;
1249 /// getMatchedOperand - If this is an input matching constraint, this method
1250 /// returns the output operand it matches.
1251 unsigned getMatchedOperand() const;
1253 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1254 : InlineAsm::ConstraintInfo(info),
1255 ConstraintType(TargetLowering::C_Unknown),
1256 CallOperandVal(0), ConstraintVT(MVT::Other) {
1260 /// ComputeConstraintToUse - Determines the constraint code and constraint
1261 /// type to use for the specific AsmOperandInfo, setting
1262 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1263 /// being passed in is available, it can be passed in as Op, otherwise an
1264 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1265 /// constraint of the inline asm instruction being processed is 'm'.
1266 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1269 SelectionDAG *DAG = 0) const;
1271 /// getConstraintType - Given a constraint, return the type of constraint it
1272 /// is for this target.
1273 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1275 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1276 /// return a list of registers that can be used to satisfy the constraint.
1277 /// This should only be used for C_RegisterClass constraints.
1278 virtual std::vector<unsigned>
1279 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1282 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1283 /// {edx}), return the register number and the register class for the
1286 /// Given a register class constraint, like 'r', if this corresponds directly
1287 /// to an LLVM register class, return a register of 0 and the register class
1290 /// This should only be used for C_Register constraints. On error,
1291 /// this returns a register number of 0 and a null register class pointer..
1292 virtual std::pair<unsigned, const TargetRegisterClass*>
1293 getRegForInlineAsmConstraint(const std::string &Constraint,
1296 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1297 /// with another that has more specific requirements based on the type of the
1298 /// corresponding operand. This returns null if there is no replacement to
1300 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1302 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1303 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1304 /// it means one of the asm constraint of the inline asm instruction being
1305 /// processed is 'm'.
1306 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1308 std::vector<SDValue> &Ops,
1309 SelectionDAG &DAG) const;
1311 //===--------------------------------------------------------------------===//
1315 // EmitInstrWithCustomInserter - This method should be implemented by targets
1316 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1317 // instructions are special in various ways, which require special support to
1318 // insert. The specified MachineInstr is created but not inserted into any
1319 // basic blocks, and the scheduler passes ownership of it to this method.
1320 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1321 MachineBasicBlock *MBB);
1323 //===--------------------------------------------------------------------===//
1324 // Addressing mode description hooks (used by LSR etc).
1327 /// AddrMode - This represents an addressing mode of:
1328 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1329 /// If BaseGV is null, there is no BaseGV.
1330 /// If BaseOffs is zero, there is no base offset.
1331 /// If HasBaseReg is false, there is no base register.
1332 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1336 GlobalValue *BaseGV;
1340 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1343 /// isLegalAddressingMode - Return true if the addressing mode represented by
1344 /// AM is legal for this target, for a load/store of the specified type.
1345 /// TODO: Handle pre/postinc as well.
1346 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1348 /// isTruncateFree - Return true if it's free to truncate a value of
1349 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1350 /// register EAX to i16 by referencing its sub-register AX.
1351 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1355 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1359 //===--------------------------------------------------------------------===//
1360 // Div utility functions
1362 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1363 std::vector<SDNode*>* Created) const;
1364 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1365 std::vector<SDNode*>* Created) const;
1368 //===--------------------------------------------------------------------===//
1369 // Runtime Library hooks
1372 /// setLibcallName - Rename the default libcall routine name for the specified
1374 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1375 LibcallRoutineNames[Call] = Name;
1378 /// getLibcallName - Get the libcall routine name for the specified libcall.
1380 const char *getLibcallName(RTLIB::Libcall Call) const {
1381 return LibcallRoutineNames[Call];
1384 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1385 /// result of the comparison libcall against zero.
1386 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1387 CmpLibcallCCs[Call] = CC;
1390 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1391 /// the comparison libcall against zero.
1392 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1393 return CmpLibcallCCs[Call];
1398 const TargetData *TD;
1400 /// PointerTy - The type to use for pointers, usually i32 or i64.
1404 /// IsLittleEndian - True if this is a little endian target.
1406 bool IsLittleEndian;
1408 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1410 bool UsesGlobalOffsetTable;
1412 /// SelectIsExpensive - Tells the code generator not to expand operations
1413 /// into sequences that use the select operations if possible.
1414 bool SelectIsExpensive;
1416 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1417 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1418 /// a real cost model is in place. If we ever optimize for size, this will be
1419 /// set to true unconditionally.
1422 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1423 /// srl/add/sra for a signed divide by power of two, and let the target handle
1425 bool Pow2DivIsCheap;
1427 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1428 /// llvm.setjmp. Defaults to false.
1429 bool UseUnderscoreSetJmp;
1431 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1432 /// llvm.longjmp. Defaults to false.
1433 bool UseUnderscoreLongJmp;
1435 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1439 OutOfRangeShiftAmount ShiftAmtHandling;
1441 /// BooleanContents - Information about the contents of the high-bits in
1442 /// boolean values held in a type wider than i1. See getBooleanContents.
1443 BooleanContent BooleanContents;
1445 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1446 /// total cycles or lowest register usage.
1447 SchedPreference SchedPreferenceInfo;
1449 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1450 unsigned JumpBufSize;
1452 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1454 unsigned JumpBufAlignment;
1456 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1458 unsigned IfCvtBlockSizeLimit;
1460 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1461 /// duplicated during if-conversion.
1462 unsigned IfCvtDupBlockSizeLimit;
1464 /// PrefLoopAlignment - The perferred loop alignment.
1466 unsigned PrefLoopAlignment;
1468 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1469 /// specifies the register that llvm.savestack/llvm.restorestack should save
1471 unsigned StackPointerRegisterToSaveRestore;
1473 /// ExceptionPointerRegister - If set to a physical register, this specifies
1474 /// the register that receives the exception address on entry to a landing
1476 unsigned ExceptionPointerRegister;
1478 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1479 /// the register that receives the exception typeid on entry to a landing
1481 unsigned ExceptionSelectorRegister;
1483 /// RegClassForVT - This indicates the default register class to use for
1484 /// each ValueType the target supports natively.
1485 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1486 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1487 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1489 /// TransformToType - For any value types we are promoting or expanding, this
1490 /// contains the value type that we are changing to. For Expanded types, this
1491 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1492 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1493 /// by the system, this holds the same type (e.g. i32 -> i32).
1494 MVT TransformToType[MVT::LAST_VALUETYPE];
1496 /// OpActions - For each operation and each value type, keep a LegalizeAction
1497 /// that indicates how instruction selection should deal with the operation.
1498 /// Most operations are Legal (aka, supported natively by the target), but
1499 /// operations that are not should be described. Note that operations on
1500 /// non-legal value types are not described here.
1501 uint64_t OpActions[ISD::BUILTIN_OP_END];
1503 /// LoadExtActions - For each load of load extension type and each value type,
1504 /// keep a LegalizeAction that indicates how instruction selection should deal
1506 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1508 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1509 /// indicates how instruction selection should deal with the store.
1510 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1512 /// IndexedModeActions - For each indexed mode and each value type, keep a
1513 /// pair of LegalizeAction that indicates how instruction selection should
1514 /// deal with the load / store.
1515 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1517 /// ConvertActions - For each conversion from source type to destination type,
1518 /// keep a LegalizeAction that indicates how instruction selection should
1519 /// deal with the conversion.
1520 /// Currently, this is used only for floating->floating conversions
1521 /// (FP_EXTEND and FP_ROUND).
1522 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1524 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1525 /// LegalizeAction that indicates how instruction selection should
1526 /// deal with the condition code.
1527 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1529 ValueTypeActionImpl ValueTypeActions;
1531 std::vector<APFloat> LegalFPImmediates;
1533 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
1535 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1536 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1537 /// which sets a bit in this array.
1539 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1541 /// PromoteToType - For operations that must be promoted to a specific type,
1542 /// this holds the destination type. This map should be sparse, so don't hold
1545 /// Targets add entries to this map with AddPromotedToType(..), clients access
1546 /// this with getTypeToPromoteTo(..).
1547 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1550 /// LibcallRoutineNames - Stores the name each libcall.
1552 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1554 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1555 /// of each of the comparison libcall against zero.
1556 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1559 /// When lowering @llvm.memset this field specifies the maximum number of
1560 /// store operations that may be substituted for the call to memset. Targets
1561 /// must set this value based on the cost threshold for that target. Targets
1562 /// should assume that the memset will be done using as many of the largest
1563 /// store operations first, followed by smaller ones, if necessary, per
1564 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1565 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1566 /// store. This only applies to setting a constant array of a constant size.
1567 /// @brief Specify maximum number of store instructions per memset call.
1568 unsigned maxStoresPerMemset;
1570 /// When lowering @llvm.memcpy this field specifies the maximum number of
1571 /// store operations that may be substituted for a call to memcpy. Targets
1572 /// must set this value based on the cost threshold for that target. Targets
1573 /// should assume that the memcpy will be done using as many of the largest
1574 /// store operations first, followed by smaller ones, if necessary, per
1575 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1576 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1577 /// and one 1-byte store. This only applies to copying a constant array of
1579 /// @brief Specify maximum bytes of store instructions per memcpy call.
1580 unsigned maxStoresPerMemcpy;
1582 /// When lowering @llvm.memmove this field specifies the maximum number of
1583 /// store instructions that may be substituted for a call to memmove. Targets
1584 /// must set this value based on the cost threshold for that target. Targets
1585 /// should assume that the memmove will be done using as many of the largest
1586 /// store operations first, followed by smaller ones, if necessary, per
1587 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1588 /// with 8-bit alignment would result in nine 1-byte stores. This only
1589 /// applies to copying a constant array of constant size.
1590 /// @brief Specify maximum bytes of store instructions per memmove call.
1591 unsigned maxStoresPerMemmove;
1593 /// This field specifies whether the target machine permits unaligned memory
1594 /// accesses. This is used, for example, to determine the size of store
1595 /// operations when copying small arrays and other similar tasks.
1596 /// @brief Indicate whether the target permits unaligned memory accesses.
1597 bool allowUnalignedMemoryAccesses;
1599 } // end llvm namespace