1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/InlineAsm.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/STLExtras.h"
41 class MachineBasicBlock;
42 class MachineFunction;
43 class MachineFrameInfo;
45 class MachineModuleInfo;
51 class TargetRegisterClass;
52 class TargetSubtarget;
55 //===----------------------------------------------------------------------===//
56 /// TargetLowering - This class defines information used to lower LLVM code to
57 /// legal SelectionDAG operators that the target instruction selector can accept
60 /// This class also defines callbacks that targets must implement to lower
61 /// target-specific constructs to SelectionDAG operators.
63 class TargetLowering {
65 /// LegalizeAction - This enum indicates whether operations are valid for a
66 /// target, and if not, what action should be used to make them valid.
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand, // Try to expand this to other ops, otherwise use a libcall.
71 Custom // Use the LowerOperation hook to implement custom lowering.
74 enum OutOfRangeShiftAmount {
75 Undefined, // Oversized shift amounts are undefined (default).
76 Mask, // Shift amounts are auto masked (anded) to value size.
77 Extend // Oversized shift pulls in zeros or sign bits.
80 enum BooleanContent { // How the target represents true/false values.
81 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
82 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
83 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
86 enum SchedPreference {
87 SchedulingForLatency, // Scheduling for shortest total latency.
88 SchedulingForRegPressure // Scheduling for lowest register pressure.
91 explicit TargetLowering(TargetMachine &TM);
92 virtual ~TargetLowering();
94 TargetMachine &getTargetMachine() const { return TM; }
95 const TargetData *getTargetData() const { return TD; }
97 bool isBigEndian() const { return !IsLittleEndian; }
98 bool isLittleEndian() const { return IsLittleEndian; }
99 MVT getPointerTy() const { return PointerTy; }
100 MVT getShiftAmountTy() const { return ShiftAmountTy; }
101 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
103 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
105 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
107 /// isSelectExpensive - Return true if the select operation is expensive for
109 bool isSelectExpensive() const { return SelectIsExpensive; }
111 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
112 /// a sequence of several shifts, adds, and multiplies for this target.
113 bool isIntDivCheap() const { return IntDivIsCheap; }
115 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
117 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
119 /// getSetCCResultType - Return the ValueType of the result of setcc
121 virtual MVT getSetCCResultType(MVT VT) const;
123 /// getBooleanContents - For targets without i1 registers, this gives the
124 /// nature of the high-bits of boolean values held in types wider than i1.
125 /// "Boolean values" are special true/false values produced by nodes like
126 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
127 /// Not to be confused with general values promoted from i1.
128 BooleanContent getBooleanContents() const { return BooleanContents;}
130 /// getSchedulingPreference - Return target scheduling preference.
131 SchedPreference getSchedulingPreference() const {
132 return SchedPreferenceInfo;
135 /// getRegClassFor - Return the register class that should be used for the
136 /// specified value type. This may only be called on legal types.
137 TargetRegisterClass *getRegClassFor(MVT VT) const {
138 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
139 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
140 assert(RC && "This value type is not natively supported!");
144 /// isTypeLegal - Return true if the target has native support for the
145 /// specified value type. This means that it has a register that directly
146 /// holds it without promotions or expansions.
147 bool isTypeLegal(MVT VT) const {
148 assert(!VT.isSimple() ||
149 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
150 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
153 class ValueTypeActionImpl {
154 /// ValueTypeActions - This is a bitvector that contains two bits for each
155 /// value type, where the two bits correspond to the LegalizeAction enum.
156 /// This can be queried with "getTypeAction(VT)".
157 uint32_t ValueTypeActions[2];
159 ValueTypeActionImpl() {
160 ValueTypeActions[0] = ValueTypeActions[1] = 0;
162 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
163 ValueTypeActions[0] = RHS.ValueTypeActions[0];
164 ValueTypeActions[1] = RHS.ValueTypeActions[1];
167 LegalizeAction getTypeAction(MVT VT) const {
168 if (VT.isExtended()) {
170 return VT.isPow2VectorType() ? Expand : Promote;
173 // First promote to a power-of-two size, then expand if necessary.
174 return VT == VT.getRoundIntegerType() ? Expand : Promote;
175 assert(0 && "Unsupported extended type!");
178 unsigned I = VT.getSimpleVT();
179 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
180 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
182 void setTypeAction(MVT VT, LegalizeAction Action) {
183 unsigned I = VT.getSimpleVT();
184 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
185 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
189 const ValueTypeActionImpl &getValueTypeActions() const {
190 return ValueTypeActions;
193 /// getTypeAction - Return how we should legalize values of this type, either
194 /// it is already legal (return 'Legal') or we need to promote it to a larger
195 /// type (return 'Promote'), or we need to expand it into multiple registers
196 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
197 LegalizeAction getTypeAction(MVT VT) const {
198 return ValueTypeActions.getTypeAction(VT);
201 /// getTypeToTransformTo - For types supported by the target, this is an
202 /// identity function. For types that must be promoted to larger types, this
203 /// returns the larger type to promote to. For integer types that are larger
204 /// than the largest integer register, this contains one step in the expansion
205 /// to get to the smaller register. For illegal floating point types, this
206 /// returns the integer type to transform to.
207 MVT getTypeToTransformTo(MVT VT) const {
209 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
210 MVT NVT = TransformToType[VT.getSimpleVT()];
211 assert(getTypeAction(NVT) != Promote &&
212 "Promote may not follow Expand or Promote");
217 MVT NVT = VT.getPow2VectorType();
219 // Vector length is a power of 2 - split to half the size.
220 unsigned NumElts = VT.getVectorNumElements();
221 MVT EltVT = VT.getVectorElementType();
222 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
224 // Promote to a power of two size, avoiding multi-step promotion.
225 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
226 } else if (VT.isInteger()) {
227 MVT NVT = VT.getRoundIntegerType();
229 // Size is a power of two - expand to half the size.
230 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
232 // Promote to a power of two size, avoiding multi-step promotion.
233 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
235 assert(0 && "Unsupported extended type!");
236 return MVT(); // Not reached
239 /// getTypeToExpandTo - For types supported by the target, this is an
240 /// identity function. For types that must be expanded (i.e. integer types
241 /// that are larger than the largest integer register or illegal floating
242 /// point types), this returns the largest legal type it will be expanded to.
243 MVT getTypeToExpandTo(MVT VT) const {
244 assert(!VT.isVector());
246 switch (getTypeAction(VT)) {
250 VT = getTypeToTransformTo(VT);
253 assert(false && "Type is not legal nor is it to be expanded!");
260 /// getVectorTypeBreakdown - Vector types are broken down into some number of
261 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
262 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
263 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
265 /// This method returns the number of registers needed, and the VT for each
266 /// register. It also returns the VT and quantity of the intermediate values
267 /// before they are promoted/expanded.
269 unsigned getVectorTypeBreakdown(MVT VT,
271 unsigned &NumIntermediates,
272 MVT &RegisterVT) const;
274 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
275 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
276 /// this is the case, it returns true and store the intrinsic
277 /// information into the IntrinsicInfo that was passed to the function.
278 typedef struct IntrinsicInfo {
279 unsigned opc; // target opcode
280 MVT memVT; // memory VT
281 const Value* ptrVal; // value representing memory location
282 int offset; // offset off of ptrVal
283 unsigned align; // alignment
284 bool vol; // is volatile?
285 bool readMem; // reads memory?
286 bool writeMem; // writes memory?
289 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
290 CallInst &I, unsigned Intrinsic) {
294 /// getWidenVectorType: given a vector type, returns the type to widen to
295 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
296 /// If there is no vector type that we want to widen to, returns MVT::Other
297 /// When and were to widen is target dependent based on the cost of
298 /// scalarizing vs using the wider vector type.
299 virtual MVT getWidenVectorType(MVT VT);
301 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
302 legal_fpimm_iterator legal_fpimm_begin() const {
303 return LegalFPImmediates.begin();
305 legal_fpimm_iterator legal_fpimm_end() const {
306 return LegalFPImmediates.end();
309 /// isShuffleMaskLegal - Targets can use this to indicate that they only
310 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
311 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
312 /// are assumed to be legal.
313 virtual bool isShuffleMaskLegal(SDValue Mask, MVT VT) const {
317 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
318 /// used by Targets can use this to indicate if there is a suitable
319 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
321 virtual bool isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
323 SelectionDAG &DAG) const {
327 /// getOperationAction - Return how this operation should be treated: either
328 /// it is legal, needs to be promoted to a larger size, needs to be
329 /// expanded to some other code sequence, or the target has a custom expander
331 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
332 if (VT.isExtended()) return Expand;
333 assert(Op < array_lengthof(OpActions) &&
334 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
335 "Table isn't big enough!");
336 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
339 /// isOperationLegal - Return true if the specified operation is legal on this
341 bool isOperationLegal(unsigned Op, MVT VT) const {
342 return (VT == MVT::Other || isTypeLegal(VT)) &&
343 (getOperationAction(Op, VT) == Legal ||
344 getOperationAction(Op, VT) == Custom);
347 /// getLoadExtAction - Return how this load with extension should be treated:
348 /// either it is legal, needs to be promoted to a larger size, needs to be
349 /// expanded to some other code sequence, or the target has a custom expander
351 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
352 assert(LType < array_lengthof(LoadExtActions) &&
353 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
354 "Table isn't big enough!");
355 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
358 /// isLoadExtLegal - Return true if the specified load with extension is legal
360 bool isLoadExtLegal(unsigned LType, MVT VT) const {
361 return VT.isSimple() &&
362 (getLoadExtAction(LType, VT) == Legal ||
363 getLoadExtAction(LType, VT) == Custom);
366 /// getTruncStoreAction - Return how this store with truncation should be
367 /// treated: either it is legal, needs to be promoted to a larger size, needs
368 /// to be expanded to some other code sequence, or the target has a custom
370 LegalizeAction getTruncStoreAction(MVT ValVT,
372 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
373 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
374 "Table isn't big enough!");
375 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
376 (2*MemVT.getSimpleVT())) & 3);
379 /// isTruncStoreLegal - Return true if the specified store with truncation is
380 /// legal on this target.
381 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
382 return isTypeLegal(ValVT) && MemVT.isSimple() &&
383 (getTruncStoreAction(ValVT, MemVT) == Legal ||
384 getTruncStoreAction(ValVT, MemVT) == Custom);
387 /// getIndexedLoadAction - Return how the indexed load should be treated:
388 /// either it is legal, needs to be promoted to a larger size, needs to be
389 /// expanded to some other code sequence, or the target has a custom expander
392 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
393 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
394 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
395 "Table isn't big enough!");
396 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
397 (2*VT.getSimpleVT())) & 3);
400 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
402 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
403 return VT.isSimple() &&
404 (getIndexedLoadAction(IdxMode, VT) == Legal ||
405 getIndexedLoadAction(IdxMode, VT) == Custom);
408 /// getIndexedStoreAction - Return how the indexed store should be treated:
409 /// either it is legal, needs to be promoted to a larger size, needs to be
410 /// expanded to some other code sequence, or the target has a custom expander
413 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
414 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
415 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
416 "Table isn't big enough!");
417 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
418 (2*VT.getSimpleVT())) & 3);
421 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
423 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
424 return VT.isSimple() &&
425 (getIndexedStoreAction(IdxMode, VT) == Legal ||
426 getIndexedStoreAction(IdxMode, VT) == Custom);
429 /// getConvertAction - Return how the conversion should be treated:
430 /// either it is legal, needs to be promoted to a larger size, needs to be
431 /// expanded to some other code sequence, or the target has a custom expander
434 getConvertAction(MVT FromVT, MVT ToVT) const {
435 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
436 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
437 "Table isn't big enough!");
438 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
439 (2*ToVT.getSimpleVT())) & 3);
442 /// isConvertLegal - Return true if the specified conversion is legal
444 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
445 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
446 (getConvertAction(FromVT, ToVT) == Legal ||
447 getConvertAction(FromVT, ToVT) == Custom);
450 /// getCondCodeAction - Return how the condition code should be treated:
451 /// either it is legal, needs to be expanded to some other code sequence,
452 /// or the target has a custom expander for it.
454 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
455 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
456 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
457 "Table isn't big enough!");
458 LegalizeAction Action = (LegalizeAction)
459 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
460 assert(Action != Promote && "Can't promote condition code!");
464 /// isCondCodeLegal - Return true if the specified condition code is legal
466 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
467 return getCondCodeAction(CC, VT) == Legal ||
468 getCondCodeAction(CC, VT) == Custom;
472 /// getTypeToPromoteTo - If the action for this operation is to promote, this
473 /// method returns the ValueType to promote to.
474 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
475 assert(getOperationAction(Op, VT) == Promote &&
476 "This operation isn't promoted!");
478 // See if this has an explicit type specified.
479 std::map<std::pair<unsigned, MVT::SimpleValueType>,
480 MVT::SimpleValueType>::const_iterator PTTI =
481 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
482 if (PTTI != PromoteToType.end()) return PTTI->second;
484 assert((VT.isInteger() || VT.isFloatingPoint()) &&
485 "Cannot autopromote this type, add it with AddPromotedToType.");
489 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
490 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
491 "Didn't find type to promote to!");
492 } while (!isTypeLegal(NVT) ||
493 getOperationAction(Op, NVT) == Promote);
497 /// getValueType - Return the MVT corresponding to this LLVM type.
498 /// This is fixed by the LLVM operations except for the pointer size. If
499 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
500 /// counterpart (e.g. structs), otherwise it will assert.
501 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
502 MVT VT = MVT::getMVT(Ty, AllowUnknown);
503 return VT == MVT::iPTR ? PointerTy : VT;
506 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
507 /// function arguments in the caller parameter area. This is the actual
508 /// alignment, not its logarithm.
509 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
511 /// getRegisterType - Return the type of registers that this ValueType will
512 /// eventually require.
513 MVT getRegisterType(MVT VT) const {
515 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
516 return RegisterTypeForVT[VT.getSimpleVT()];
520 unsigned NumIntermediates;
521 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
524 if (VT.isInteger()) {
525 return getRegisterType(getTypeToTransformTo(VT));
527 assert(0 && "Unsupported extended type!");
528 return MVT(); // Not reached
531 /// getNumRegisters - Return the number of registers that this ValueType will
532 /// eventually require. This is one for any types promoted to live in larger
533 /// registers, but may be more than one for types (like i64) that are split
534 /// into pieces. For types like i140, which are first promoted then expanded,
535 /// it is the number of registers needed to hold all the bits of the original
536 /// type. For an i140 on a 32 bit machine this means 5 registers.
537 unsigned getNumRegisters(MVT VT) const {
539 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
540 return NumRegistersForVT[VT.getSimpleVT()];
544 unsigned NumIntermediates;
545 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
547 if (VT.isInteger()) {
548 unsigned BitWidth = VT.getSizeInBits();
549 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
550 return (BitWidth + RegWidth - 1) / RegWidth;
552 assert(0 && "Unsupported extended type!");
553 return 0; // Not reached
556 /// ShouldShrinkFPConstant - If true, then instruction selection should
557 /// seek to shrink the FP constant of the specified type to a smaller type
558 /// in order to save space and / or reduce runtime.
559 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
561 /// hasTargetDAGCombine - If true, the target has custom DAG combine
562 /// transformations that it can perform for the specified node.
563 bool hasTargetDAGCombine(ISD::NodeType NT) const {
564 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
565 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
568 /// This function returns the maximum number of store operations permitted
569 /// to replace a call to llvm.memset. The value is set by the target at the
570 /// performance threshold for such a replacement.
571 /// @brief Get maximum # of store operations permitted for llvm.memset
572 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
574 /// This function returns the maximum number of store operations permitted
575 /// to replace a call to llvm.memcpy. The value is set by the target at the
576 /// performance threshold for such a replacement.
577 /// @brief Get maximum # of store operations permitted for llvm.memcpy
578 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
580 /// This function returns the maximum number of store operations permitted
581 /// to replace a call to llvm.memmove. The value is set by the target at the
582 /// performance threshold for such a replacement.
583 /// @brief Get maximum # of store operations permitted for llvm.memmove
584 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
586 /// This function returns true if the target allows unaligned memory accesses.
587 /// This is used, for example, in situations where an array copy/move/set is
588 /// converted to a sequence of store operations. It's use helps to ensure that
589 /// such replacements don't generate code that causes an alignment error
590 /// (trap) on the target machine.
591 /// @brief Determine if the target supports unaligned memory accesses.
592 bool allowsUnalignedMemoryAccesses() const {
593 return allowUnalignedMemoryAccesses;
596 /// getOptimalMemOpType - Returns the target specific optimal type for load
597 /// and store operations as a result of memset, memcpy, and memmove lowering.
598 /// It returns MVT::iAny if SelectionDAG should be responsible for
600 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
601 bool isSrcConst, bool isSrcStr) const {
605 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
606 /// to implement llvm.setjmp.
607 bool usesUnderscoreSetJmp() const {
608 return UseUnderscoreSetJmp;
611 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
612 /// to implement llvm.longjmp.
613 bool usesUnderscoreLongJmp() const {
614 return UseUnderscoreLongJmp;
617 /// getStackPointerRegisterToSaveRestore - If a physical register, this
618 /// specifies the register that llvm.savestack/llvm.restorestack should save
620 unsigned getStackPointerRegisterToSaveRestore() const {
621 return StackPointerRegisterToSaveRestore;
624 /// getExceptionAddressRegister - If a physical register, this returns
625 /// the register that receives the exception address on entry to a landing
627 unsigned getExceptionAddressRegister() const {
628 return ExceptionPointerRegister;
631 /// getExceptionSelectorRegister - If a physical register, this returns
632 /// the register that receives the exception typeid on entry to a landing
634 unsigned getExceptionSelectorRegister() const {
635 return ExceptionSelectorRegister;
638 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
639 /// set, the default is 200)
640 unsigned getJumpBufSize() const {
644 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
645 /// (if never set, the default is 0)
646 unsigned getJumpBufAlignment() const {
647 return JumpBufAlignment;
650 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
651 /// limit. Any block whose size is greater should not be predicated.
652 unsigned getIfCvtBlockSizeLimit() const {
653 return IfCvtBlockSizeLimit;
656 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
657 /// block to be considered for duplication. Any block whose size is greater
658 /// should not be duplicated to facilitate its predication.
659 unsigned getIfCvtDupBlockSizeLimit() const {
660 return IfCvtDupBlockSizeLimit;
663 /// getPrefLoopAlignment - return the preferred loop alignment.
665 unsigned getPrefLoopAlignment() const {
666 return PrefLoopAlignment;
669 /// getPreIndexedAddressParts - returns true by value, base pointer and
670 /// offset pointer and addressing mode by reference if the node's address
671 /// can be legally represented as pre-indexed load / store address.
672 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
674 ISD::MemIndexedMode &AM,
679 /// getPostIndexedAddressParts - returns true by value, base pointer and
680 /// offset pointer and addressing mode by reference if this node can be
681 /// combined with a load / store to form a post-indexed load / store.
682 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
683 SDValue &Base, SDValue &Offset,
684 ISD::MemIndexedMode &AM,
689 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
691 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
692 SelectionDAG &DAG) const;
694 /// isOffsetFoldingLegal - Return true if folding a constant offset
695 /// with the given GlobalAddress is legal. It is frequently not legal in
696 /// PIC relocation models.
697 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
699 //===--------------------------------------------------------------------===//
700 // TargetLowering Optimization Methods
703 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
704 /// SDValues for returning information from TargetLowering to its clients
705 /// that want to combine
706 struct TargetLoweringOpt {
711 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
713 bool CombineTo(SDValue O, SDValue N) {
719 /// ShrinkDemandedConstant - Check to see if the specified operand of the
720 /// specified instruction is a constant integer. If so, check to see if
721 /// there are any bits set in the constant that are not demanded. If so,
722 /// shrink the constant and return true.
723 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
726 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
727 /// DemandedMask bits of the result of Op are ever used downstream. If we can
728 /// use this information to simplify Op, create a new simplified DAG node and
729 /// return true, returning the original and new nodes in Old and New.
730 /// Otherwise, analyze the expression and return a mask of KnownOne and
731 /// KnownZero bits for the expression (used to simplify the caller).
732 /// The KnownZero/One bits may only be accurate for those bits in the
734 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
735 APInt &KnownZero, APInt &KnownOne,
736 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
738 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
739 /// Mask are known to be either zero or one and return them in the
740 /// KnownZero/KnownOne bitsets.
741 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
745 const SelectionDAG &DAG,
746 unsigned Depth = 0) const;
748 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
749 /// targets that want to expose additional information about sign bits to the
751 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
752 unsigned Depth = 0) const;
754 struct DAGCombinerInfo {
755 void *DC; // The DAG Combiner object.
757 bool CalledByLegalizer;
761 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
762 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
764 bool isBeforeLegalize() const { return BeforeLegalize; }
765 bool isCalledByLegalizer() const { return CalledByLegalizer; }
767 void AddToWorklist(SDNode *N);
768 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To);
769 SDValue CombineTo(SDNode *N, SDValue Res);
770 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1);
773 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
774 /// and cc. If it is unable to simplify it, return a null SDValue.
775 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
776 ISD::CondCode Cond, bool foldBooleans,
777 DAGCombinerInfo &DCI) const;
779 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
780 /// node is a GlobalAddress + offset.
782 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
784 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
785 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
786 /// location that the 'Base' load is loading from.
787 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
788 const MachineFrameInfo *MFI) const;
790 /// PerformDAGCombine - This method will be invoked for all target nodes and
791 /// for any target-independent nodes that the target has registered with
794 /// The semantics are as follows:
796 /// SDValue.Val == 0 - No change was made
797 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
798 /// otherwise - N should be replaced by the returned Operand.
800 /// In addition, methods provided by DAGCombinerInfo may be used to perform
801 /// more complex transformations.
803 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
805 //===--------------------------------------------------------------------===//
806 // TargetLowering Configuration Methods - These methods should be invoked by
807 // the derived class constructor to configure this object for the target.
811 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
812 /// GOT for PC-relative code.
813 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
815 /// setShiftAmountType - Describe the type that should be used for shift
816 /// amounts. This type defaults to the pointer type.
817 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
819 /// setBooleanContents - Specify how the target extends the result of a
820 /// boolean value from i1 to a wider type. See getBooleanContents.
821 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
823 /// setSchedulingPreference - Specify the target scheduling preference.
824 void setSchedulingPreference(SchedPreference Pref) {
825 SchedPreferenceInfo = Pref;
828 /// setShiftAmountFlavor - Describe how the target handles out of range shift
830 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
831 ShiftAmtHandling = OORSA;
834 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
835 /// use _setjmp to implement llvm.setjmp or the non _ version.
836 /// Defaults to false.
837 void setUseUnderscoreSetJmp(bool Val) {
838 UseUnderscoreSetJmp = Val;
841 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
842 /// use _longjmp to implement llvm.longjmp or the non _ version.
843 /// Defaults to false.
844 void setUseUnderscoreLongJmp(bool Val) {
845 UseUnderscoreLongJmp = Val;
848 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
849 /// specifies the register that llvm.savestack/llvm.restorestack should save
851 void setStackPointerRegisterToSaveRestore(unsigned R) {
852 StackPointerRegisterToSaveRestore = R;
855 /// setExceptionPointerRegister - If set to a physical register, this sets
856 /// the register that receives the exception address on entry to a landing
858 void setExceptionPointerRegister(unsigned R) {
859 ExceptionPointerRegister = R;
862 /// setExceptionSelectorRegister - If set to a physical register, this sets
863 /// the register that receives the exception typeid on entry to a landing
865 void setExceptionSelectorRegister(unsigned R) {
866 ExceptionSelectorRegister = R;
869 /// SelectIsExpensive - Tells the code generator not to expand operations
870 /// into sequences that use the select operations if possible.
871 void setSelectIsExpensive() { SelectIsExpensive = true; }
873 /// setIntDivIsCheap - Tells the code generator that integer divide is
874 /// expensive, and if possible, should be replaced by an alternate sequence
875 /// of instructions not containing an integer divide.
876 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
878 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
879 /// srl/add/sra for a signed divide by power of two, and let the target handle
881 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
883 /// addRegisterClass - Add the specified register class as an available
884 /// regclass for the specified value type. This indicates the selector can
885 /// handle values of that class natively.
886 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
887 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
888 AvailableRegClasses.push_back(std::make_pair(VT, RC));
889 RegClassForVT[VT.getSimpleVT()] = RC;
892 /// computeRegisterProperties - Once all of the register classes are added,
893 /// this allows us to compute derived properties we expose.
894 void computeRegisterProperties();
896 /// setOperationAction - Indicate that the specified operation does not work
897 /// with the specified type and indicate what to do about it.
898 void setOperationAction(unsigned Op, MVT VT,
899 LegalizeAction Action) {
900 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
901 Op < array_lengthof(OpActions) && "Table isn't big enough!");
902 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
903 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
906 /// setLoadExtAction - Indicate that the specified load with extension does
907 /// not work with the with specified type and indicate what to do about it.
908 void setLoadExtAction(unsigned ExtType, MVT VT,
909 LegalizeAction Action) {
910 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
911 ExtType < array_lengthof(LoadExtActions) &&
912 "Table isn't big enough!");
913 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
914 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
917 /// setTruncStoreAction - Indicate that the specified truncating store does
918 /// not work with the with specified type and indicate what to do about it.
919 void setTruncStoreAction(MVT ValVT, MVT MemVT,
920 LegalizeAction Action) {
921 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
922 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
923 "Table isn't big enough!");
924 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
925 MemVT.getSimpleVT()*2);
926 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
927 MemVT.getSimpleVT()*2;
930 /// setIndexedLoadAction - Indicate that the specified indexed load does or
931 /// does not work with the with specified type and indicate what to do abort
932 /// it. NOTE: All indexed mode loads are initialized to Expand in
933 /// TargetLowering.cpp
934 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
935 LegalizeAction Action) {
936 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
937 IdxMode < array_lengthof(IndexedModeActions[0]) &&
938 "Table isn't big enough!");
939 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
940 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
943 /// setIndexedStoreAction - Indicate that the specified indexed store does or
944 /// does not work with the with specified type and indicate what to do about
945 /// it. NOTE: All indexed mode stores are initialized to Expand in
946 /// TargetLowering.cpp
947 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
948 LegalizeAction Action) {
949 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
950 IdxMode < array_lengthof(IndexedModeActions[1]) &&
951 "Table isn't big enough!");
952 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
953 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
956 /// setConvertAction - Indicate that the specified conversion does or does
957 /// not work with the with specified type and indicate what to do about it.
958 void setConvertAction(MVT FromVT, MVT ToVT,
959 LegalizeAction Action) {
960 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
961 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
962 "Table isn't big enough!");
963 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
964 ToVT.getSimpleVT()*2);
965 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
966 ToVT.getSimpleVT()*2;
969 /// setCondCodeAction - Indicate that the specified condition code is or isn't
970 /// supported on the target and indicate what to do about it.
971 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) {
972 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
973 (unsigned)CC < array_lengthof(CondCodeActions) &&
974 "Table isn't big enough!");
975 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
976 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2;
979 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
980 /// promotion code defaults to trying a larger integer/fp until it can find
981 /// one that works. If that default is insufficient, this method can be used
982 /// by the target to override the default.
983 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
984 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
985 DestVT.getSimpleVT();
988 /// addLegalFPImmediate - Indicate that this target can instruction select
989 /// the specified FP immediate natively.
990 void addLegalFPImmediate(const APFloat& Imm) {
991 LegalFPImmediates.push_back(Imm);
994 /// setTargetDAGCombine - Targets should invoke this method for each target
995 /// independent node that they want to provide a custom DAG combiner for by
996 /// implementing the PerformDAGCombine virtual method.
997 void setTargetDAGCombine(ISD::NodeType NT) {
998 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
999 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1002 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1003 /// bytes); default is 200
1004 void setJumpBufSize(unsigned Size) {
1008 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1009 /// alignment (in bytes); default is 0
1010 void setJumpBufAlignment(unsigned Align) {
1011 JumpBufAlignment = Align;
1014 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1015 /// limit (in number of instructions); default is 2.
1016 void setIfCvtBlockSizeLimit(unsigned Limit) {
1017 IfCvtBlockSizeLimit = Limit;
1020 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1021 /// of instructions) to be considered for code duplication during
1022 /// if-conversion; default is 2.
1023 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1024 IfCvtDupBlockSizeLimit = Limit;
1027 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1028 /// alignment is zero, it means the target does not care about loop alignment.
1029 void setPrefLoopAlignment(unsigned Align) {
1030 PrefLoopAlignment = Align;
1035 virtual const TargetSubtarget *getSubtarget() {
1036 assert(0 && "Not Implemented");
1037 return NULL; // this is here to silence compiler errors
1039 //===--------------------------------------------------------------------===//
1040 // Lowering methods - These methods must be implemented by targets so that
1041 // the SelectionDAGLowering code knows how to lower these.
1044 /// LowerArguments - This hook must be implemented to indicate how we should
1045 /// lower the arguments for the specified function, into the specified DAG.
1047 LowerArguments(Function &F, SelectionDAG &DAG,
1048 SmallVectorImpl<SDValue>& ArgValues);
1050 /// LowerCallTo - This hook lowers an abstract call to a function into an
1051 /// actual call. This returns a pair of operands. The first element is the
1052 /// return value for the function (if RetTy is not VoidTy). The second
1053 /// element is the outgoing token chain.
1054 struct ArgListEntry {
1065 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1066 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1068 typedef std::vector<ArgListEntry> ArgListTy;
1069 virtual std::pair<SDValue, SDValue>
1070 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1071 bool isVarArg, bool isInreg, unsigned CallingConv,
1072 bool isTailCall, SDValue Callee, ArgListTy &Args,
1075 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1076 /// memcpy. This can be used by targets to provide code sequences for cases
1077 /// that don't fit the target's parameters for simple loads/stores and can be
1078 /// more efficient than using a library call. This function can return a null
1079 /// SDValue if the target declines to use custom code and a different
1080 /// lowering strategy should be used.
1082 /// If AlwaysInline is true, the size is constant and the target should not
1083 /// emit any calls and is strongly encouraged to attempt to emit inline code
1084 /// even if it is beyond the usual threshold because this intrinsic is being
1085 /// expanded in a place where calls are not feasible (e.g. within the prologue
1086 /// for another call). If the target chooses to decline an AlwaysInline
1087 /// request here, legalize will resort to using simple loads and stores.
1089 EmitTargetCodeForMemcpy(SelectionDAG &DAG,
1091 SDValue Op1, SDValue Op2,
1092 SDValue Op3, unsigned Align,
1094 const Value *DstSV, uint64_t DstOff,
1095 const Value *SrcSV, uint64_t SrcOff) {
1099 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1100 /// memmove. This can be used by targets to provide code sequences for cases
1101 /// that don't fit the target's parameters for simple loads/stores and can be
1102 /// more efficient than using a library call. This function can return a null
1103 /// SDValue if the target declines to use custom code and a different
1104 /// lowering strategy should be used.
1106 EmitTargetCodeForMemmove(SelectionDAG &DAG,
1108 SDValue Op1, SDValue Op2,
1109 SDValue Op3, unsigned Align,
1110 const Value *DstSV, uint64_t DstOff,
1111 const Value *SrcSV, uint64_t SrcOff) {
1115 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1116 /// memset. This can be used by targets to provide code sequences for cases
1117 /// that don't fit the target's parameters for simple stores and can be more
1118 /// efficient than using a library call. This function can return a null
1119 /// SDValue if the target declines to use custom code and a different
1120 /// lowering strategy should be used.
1122 EmitTargetCodeForMemset(SelectionDAG &DAG,
1124 SDValue Op1, SDValue Op2,
1125 SDValue Op3, unsigned Align,
1126 const Value *DstSV, uint64_t DstOff) {
1130 /// LowerOperation - This callback is invoked for operations that are
1131 /// unsupported by the target, which are registered to use 'custom' lowering,
1132 /// and whose defined values are all legal.
1133 /// If the target has no operations that require custom lowering, it need not
1134 /// implement this. The default implementation of this aborts.
1135 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1137 /// ReplaceNodeResults - This callback is invoked when a node result type is
1138 /// illegal for the target, and the operation was registered to use 'custom'
1139 /// lowering for that result type. The target places new result values for
1140 /// the node in Results (their number and types must exactly match those of
1141 /// the original return values of the node), or leaves Results empty, which
1142 /// indicates that the node is not to be custom lowered after all.
1144 /// If the target has no operations that require custom lowering, it need not
1145 /// implement this. The default implementation aborts.
1146 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1147 SelectionDAG &DAG) {
1148 assert(0 && "ReplaceNodeResults not implemented for this target!");
1151 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1152 /// tail call optimization. Targets which want to do tail call optimization
1153 /// should override this function.
1154 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call,
1156 SelectionDAG &DAG) const {
1160 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly
1161 /// preceeds the RET node and whether the return uses the result of the node
1162 /// or is a void return. This function can be used by the target to determine
1163 /// eligiblity of tail call optimization.
1164 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret) {
1165 unsigned NumOps = Ret.getNumOperands();
1167 (Ret.getOperand(0) == SDValue(TheCall,1) ||
1168 Ret.getOperand(0) == SDValue(TheCall,0))) ||
1170 Ret.getOperand(0) == SDValue(TheCall,
1171 TheCall->getNumValues()-1) &&
1172 Ret.getOperand(1) == SDValue(TheCall,0)))
1177 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1178 /// it exists. Skip a possible ISD::TokenFactor.
1179 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1180 unsigned TailCallNodeOpCode) {
1181 if (Chain.getOpcode() == TailCallNodeOpCode) {
1183 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1184 if (Chain.getNumOperands() &&
1185 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1186 return Chain.getOperand(0);
1191 /// getTargetNodeName() - This method returns the name of a target specific
1193 virtual const char *getTargetNodeName(unsigned Opcode) const;
1195 /// createFastISel - This method returns a target specific FastISel object,
1196 /// or null if the target does not support "fast" ISel.
1198 createFastISel(MachineFunction &,
1199 MachineModuleInfo *,
1200 DenseMap<const Value *, unsigned> &,
1201 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1202 DenseMap<const AllocaInst *, int> &
1204 , SmallSet<Instruction*, 8> &CatchInfoLost
1210 //===--------------------------------------------------------------------===//
1211 // Inline Asm Support hooks
1214 enum ConstraintType {
1215 C_Register, // Constraint represents specific register(s).
1216 C_RegisterClass, // Constraint represents any of register(s) in class.
1217 C_Memory, // Memory constraint.
1218 C_Other, // Something else.
1219 C_Unknown // Unsupported constraint.
1222 /// AsmOperandInfo - This contains information for each constraint that we are
1224 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1225 /// ConstraintCode - This contains the actual string for the code, like "m".
1226 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1227 /// most closely matches the operand.
1228 std::string ConstraintCode;
1230 /// ConstraintType - Information about the constraint code, e.g. Register,
1231 /// RegisterClass, Memory, Other, Unknown.
1232 TargetLowering::ConstraintType ConstraintType;
1234 /// CallOperandval - If this is the result output operand or a
1235 /// clobber, this is null, otherwise it is the incoming operand to the
1236 /// CallInst. This gets modified as the asm is processed.
1237 Value *CallOperandVal;
1239 /// ConstraintVT - The ValueType for the operand value.
1242 /// isMatchingInputConstraint - Return true of this is an input operand that
1243 /// is a matching constraint like "4".
1244 bool isMatchingInputConstraint() const;
1246 /// getMatchedOperand - If this is an input matching constraint, this method
1247 /// returns the output operand it matches.
1248 unsigned getMatchedOperand() const;
1250 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1251 : InlineAsm::ConstraintInfo(info),
1252 ConstraintType(TargetLowering::C_Unknown),
1253 CallOperandVal(0), ConstraintVT(MVT::Other) {
1257 /// ComputeConstraintToUse - Determines the constraint code and constraint
1258 /// type to use for the specific AsmOperandInfo, setting
1259 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1260 /// being passed in is available, it can be passed in as Op, otherwise an
1261 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1262 /// constraint of the inline asm instruction being processed is 'm'.
1263 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1266 SelectionDAG *DAG = 0) const;
1268 /// getConstraintType - Given a constraint, return the type of constraint it
1269 /// is for this target.
1270 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1272 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1273 /// return a list of registers that can be used to satisfy the constraint.
1274 /// This should only be used for C_RegisterClass constraints.
1275 virtual std::vector<unsigned>
1276 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1279 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1280 /// {edx}), return the register number and the register class for the
1283 /// Given a register class constraint, like 'r', if this corresponds directly
1284 /// to an LLVM register class, return a register of 0 and the register class
1287 /// This should only be used for C_Register constraints. On error,
1288 /// this returns a register number of 0 and a null register class pointer..
1289 virtual std::pair<unsigned, const TargetRegisterClass*>
1290 getRegForInlineAsmConstraint(const std::string &Constraint,
1293 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1294 /// with another that has more specific requirements based on the type of the
1295 /// corresponding operand. This returns null if there is no replacement to
1297 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1299 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1300 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1301 /// it means one of the asm constraint of the inline asm instruction being
1302 /// processed is 'm'.
1303 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1305 std::vector<SDValue> &Ops,
1306 SelectionDAG &DAG) const;
1308 //===--------------------------------------------------------------------===//
1312 // EmitInstrWithCustomInserter - This method should be implemented by targets
1313 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1314 // instructions are special in various ways, which require special support to
1315 // insert. The specified MachineInstr is created but not inserted into any
1316 // basic blocks, and the scheduler passes ownership of it to this method.
1317 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1318 MachineBasicBlock *MBB);
1320 //===--------------------------------------------------------------------===//
1321 // Addressing mode description hooks (used by LSR etc).
1324 /// AddrMode - This represents an addressing mode of:
1325 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1326 /// If BaseGV is null, there is no BaseGV.
1327 /// If BaseOffs is zero, there is no base offset.
1328 /// If HasBaseReg is false, there is no base register.
1329 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1333 GlobalValue *BaseGV;
1337 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1340 /// isLegalAddressingMode - Return true if the addressing mode represented by
1341 /// AM is legal for this target, for a load/store of the specified type.
1342 /// TODO: Handle pre/postinc as well.
1343 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1345 /// isTruncateFree - Return true if it's free to truncate a value of
1346 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1347 /// register EAX to i16 by referencing its sub-register AX.
1348 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1352 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1356 //===--------------------------------------------------------------------===//
1357 // Div utility functions
1359 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1360 std::vector<SDNode*>* Created) const;
1361 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1362 std::vector<SDNode*>* Created) const;
1365 //===--------------------------------------------------------------------===//
1366 // Runtime Library hooks
1369 /// setLibcallName - Rename the default libcall routine name for the specified
1371 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1372 LibcallRoutineNames[Call] = Name;
1375 /// getLibcallName - Get the libcall routine name for the specified libcall.
1377 const char *getLibcallName(RTLIB::Libcall Call) const {
1378 return LibcallRoutineNames[Call];
1381 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1382 /// result of the comparison libcall against zero.
1383 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1384 CmpLibcallCCs[Call] = CC;
1387 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1388 /// the comparison libcall against zero.
1389 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1390 return CmpLibcallCCs[Call];
1395 const TargetData *TD;
1397 /// PointerTy - The type to use for pointers, usually i32 or i64.
1401 /// IsLittleEndian - True if this is a little endian target.
1403 bool IsLittleEndian;
1405 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1407 bool UsesGlobalOffsetTable;
1409 /// SelectIsExpensive - Tells the code generator not to expand operations
1410 /// into sequences that use the select operations if possible.
1411 bool SelectIsExpensive;
1413 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1414 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1415 /// a real cost model is in place. If we ever optimize for size, this will be
1416 /// set to true unconditionally.
1419 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1420 /// srl/add/sra for a signed divide by power of two, and let the target handle
1422 bool Pow2DivIsCheap;
1424 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1425 /// llvm.setjmp. Defaults to false.
1426 bool UseUnderscoreSetJmp;
1428 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1429 /// llvm.longjmp. Defaults to false.
1430 bool UseUnderscoreLongJmp;
1432 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1436 OutOfRangeShiftAmount ShiftAmtHandling;
1438 /// BooleanContents - Information about the contents of the high-bits in
1439 /// boolean values held in a type wider than i1. See getBooleanContents.
1440 BooleanContent BooleanContents;
1442 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1443 /// total cycles or lowest register usage.
1444 SchedPreference SchedPreferenceInfo;
1446 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1447 unsigned JumpBufSize;
1449 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1451 unsigned JumpBufAlignment;
1453 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1455 unsigned IfCvtBlockSizeLimit;
1457 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1458 /// duplicated during if-conversion.
1459 unsigned IfCvtDupBlockSizeLimit;
1461 /// PrefLoopAlignment - The perferred loop alignment.
1463 unsigned PrefLoopAlignment;
1465 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1466 /// specifies the register that llvm.savestack/llvm.restorestack should save
1468 unsigned StackPointerRegisterToSaveRestore;
1470 /// ExceptionPointerRegister - If set to a physical register, this specifies
1471 /// the register that receives the exception address on entry to a landing
1473 unsigned ExceptionPointerRegister;
1475 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1476 /// the register that receives the exception typeid on entry to a landing
1478 unsigned ExceptionSelectorRegister;
1480 /// RegClassForVT - This indicates the default register class to use for
1481 /// each ValueType the target supports natively.
1482 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1483 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1484 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1486 /// TransformToType - For any value types we are promoting or expanding, this
1487 /// contains the value type that we are changing to. For Expanded types, this
1488 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1489 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1490 /// by the system, this holds the same type (e.g. i32 -> i32).
1491 MVT TransformToType[MVT::LAST_VALUETYPE];
1493 /// OpActions - For each operation and each value type, keep a LegalizeAction
1494 /// that indicates how instruction selection should deal with the operation.
1495 /// Most operations are Legal (aka, supported natively by the target), but
1496 /// operations that are not should be described. Note that operations on
1497 /// non-legal value types are not described here.
1498 uint64_t OpActions[ISD::BUILTIN_OP_END];
1500 /// LoadExtActions - For each load of load extension type and each value type,
1501 /// keep a LegalizeAction that indicates how instruction selection should deal
1503 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1505 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1506 /// indicates how instruction selection should deal with the store.
1507 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1509 /// IndexedModeActions - For each indexed mode and each value type, keep a
1510 /// pair of LegalizeAction that indicates how instruction selection should
1511 /// deal with the load / store.
1512 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1514 /// ConvertActions - For each conversion from source type to destination type,
1515 /// keep a LegalizeAction that indicates how instruction selection should
1516 /// deal with the conversion.
1517 /// Currently, this is used only for floating->floating conversions
1518 /// (FP_EXTEND and FP_ROUND).
1519 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1521 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1522 /// LegalizeAction that indicates how instruction selection should
1523 /// deal with the condition code.
1524 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1526 ValueTypeActionImpl ValueTypeActions;
1528 std::vector<APFloat> LegalFPImmediates;
1530 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
1532 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1533 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1534 /// which sets a bit in this array.
1536 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1538 /// PromoteToType - For operations that must be promoted to a specific type,
1539 /// this holds the destination type. This map should be sparse, so don't hold
1542 /// Targets add entries to this map with AddPromotedToType(..), clients access
1543 /// this with getTypeToPromoteTo(..).
1544 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1547 /// LibcallRoutineNames - Stores the name each libcall.
1549 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1551 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1552 /// of each of the comparison libcall against zero.
1553 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1556 /// When lowering @llvm.memset this field specifies the maximum number of
1557 /// store operations that may be substituted for the call to memset. Targets
1558 /// must set this value based on the cost threshold for that target. Targets
1559 /// should assume that the memset will be done using as many of the largest
1560 /// store operations first, followed by smaller ones, if necessary, per
1561 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1562 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1563 /// store. This only applies to setting a constant array of a constant size.
1564 /// @brief Specify maximum number of store instructions per memset call.
1565 unsigned maxStoresPerMemset;
1567 /// When lowering @llvm.memcpy this field specifies the maximum number of
1568 /// store operations that may be substituted for a call to memcpy. Targets
1569 /// must set this value based on the cost threshold for that target. Targets
1570 /// should assume that the memcpy will be done using as many of the largest
1571 /// store operations first, followed by smaller ones, if necessary, per
1572 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1573 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1574 /// and one 1-byte store. This only applies to copying a constant array of
1576 /// @brief Specify maximum bytes of store instructions per memcpy call.
1577 unsigned maxStoresPerMemcpy;
1579 /// When lowering @llvm.memmove this field specifies the maximum number of
1580 /// store instructions that may be substituted for a call to memmove. Targets
1581 /// must set this value based on the cost threshold for that target. Targets
1582 /// should assume that the memmove will be done using as many of the largest
1583 /// store operations first, followed by smaller ones, if necessary, per
1584 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1585 /// with 8-bit alignment would result in nine 1-byte stores. This only
1586 /// applies to copying a constant array of constant size.
1587 /// @brief Specify maximum bytes of store instructions per memmove call.
1588 unsigned maxStoresPerMemmove;
1590 /// This field specifies whether the target machine permits unaligned memory
1591 /// accesses. This is used, for example, to determine the size of store
1592 /// operations when copying small arrays and other similar tasks.
1593 /// @brief Indicate whether the target permits unaligned memory accesses.
1594 bool allowUnalignedMemoryAccesses;
1596 } // end llvm namespace