1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/InlineAsm.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/ADT/APFloat.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/ADT/STLExtras.h"
33 #include "llvm/CodeGen/DebugLoc.h"
34 #include "llvm/Target/TargetMachine.h"
44 class MachineBasicBlock;
45 class MachineFunction;
46 class MachineFrameInfo;
48 class MachineModuleInfo;
55 class TargetRegisterClass;
56 class TargetSubtarget;
59 // FIXME: should this be here?
68 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
71 //===----------------------------------------------------------------------===//
72 /// TargetLowering - This class defines information used to lower LLVM code to
73 /// legal SelectionDAG operators that the target instruction selector can accept
76 /// This class also defines callbacks that targets must implement to lower
77 /// target-specific constructs to SelectionDAG operators.
79 class TargetLowering {
81 /// LegalizeAction - This enum indicates whether operations are valid for a
82 /// target, and if not, what action should be used to make them valid.
84 Legal, // The target natively supports this operation.
85 Promote, // This operation should be executed in a larger type.
86 Expand, // Try to expand this to other ops, otherwise use a libcall.
87 Custom // Use the LowerOperation hook to implement custom lowering.
90 enum OutOfRangeShiftAmount {
91 Undefined, // Oversized shift amounts are undefined (default).
92 Mask, // Shift amounts are auto masked (anded) to value size.
93 Extend // Oversized shift pulls in zeros or sign bits.
96 enum BooleanContent { // How the target represents true/false values.
97 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
98 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
99 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
102 enum SchedPreference {
103 SchedulingForLatency, // Scheduling for shortest total latency.
104 SchedulingForRegPressure // Scheduling for lowest register pressure.
107 explicit TargetLowering(TargetMachine &TM);
108 virtual ~TargetLowering();
110 TargetMachine &getTargetMachine() const { return TM; }
111 const TargetData *getTargetData() const { return TD; }
113 bool isBigEndian() const { return !IsLittleEndian; }
114 bool isLittleEndian() const { return IsLittleEndian; }
115 MVT getPointerTy() const { return PointerTy; }
116 MVT getShiftAmountTy() const { return ShiftAmountTy; }
117 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
119 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
121 bool usesGlobalOffsetTable() const { return UsesGlobalOffsetTable; }
123 /// isSelectExpensive - Return true if the select operation is expensive for
125 bool isSelectExpensive() const { return SelectIsExpensive; }
127 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
128 /// a sequence of several shifts, adds, and multiplies for this target.
129 bool isIntDivCheap() const { return IntDivIsCheap; }
131 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
133 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
135 /// getSetCCResultType - Return the ValueType of the result of SETCC
136 /// operations. Also used to obtain the target's preferred type for
137 /// the condition operand of SELECT and BRCOND nodes. In the case of
138 /// BRCOND the argument passed is MVT::Other since there are no other
139 /// operands to get a type hint from.
140 virtual MVT getSetCCResultType(MVT VT) const;
142 /// getBooleanContents - For targets without i1 registers, this gives the
143 /// nature of the high-bits of boolean values held in types wider than i1.
144 /// "Boolean values" are special true/false values produced by nodes like
145 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
146 /// Not to be confused with general values promoted from i1.
147 BooleanContent getBooleanContents() const { return BooleanContents;}
149 /// getSchedulingPreference - Return target scheduling preference.
150 SchedPreference getSchedulingPreference() const {
151 return SchedPreferenceInfo;
154 /// getRegClassFor - Return the register class that should be used for the
155 /// specified value type. This may only be called on legal types.
156 TargetRegisterClass *getRegClassFor(MVT VT) const {
157 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
158 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
159 assert(RC && "This value type is not natively supported!");
163 /// isTypeLegal - Return true if the target has native support for the
164 /// specified value type. This means that it has a register that directly
165 /// holds it without promotions or expansions.
166 bool isTypeLegal(MVT VT) const {
167 assert(!VT.isSimple() ||
168 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
169 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
172 class ValueTypeActionImpl {
173 /// ValueTypeActions - This is a bitvector that contains two bits for each
174 /// value type, where the two bits correspond to the LegalizeAction enum.
175 /// This can be queried with "getTypeAction(VT)".
176 uint32_t ValueTypeActions[2];
178 ValueTypeActionImpl() {
179 ValueTypeActions[0] = ValueTypeActions[1] = 0;
181 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
182 ValueTypeActions[0] = RHS.ValueTypeActions[0];
183 ValueTypeActions[1] = RHS.ValueTypeActions[1];
186 LegalizeAction getTypeAction(MVT VT) const {
187 if (VT.isExtended()) {
189 return VT.isPow2VectorType() ? Expand : Promote;
192 // First promote to a power-of-two size, then expand if necessary.
193 return VT == VT.getRoundIntegerType() ? Expand : Promote;
194 assert(0 && "Unsupported extended type!");
197 unsigned I = VT.getSimpleVT();
198 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
199 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
201 void setTypeAction(MVT VT, LegalizeAction Action) {
202 unsigned I = VT.getSimpleVT();
203 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
204 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
208 const ValueTypeActionImpl &getValueTypeActions() const {
209 return ValueTypeActions;
212 /// getTypeAction - Return how we should legalize values of this type, either
213 /// it is already legal (return 'Legal') or we need to promote it to a larger
214 /// type (return 'Promote'), or we need to expand it into multiple registers
215 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
216 LegalizeAction getTypeAction(MVT VT) const {
217 return ValueTypeActions.getTypeAction(VT);
220 /// getTypeToTransformTo - For types supported by the target, this is an
221 /// identity function. For types that must be promoted to larger types, this
222 /// returns the larger type to promote to. For integer types that are larger
223 /// than the largest integer register, this contains one step in the expansion
224 /// to get to the smaller register. For illegal floating point types, this
225 /// returns the integer type to transform to.
226 MVT getTypeToTransformTo(MVT VT) const {
228 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
229 MVT NVT = TransformToType[VT.getSimpleVT()];
230 assert(getTypeAction(NVT) != Promote &&
231 "Promote may not follow Expand or Promote");
236 MVT NVT = VT.getPow2VectorType();
238 // Vector length is a power of 2 - split to half the size.
239 unsigned NumElts = VT.getVectorNumElements();
240 MVT EltVT = VT.getVectorElementType();
241 return (NumElts == 1) ? EltVT : MVT::getVectorVT(EltVT, NumElts / 2);
243 // Promote to a power of two size, avoiding multi-step promotion.
244 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
245 } else if (VT.isInteger()) {
246 MVT NVT = VT.getRoundIntegerType();
248 // Size is a power of two - expand to half the size.
249 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
251 // Promote to a power of two size, avoiding multi-step promotion.
252 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
254 assert(0 && "Unsupported extended type!");
255 return MVT(); // Not reached
258 /// getTypeToExpandTo - For types supported by the target, this is an
259 /// identity function. For types that must be expanded (i.e. integer types
260 /// that are larger than the largest integer register or illegal floating
261 /// point types), this returns the largest legal type it will be expanded to.
262 MVT getTypeToExpandTo(MVT VT) const {
263 assert(!VT.isVector());
265 switch (getTypeAction(VT)) {
269 VT = getTypeToTransformTo(VT);
272 assert(false && "Type is not legal nor is it to be expanded!");
279 /// getVectorTypeBreakdown - Vector types are broken down into some number of
280 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
281 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
282 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
284 /// This method returns the number of registers needed, and the VT for each
285 /// register. It also returns the VT and quantity of the intermediate values
286 /// before they are promoted/expanded.
288 unsigned getVectorTypeBreakdown(MVT VT,
290 unsigned &NumIntermediates,
291 MVT &RegisterVT) const;
293 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
294 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
295 /// this is the case, it returns true and store the intrinsic
296 /// information into the IntrinsicInfo that was passed to the function.
297 typedef struct IntrinsicInfo {
298 unsigned opc; // target opcode
299 MVT memVT; // memory VT
300 const Value* ptrVal; // value representing memory location
301 int offset; // offset off of ptrVal
302 unsigned align; // alignment
303 bool vol; // is volatile?
304 bool readMem; // reads memory?
305 bool writeMem; // writes memory?
308 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
309 CallInst &I, unsigned Intrinsic) {
313 /// getWidenVectorType: given a vector type, returns the type to widen to
314 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
315 /// If there is no vector type that we want to widen to, returns MVT::Other
316 /// When and were to widen is target dependent based on the cost of
317 /// scalarizing vs using the wider vector type.
318 virtual MVT getWidenVectorType(MVT VT) const;
320 typedef std::vector<APFloat>::const_iterator legal_fpimm_iterator;
321 legal_fpimm_iterator legal_fpimm_begin() const {
322 return LegalFPImmediates.begin();
324 legal_fpimm_iterator legal_fpimm_end() const {
325 return LegalFPImmediates.end();
328 /// isShuffleMaskLegal - Targets can use this to indicate that they only
329 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
330 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
331 /// are assumed to be legal.
332 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
337 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
338 /// used by Targets can use this to indicate if there is a suitable
339 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
341 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
346 /// getOperationAction - Return how this operation should be treated: either
347 /// it is legal, needs to be promoted to a larger size, needs to be
348 /// expanded to some other code sequence, or the target has a custom expander
350 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
351 if (VT.isExtended()) return Expand;
352 assert(Op < array_lengthof(OpActions) &&
353 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
354 "Table isn't big enough!");
355 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
358 /// isOperationLegalOrCustom - Return true if the specified operation is
359 /// legal on this target or can be made legal with custom lowering. This
360 /// is used to help guide high-level lowering decisions.
361 bool isOperationLegalOrCustom(unsigned Op, MVT VT) const {
362 return (VT == MVT::Other || isTypeLegal(VT)) &&
363 (getOperationAction(Op, VT) == Legal ||
364 getOperationAction(Op, VT) == Custom);
367 /// isOperationLegal - Return true if the specified operation is legal on this
369 bool isOperationLegal(unsigned Op, MVT VT) const {
370 return (VT == MVT::Other || isTypeLegal(VT)) &&
371 getOperationAction(Op, VT) == Legal;
374 /// getLoadExtAction - Return how this load with extension should be treated:
375 /// either it is legal, needs to be promoted to a larger size, needs to be
376 /// expanded to some other code sequence, or the target has a custom expander
378 LegalizeAction getLoadExtAction(unsigned LType, MVT VT) const {
379 assert(LType < array_lengthof(LoadExtActions) &&
380 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
381 "Table isn't big enough!");
382 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
385 /// isLoadExtLegal - Return true if the specified load with extension is legal
387 bool isLoadExtLegal(unsigned LType, MVT VT) const {
388 return VT.isSimple() &&
389 (getLoadExtAction(LType, VT) == Legal ||
390 getLoadExtAction(LType, VT) == Custom);
393 /// getTruncStoreAction - Return how this store with truncation should be
394 /// treated: either it is legal, needs to be promoted to a larger size, needs
395 /// to be expanded to some other code sequence, or the target has a custom
397 LegalizeAction getTruncStoreAction(MVT ValVT,
399 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
400 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
401 "Table isn't big enough!");
402 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
403 (2*MemVT.getSimpleVT())) & 3);
406 /// isTruncStoreLegal - Return true if the specified store with truncation is
407 /// legal on this target.
408 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
409 return isTypeLegal(ValVT) && MemVT.isSimple() &&
410 (getTruncStoreAction(ValVT, MemVT) == Legal ||
411 getTruncStoreAction(ValVT, MemVT) == Custom);
414 /// getIndexedLoadAction - Return how the indexed load should be treated:
415 /// either it is legal, needs to be promoted to a larger size, needs to be
416 /// expanded to some other code sequence, or the target has a custom expander
419 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
420 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
421 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
422 "Table isn't big enough!");
423 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
424 (2*VT.getSimpleVT())) & 3);
427 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
429 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
430 return VT.isSimple() &&
431 (getIndexedLoadAction(IdxMode, VT) == Legal ||
432 getIndexedLoadAction(IdxMode, VT) == Custom);
435 /// getIndexedStoreAction - Return how the indexed store should be treated:
436 /// either it is legal, needs to be promoted to a larger size, needs to be
437 /// expanded to some other code sequence, or the target has a custom expander
440 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
441 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
442 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
443 "Table isn't big enough!");
444 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
445 (2*VT.getSimpleVT())) & 3);
448 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
450 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
451 return VT.isSimple() &&
452 (getIndexedStoreAction(IdxMode, VT) == Legal ||
453 getIndexedStoreAction(IdxMode, VT) == Custom);
456 /// getConvertAction - Return how the conversion should be treated:
457 /// either it is legal, needs to be promoted to a larger size, needs to be
458 /// expanded to some other code sequence, or the target has a custom expander
461 getConvertAction(MVT FromVT, MVT ToVT) const {
462 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
463 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
464 "Table isn't big enough!");
465 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
466 (2*ToVT.getSimpleVT())) & 3);
469 /// isConvertLegal - Return true if the specified conversion is legal
471 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
472 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
473 (getConvertAction(FromVT, ToVT) == Legal ||
474 getConvertAction(FromVT, ToVT) == Custom);
477 /// getCondCodeAction - Return how the condition code should be treated:
478 /// either it is legal, needs to be expanded to some other code sequence,
479 /// or the target has a custom expander for it.
481 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
482 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
483 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
484 "Table isn't big enough!");
485 LegalizeAction Action = (LegalizeAction)
486 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
487 assert(Action != Promote && "Can't promote condition code!");
491 /// isCondCodeLegal - Return true if the specified condition code is legal
493 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
494 return getCondCodeAction(CC, VT) == Legal ||
495 getCondCodeAction(CC, VT) == Custom;
499 /// getTypeToPromoteTo - If the action for this operation is to promote, this
500 /// method returns the ValueType to promote to.
501 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
502 assert(getOperationAction(Op, VT) == Promote &&
503 "This operation isn't promoted!");
505 // See if this has an explicit type specified.
506 std::map<std::pair<unsigned, MVT::SimpleValueType>,
507 MVT::SimpleValueType>::const_iterator PTTI =
508 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
509 if (PTTI != PromoteToType.end()) return PTTI->second;
511 assert((VT.isInteger() || VT.isFloatingPoint()) &&
512 "Cannot autopromote this type, add it with AddPromotedToType.");
516 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
517 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
518 "Didn't find type to promote to!");
519 } while (!isTypeLegal(NVT) ||
520 getOperationAction(Op, NVT) == Promote);
524 /// getValueType - Return the MVT corresponding to this LLVM type.
525 /// This is fixed by the LLVM operations except for the pointer size. If
526 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
527 /// counterpart (e.g. structs), otherwise it will assert.
528 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
529 MVT VT = MVT::getMVT(Ty, AllowUnknown);
530 return VT == MVT::iPTR ? PointerTy : VT;
533 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
534 /// function arguments in the caller parameter area. This is the actual
535 /// alignment, not its logarithm.
536 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
538 /// getRegisterType - Return the type of registers that this ValueType will
539 /// eventually require.
540 MVT getRegisterType(MVT VT) const {
542 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
543 return RegisterTypeForVT[VT.getSimpleVT()];
547 unsigned NumIntermediates;
548 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
551 if (VT.isInteger()) {
552 return getRegisterType(getTypeToTransformTo(VT));
554 assert(0 && "Unsupported extended type!");
555 return MVT(); // Not reached
558 /// getNumRegisters - Return the number of registers that this ValueType will
559 /// eventually require. This is one for any types promoted to live in larger
560 /// registers, but may be more than one for types (like i64) that are split
561 /// into pieces. For types like i140, which are first promoted then expanded,
562 /// it is the number of registers needed to hold all the bits of the original
563 /// type. For an i140 on a 32 bit machine this means 5 registers.
564 unsigned getNumRegisters(MVT VT) const {
566 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
567 return NumRegistersForVT[VT.getSimpleVT()];
571 unsigned NumIntermediates;
572 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
574 if (VT.isInteger()) {
575 unsigned BitWidth = VT.getSizeInBits();
576 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
577 return (BitWidth + RegWidth - 1) / RegWidth;
579 assert(0 && "Unsupported extended type!");
580 return 0; // Not reached
583 /// ShouldShrinkFPConstant - If true, then instruction selection should
584 /// seek to shrink the FP constant of the specified type to a smaller type
585 /// in order to save space and / or reduce runtime.
586 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
588 /// hasTargetDAGCombine - If true, the target has custom DAG combine
589 /// transformations that it can perform for the specified node.
590 bool hasTargetDAGCombine(ISD::NodeType NT) const {
591 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
592 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
595 /// This function returns the maximum number of store operations permitted
596 /// to replace a call to llvm.memset. The value is set by the target at the
597 /// performance threshold for such a replacement.
598 /// @brief Get maximum # of store operations permitted for llvm.memset
599 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
601 /// This function returns the maximum number of store operations permitted
602 /// to replace a call to llvm.memcpy. The value is set by the target at the
603 /// performance threshold for such a replacement.
604 /// @brief Get maximum # of store operations permitted for llvm.memcpy
605 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
607 /// This function returns the maximum number of store operations permitted
608 /// to replace a call to llvm.memmove. The value is set by the target at the
609 /// performance threshold for such a replacement.
610 /// @brief Get maximum # of store operations permitted for llvm.memmove
611 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
613 /// This function returns true if the target allows unaligned memory accesses.
614 /// This is used, for example, in situations where an array copy/move/set is
615 /// converted to a sequence of store operations. It's use helps to ensure that
616 /// such replacements don't generate code that causes an alignment error
617 /// (trap) on the target machine.
618 /// @brief Determine if the target supports unaligned memory accesses.
619 bool allowsUnalignedMemoryAccesses() const {
620 return allowUnalignedMemoryAccesses;
623 /// getOptimalMemOpType - Returns the target specific optimal type for load
624 /// and store operations as a result of memset, memcpy, and memmove lowering.
625 /// It returns MVT::iAny if SelectionDAG should be responsible for
627 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
628 bool isSrcConst, bool isSrcStr) const {
632 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
633 /// to implement llvm.setjmp.
634 bool usesUnderscoreSetJmp() const {
635 return UseUnderscoreSetJmp;
638 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
639 /// to implement llvm.longjmp.
640 bool usesUnderscoreLongJmp() const {
641 return UseUnderscoreLongJmp;
644 /// getStackPointerRegisterToSaveRestore - If a physical register, this
645 /// specifies the register that llvm.savestack/llvm.restorestack should save
647 unsigned getStackPointerRegisterToSaveRestore() const {
648 return StackPointerRegisterToSaveRestore;
651 /// getExceptionAddressRegister - If a physical register, this returns
652 /// the register that receives the exception address on entry to a landing
654 unsigned getExceptionAddressRegister() const {
655 return ExceptionPointerRegister;
658 /// getExceptionSelectorRegister - If a physical register, this returns
659 /// the register that receives the exception typeid on entry to a landing
661 unsigned getExceptionSelectorRegister() const {
662 return ExceptionSelectorRegister;
665 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
666 /// set, the default is 200)
667 unsigned getJumpBufSize() const {
671 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
672 /// (if never set, the default is 0)
673 unsigned getJumpBufAlignment() const {
674 return JumpBufAlignment;
677 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
678 /// limit. Any block whose size is greater should not be predicated.
679 unsigned getIfCvtBlockSizeLimit() const {
680 return IfCvtBlockSizeLimit;
683 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
684 /// block to be considered for duplication. Any block whose size is greater
685 /// should not be duplicated to facilitate its predication.
686 unsigned getIfCvtDupBlockSizeLimit() const {
687 return IfCvtDupBlockSizeLimit;
690 /// getPrefLoopAlignment - return the preferred loop alignment.
692 unsigned getPrefLoopAlignment() const {
693 return PrefLoopAlignment;
696 /// getPreIndexedAddressParts - returns true by value, base pointer and
697 /// offset pointer and addressing mode by reference if the node's address
698 /// can be legally represented as pre-indexed load / store address.
699 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
701 ISD::MemIndexedMode &AM,
702 SelectionDAG &DAG) const {
706 /// getPostIndexedAddressParts - returns true by value, base pointer and
707 /// offset pointer and addressing mode by reference if this node can be
708 /// combined with a load / store to form a post-indexed load / store.
709 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
710 SDValue &Base, SDValue &Offset,
711 ISD::MemIndexedMode &AM,
712 SelectionDAG &DAG) const {
716 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
718 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
719 SelectionDAG &DAG) const;
721 /// isOffsetFoldingLegal - Return true if folding a constant offset
722 /// with the given GlobalAddress is legal. It is frequently not legal in
723 /// PIC relocation models.
724 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
726 //===--------------------------------------------------------------------===//
727 // TargetLowering Optimization Methods
730 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
731 /// SDValues for returning information from TargetLowering to its clients
732 /// that want to combine
733 struct TargetLoweringOpt {
738 explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
740 bool CombineTo(SDValue O, SDValue N) {
746 /// ShrinkDemandedConstant - Check to see if the specified operand of the
747 /// specified instruction is a constant integer. If so, check to see if
748 /// there are any bits set in the constant that are not demanded. If so,
749 /// shrink the constant and return true.
750 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
752 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
753 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
754 /// cast, but it could be generalized for targets with other types of
755 /// implicit widening casts.
756 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
760 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
761 /// DemandedMask bits of the result of Op are ever used downstream. If we can
762 /// use this information to simplify Op, create a new simplified DAG node and
763 /// return true, returning the original and new nodes in Old and New.
764 /// Otherwise, analyze the expression and return a mask of KnownOne and
765 /// KnownZero bits for the expression (used to simplify the caller).
766 /// The KnownZero/One bits may only be accurate for those bits in the
768 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
769 APInt &KnownZero, APInt &KnownOne,
770 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
772 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
773 /// Mask are known to be either zero or one and return them in the
774 /// KnownZero/KnownOne bitsets.
775 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
779 const SelectionDAG &DAG,
780 unsigned Depth = 0) const;
782 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
783 /// targets that want to expose additional information about sign bits to the
785 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
786 unsigned Depth = 0) const;
788 struct DAGCombinerInfo {
789 void *DC; // The DAG Combiner object.
791 bool CalledByLegalizer;
795 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool cl, void *dc)
796 : DC(dc), BeforeLegalize(bl), CalledByLegalizer(cl), DAG(dag) {}
798 bool isBeforeLegalize() const { return BeforeLegalize; }
799 bool isCalledByLegalizer() const { return CalledByLegalizer; }
801 void AddToWorklist(SDNode *N);
802 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
804 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
805 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
807 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
810 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
811 /// and cc. If it is unable to simplify it, return a null SDValue.
812 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
813 ISD::CondCode Cond, bool foldBooleans,
814 DAGCombinerInfo &DCI, DebugLoc dl) const;
816 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
817 /// node is a GlobalAddress + offset.
819 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
821 /// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
822 /// loading 'Bytes' bytes from a location that is 'Dist' units away from the
823 /// location that the 'Base' load is loading from.
824 bool isConsecutiveLoad(SDNode *LD, SDNode *Base, unsigned Bytes, int Dist,
825 const MachineFrameInfo *MFI) const;
827 /// PerformDAGCombine - This method will be invoked for all target nodes and
828 /// for any target-independent nodes that the target has registered with
831 /// The semantics are as follows:
833 /// SDValue.Val == 0 - No change was made
834 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
835 /// otherwise - N should be replaced by the returned Operand.
837 /// In addition, methods provided by DAGCombinerInfo may be used to perform
838 /// more complex transformations.
840 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
842 //===--------------------------------------------------------------------===//
843 // TargetLowering Configuration Methods - These methods should be invoked by
844 // the derived class constructor to configure this object for the target.
848 /// setUsesGlobalOffsetTable - Specify that this target does or doesn't use a
849 /// GOT for PC-relative code.
850 void setUsesGlobalOffsetTable(bool V) { UsesGlobalOffsetTable = V; }
852 /// setShiftAmountType - Describe the type that should be used for shift
853 /// amounts. This type defaults to the pointer type.
854 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
856 /// setBooleanContents - Specify how the target extends the result of a
857 /// boolean value from i1 to a wider type. See getBooleanContents.
858 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
860 /// setSchedulingPreference - Specify the target scheduling preference.
861 void setSchedulingPreference(SchedPreference Pref) {
862 SchedPreferenceInfo = Pref;
865 /// setShiftAmountFlavor - Describe how the target handles out of range shift
867 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
868 ShiftAmtHandling = OORSA;
871 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
872 /// use _setjmp to implement llvm.setjmp or the non _ version.
873 /// Defaults to false.
874 void setUseUnderscoreSetJmp(bool Val) {
875 UseUnderscoreSetJmp = Val;
878 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
879 /// use _longjmp to implement llvm.longjmp or the non _ version.
880 /// Defaults to false.
881 void setUseUnderscoreLongJmp(bool Val) {
882 UseUnderscoreLongJmp = Val;
885 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
886 /// specifies the register that llvm.savestack/llvm.restorestack should save
888 void setStackPointerRegisterToSaveRestore(unsigned R) {
889 StackPointerRegisterToSaveRestore = R;
892 /// setExceptionPointerRegister - If set to a physical register, this sets
893 /// the register that receives the exception address on entry to a landing
895 void setExceptionPointerRegister(unsigned R) {
896 ExceptionPointerRegister = R;
899 /// setExceptionSelectorRegister - If set to a physical register, this sets
900 /// the register that receives the exception typeid on entry to a landing
902 void setExceptionSelectorRegister(unsigned R) {
903 ExceptionSelectorRegister = R;
906 /// SelectIsExpensive - Tells the code generator not to expand operations
907 /// into sequences that use the select operations if possible.
908 void setSelectIsExpensive() { SelectIsExpensive = true; }
910 /// setIntDivIsCheap - Tells the code generator that integer divide is
911 /// expensive, and if possible, should be replaced by an alternate sequence
912 /// of instructions not containing an integer divide.
913 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
915 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
916 /// srl/add/sra for a signed divide by power of two, and let the target handle
918 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
920 /// addRegisterClass - Add the specified register class as an available
921 /// regclass for the specified value type. This indicates the selector can
922 /// handle values of that class natively.
923 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
924 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
925 AvailableRegClasses.push_back(std::make_pair(VT, RC));
926 RegClassForVT[VT.getSimpleVT()] = RC;
929 /// computeRegisterProperties - Once all of the register classes are added,
930 /// this allows us to compute derived properties we expose.
931 void computeRegisterProperties();
933 /// setOperationAction - Indicate that the specified operation does not work
934 /// with the specified type and indicate what to do about it.
935 void setOperationAction(unsigned Op, MVT VT,
936 LegalizeAction Action) {
937 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
938 Op < array_lengthof(OpActions) && "Table isn't big enough!");
939 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
940 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
943 /// setLoadExtAction - Indicate that the specified load with extension does
944 /// not work with the with specified type and indicate what to do about it.
945 void setLoadExtAction(unsigned ExtType, MVT VT,
946 LegalizeAction Action) {
947 assert((unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
948 ExtType < array_lengthof(LoadExtActions) &&
949 "Table isn't big enough!");
950 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
951 LoadExtActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
954 /// setTruncStoreAction - Indicate that the specified truncating store does
955 /// not work with the with specified type and indicate what to do about it.
956 void setTruncStoreAction(MVT ValVT, MVT MemVT,
957 LegalizeAction Action) {
958 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
959 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
960 "Table isn't big enough!");
961 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
962 MemVT.getSimpleVT()*2);
963 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
964 MemVT.getSimpleVT()*2;
967 /// setIndexedLoadAction - Indicate that the specified indexed load does or
968 /// does not work with the with specified type and indicate what to do abort
969 /// it. NOTE: All indexed mode loads are initialized to Expand in
970 /// TargetLowering.cpp
971 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
972 LegalizeAction Action) {
973 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
974 IdxMode < array_lengthof(IndexedModeActions[0]) &&
975 "Table isn't big enough!");
976 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
977 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
980 /// setIndexedStoreAction - Indicate that the specified indexed store does or
981 /// does not work with the with specified type and indicate what to do about
982 /// it. NOTE: All indexed mode stores are initialized to Expand in
983 /// TargetLowering.cpp
984 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
985 LegalizeAction Action) {
986 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
987 IdxMode < array_lengthof(IndexedModeActions[1]) &&
988 "Table isn't big enough!");
989 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
990 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
993 /// setConvertAction - Indicate that the specified conversion does or does
994 /// not work with the with specified type and indicate what to do about it.
995 void setConvertAction(MVT FromVT, MVT ToVT,
996 LegalizeAction Action) {
997 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
998 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
999 "Table isn't big enough!");
1000 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
1001 ToVT.getSimpleVT()*2);
1002 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
1003 ToVT.getSimpleVT()*2;
1006 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1007 /// supported on the target and indicate what to do about it.
1008 void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action) {
1009 assert((unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
1010 (unsigned)CC < array_lengthof(CondCodeActions) &&
1011 "Table isn't big enough!");
1012 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
1013 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.getSimpleVT()*2;
1016 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1017 /// promotion code defaults to trying a larger integer/fp until it can find
1018 /// one that works. If that default is insufficient, this method can be used
1019 /// by the target to override the default.
1020 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1021 PromoteToType[std::make_pair(Opc, OrigVT.getSimpleVT())] =
1022 DestVT.getSimpleVT();
1025 /// addLegalFPImmediate - Indicate that this target can instruction select
1026 /// the specified FP immediate natively.
1027 void addLegalFPImmediate(const APFloat& Imm) {
1028 LegalFPImmediates.push_back(Imm);
1031 /// setTargetDAGCombine - Targets should invoke this method for each target
1032 /// independent node that they want to provide a custom DAG combiner for by
1033 /// implementing the PerformDAGCombine virtual method.
1034 void setTargetDAGCombine(ISD::NodeType NT) {
1035 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1036 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1039 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1040 /// bytes); default is 200
1041 void setJumpBufSize(unsigned Size) {
1045 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1046 /// alignment (in bytes); default is 0
1047 void setJumpBufAlignment(unsigned Align) {
1048 JumpBufAlignment = Align;
1051 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1052 /// limit (in number of instructions); default is 2.
1053 void setIfCvtBlockSizeLimit(unsigned Limit) {
1054 IfCvtBlockSizeLimit = Limit;
1057 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1058 /// of instructions) to be considered for code duplication during
1059 /// if-conversion; default is 2.
1060 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1061 IfCvtDupBlockSizeLimit = Limit;
1064 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1065 /// alignment is zero, it means the target does not care about loop alignment.
1066 void setPrefLoopAlignment(unsigned Align) {
1067 PrefLoopAlignment = Align;
1072 virtual const TargetSubtarget *getSubtarget() {
1073 assert(0 && "Not Implemented");
1074 return NULL; // this is here to silence compiler errors
1076 //===--------------------------------------------------------------------===//
1077 // Lowering methods - These methods must be implemented by targets so that
1078 // the SelectionDAGLowering code knows how to lower these.
1081 /// LowerArguments - This hook must be implemented to indicate how we should
1082 /// lower the arguments for the specified function, into the specified DAG.
1084 LowerArguments(Function &F, SelectionDAG &DAG,
1085 SmallVectorImpl<SDValue>& ArgValues, DebugLoc dl);
1087 /// LowerCallTo - This hook lowers an abstract call to a function into an
1088 /// actual call. This returns a pair of operands. The first element is the
1089 /// return value for the function (if RetTy is not VoidTy). The second
1090 /// element is the outgoing token chain.
1091 struct ArgListEntry {
1102 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1103 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1105 typedef std::vector<ArgListEntry> ArgListTy;
1106 virtual std::pair<SDValue, SDValue>
1107 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1108 bool isVarArg, bool isInreg, unsigned CallingConv,
1109 bool isTailCall, SDValue Callee, ArgListTy &Args,
1110 SelectionDAG &DAG, DebugLoc dl);
1112 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1113 /// memcpy. This can be used by targets to provide code sequences for cases
1114 /// that don't fit the target's parameters for simple loads/stores and can be
1115 /// more efficient than using a library call. This function can return a null
1116 /// SDValue if the target declines to use custom code and a different
1117 /// lowering strategy should be used.
1119 /// If AlwaysInline is true, the size is constant and the target should not
1120 /// emit any calls and is strongly encouraged to attempt to emit inline code
1121 /// even if it is beyond the usual threshold because this intrinsic is being
1122 /// expanded in a place where calls are not feasible (e.g. within the prologue
1123 /// for another call). If the target chooses to decline an AlwaysInline
1124 /// request here, legalize will resort to using simple loads and stores.
1126 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1128 SDValue Op1, SDValue Op2,
1129 SDValue Op3, unsigned Align,
1131 const Value *DstSV, uint64_t DstOff,
1132 const Value *SrcSV, uint64_t SrcOff) {
1136 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1137 /// memmove. This can be used by targets to provide code sequences for cases
1138 /// that don't fit the target's parameters for simple loads/stores and can be
1139 /// more efficient than using a library call. This function can return a null
1140 /// SDValue if the target declines to use custom code and a different
1141 /// lowering strategy should be used.
1143 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1145 SDValue Op1, SDValue Op2,
1146 SDValue Op3, unsigned Align,
1147 const Value *DstSV, uint64_t DstOff,
1148 const Value *SrcSV, uint64_t SrcOff) {
1152 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1153 /// memset. This can be used by targets to provide code sequences for cases
1154 /// that don't fit the target's parameters for simple stores and can be more
1155 /// efficient than using a library call. This function can return a null
1156 /// SDValue if the target declines to use custom code and a different
1157 /// lowering strategy should be used.
1159 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1161 SDValue Op1, SDValue Op2,
1162 SDValue Op3, unsigned Align,
1163 const Value *DstSV, uint64_t DstOff) {
1167 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1168 /// to legalize nodes with an illegal operand type but legal result types.
1169 /// It replaces the LowerOperation callback in the type Legalizer.
1170 /// The reason we can not do away with LowerOperation entirely is that
1171 /// LegalizeDAG isn't yet ready to use this callback.
1172 /// TODO: Consider merging with ReplaceNodeResults.
1174 /// The target places new result values for the node in Results (their number
1175 /// and types must exactly match those of the original return values of
1176 /// the node), or leaves Results empty, which indicates that the node is not
1177 /// to be custom lowered after all.
1178 /// The default implementation calls LowerOperation.
1179 virtual void LowerOperationWrapper(SDNode *N,
1180 SmallVectorImpl<SDValue> &Results,
1183 /// LowerOperation - This callback is invoked for operations that are
1184 /// unsupported by the target, which are registered to use 'custom' lowering,
1185 /// and whose defined values are all legal.
1186 /// If the target has no operations that require custom lowering, it need not
1187 /// implement this. The default implementation of this aborts.
1188 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1190 /// ReplaceNodeResults - This callback is invoked when a node result type is
1191 /// illegal for the target, and the operation was registered to use 'custom'
1192 /// lowering for that result type. The target places new result values for
1193 /// the node in Results (their number and types must exactly match those of
1194 /// the original return values of the node), or leaves Results empty, which
1195 /// indicates that the node is not to be custom lowered after all.
1197 /// If the target has no operations that require custom lowering, it need not
1198 /// implement this. The default implementation aborts.
1199 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1200 SelectionDAG &DAG) {
1201 assert(0 && "ReplaceNodeResults not implemented for this target!");
1204 /// IsEligibleForTailCallOptimization - Check whether the call is eligible for
1205 /// tail call optimization. Targets which want to do tail call optimization
1206 /// should override this function.
1207 virtual bool IsEligibleForTailCallOptimization(CallSDNode *Call,
1209 SelectionDAG &DAG) const {
1213 /// CheckTailCallReturnConstraints - Check whether CALL node immediatly
1214 /// preceeds the RET node and whether the return uses the result of the node
1215 /// or is a void return. This function can be used by the target to determine
1216 /// eligiblity of tail call optimization.
1217 static bool CheckTailCallReturnConstraints(CallSDNode *TheCall, SDValue Ret);
1219 /// GetPossiblePreceedingTailCall - Get preceeding TailCallNodeOpCode node if
1220 /// it exists. Skip a possible ISD::TokenFactor.
1221 static SDValue GetPossiblePreceedingTailCall(SDValue Chain,
1222 unsigned TailCallNodeOpCode) {
1223 if (Chain.getOpcode() == TailCallNodeOpCode) {
1225 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1226 if (Chain.getNumOperands() &&
1227 Chain.getOperand(0).getOpcode() == TailCallNodeOpCode)
1228 return Chain.getOperand(0);
1233 /// getTargetNodeName() - This method returns the name of a target specific
1235 virtual const char *getTargetNodeName(unsigned Opcode) const;
1237 /// createFastISel - This method returns a target specific FastISel object,
1238 /// or null if the target does not support "fast" ISel.
1240 createFastISel(MachineFunction &,
1241 MachineModuleInfo *, DwarfWriter *,
1242 DenseMap<const Value *, unsigned> &,
1243 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1244 DenseMap<const AllocaInst *, int> &
1246 , SmallSet<Instruction*, 8> &CatchInfoLost
1252 //===--------------------------------------------------------------------===//
1253 // Inline Asm Support hooks
1256 enum ConstraintType {
1257 C_Register, // Constraint represents specific register(s).
1258 C_RegisterClass, // Constraint represents any of register(s) in class.
1259 C_Memory, // Memory constraint.
1260 C_Other, // Something else.
1261 C_Unknown // Unsupported constraint.
1264 /// AsmOperandInfo - This contains information for each constraint that we are
1266 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1267 /// ConstraintCode - This contains the actual string for the code, like "m".
1268 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1269 /// most closely matches the operand.
1270 std::string ConstraintCode;
1272 /// ConstraintType - Information about the constraint code, e.g. Register,
1273 /// RegisterClass, Memory, Other, Unknown.
1274 TargetLowering::ConstraintType ConstraintType;
1276 /// CallOperandval - If this is the result output operand or a
1277 /// clobber, this is null, otherwise it is the incoming operand to the
1278 /// CallInst. This gets modified as the asm is processed.
1279 Value *CallOperandVal;
1281 /// ConstraintVT - The ValueType for the operand value.
1284 /// isMatchingInputConstraint - Return true of this is an input operand that
1285 /// is a matching constraint like "4".
1286 bool isMatchingInputConstraint() const;
1288 /// getMatchedOperand - If this is an input matching constraint, this method
1289 /// returns the output operand it matches.
1290 unsigned getMatchedOperand() const;
1292 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1293 : InlineAsm::ConstraintInfo(info),
1294 ConstraintType(TargetLowering::C_Unknown),
1295 CallOperandVal(0), ConstraintVT(MVT::Other) {
1299 /// ComputeConstraintToUse - Determines the constraint code and constraint
1300 /// type to use for the specific AsmOperandInfo, setting
1301 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1302 /// being passed in is available, it can be passed in as Op, otherwise an
1303 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1304 /// constraint of the inline asm instruction being processed is 'm'.
1305 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1308 SelectionDAG *DAG = 0) const;
1310 /// getConstraintType - Given a constraint, return the type of constraint it
1311 /// is for this target.
1312 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1314 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1315 /// return a list of registers that can be used to satisfy the constraint.
1316 /// This should only be used for C_RegisterClass constraints.
1317 virtual std::vector<unsigned>
1318 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1321 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1322 /// {edx}), return the register number and the register class for the
1325 /// Given a register class constraint, like 'r', if this corresponds directly
1326 /// to an LLVM register class, return a register of 0 and the register class
1329 /// This should only be used for C_Register constraints. On error,
1330 /// this returns a register number of 0 and a null register class pointer..
1331 virtual std::pair<unsigned, const TargetRegisterClass*>
1332 getRegForInlineAsmConstraint(const std::string &Constraint,
1335 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1336 /// with another that has more specific requirements based on the type of the
1337 /// corresponding operand. This returns null if there is no replacement to
1339 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
1341 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1342 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1343 /// it means one of the asm constraint of the inline asm instruction being
1344 /// processed is 'm'.
1345 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1347 std::vector<SDValue> &Ops,
1348 SelectionDAG &DAG) const;
1350 //===--------------------------------------------------------------------===//
1354 // EmitInstrWithCustomInserter - This method should be implemented by targets
1355 // that mark instructions with the 'usesCustomDAGSchedInserter' flag. These
1356 // instructions are special in various ways, which require special support to
1357 // insert. The specified MachineInstr is created but not inserted into any
1358 // basic blocks, and the scheduler passes ownership of it to this method.
1359 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1360 MachineBasicBlock *MBB) const;
1362 //===--------------------------------------------------------------------===//
1363 // Addressing mode description hooks (used by LSR etc).
1366 /// AddrMode - This represents an addressing mode of:
1367 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1368 /// If BaseGV is null, there is no BaseGV.
1369 /// If BaseOffs is zero, there is no base offset.
1370 /// If HasBaseReg is false, there is no base register.
1371 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1375 GlobalValue *BaseGV;
1379 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1382 /// isLegalAddressingMode - Return true if the addressing mode represented by
1383 /// AM is legal for this target, for a load/store of the specified type.
1384 /// The type may be VoidTy, in which case only return true if the addressing
1385 /// mode is legal for a load/store of any legal type.
1386 /// TODO: Handle pre/postinc as well.
1387 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1389 /// isTruncateFree - Return true if it's free to truncate a value of
1390 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1391 /// register EAX to i16 by referencing its sub-register AX.
1392 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1396 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
1400 /// isZExtFree - Return true if any actual instruction that defines a
1401 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
1402 /// register. This does not necessarily include registers defined in
1403 /// unknown ways, such as incoming arguments, or copies from unknown
1404 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1405 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1406 /// all instructions that define 32-bit values implicit zero-extend the
1407 /// result out to 64 bits.
1408 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1412 virtual bool isZExtFree(MVT VT1, MVT VT2) const {
1416 //===--------------------------------------------------------------------===//
1417 // Div utility functions
1419 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1420 std::vector<SDNode*>* Created) const;
1421 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1422 std::vector<SDNode*>* Created) const;
1425 //===--------------------------------------------------------------------===//
1426 // Runtime Library hooks
1429 /// setLibcallName - Rename the default libcall routine name for the specified
1431 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1432 LibcallRoutineNames[Call] = Name;
1435 /// getLibcallName - Get the libcall routine name for the specified libcall.
1437 const char *getLibcallName(RTLIB::Libcall Call) const {
1438 return LibcallRoutineNames[Call];
1441 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1442 /// result of the comparison libcall against zero.
1443 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1444 CmpLibcallCCs[Call] = CC;
1447 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1448 /// the comparison libcall against zero.
1449 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1450 return CmpLibcallCCs[Call];
1455 const TargetData *TD;
1457 /// PointerTy - The type to use for pointers, usually i32 or i64.
1461 /// IsLittleEndian - True if this is a little endian target.
1463 bool IsLittleEndian;
1465 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
1467 bool UsesGlobalOffsetTable;
1469 /// SelectIsExpensive - Tells the code generator not to expand operations
1470 /// into sequences that use the select operations if possible.
1471 bool SelectIsExpensive;
1473 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1474 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1475 /// a real cost model is in place. If we ever optimize for size, this will be
1476 /// set to true unconditionally.
1479 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1480 /// srl/add/sra for a signed divide by power of two, and let the target handle
1482 bool Pow2DivIsCheap;
1484 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1485 /// llvm.setjmp. Defaults to false.
1486 bool UseUnderscoreSetJmp;
1488 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1489 /// llvm.longjmp. Defaults to false.
1490 bool UseUnderscoreLongJmp;
1492 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1496 OutOfRangeShiftAmount ShiftAmtHandling;
1498 /// BooleanContents - Information about the contents of the high-bits in
1499 /// boolean values held in a type wider than i1. See getBooleanContents.
1500 BooleanContent BooleanContents;
1502 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1503 /// total cycles or lowest register usage.
1504 SchedPreference SchedPreferenceInfo;
1506 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1507 unsigned JumpBufSize;
1509 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1511 unsigned JumpBufAlignment;
1513 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1515 unsigned IfCvtBlockSizeLimit;
1517 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1518 /// duplicated during if-conversion.
1519 unsigned IfCvtDupBlockSizeLimit;
1521 /// PrefLoopAlignment - The perferred loop alignment.
1523 unsigned PrefLoopAlignment;
1525 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1526 /// specifies the register that llvm.savestack/llvm.restorestack should save
1528 unsigned StackPointerRegisterToSaveRestore;
1530 /// ExceptionPointerRegister - If set to a physical register, this specifies
1531 /// the register that receives the exception address on entry to a landing
1533 unsigned ExceptionPointerRegister;
1535 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1536 /// the register that receives the exception typeid on entry to a landing
1538 unsigned ExceptionSelectorRegister;
1540 /// RegClassForVT - This indicates the default register class to use for
1541 /// each ValueType the target supports natively.
1542 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1543 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1544 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1546 /// TransformToType - For any value types we are promoting or expanding, this
1547 /// contains the value type that we are changing to. For Expanded types, this
1548 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1549 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1550 /// by the system, this holds the same type (e.g. i32 -> i32).
1551 MVT TransformToType[MVT::LAST_VALUETYPE];
1553 /// OpActions - For each operation and each value type, keep a LegalizeAction
1554 /// that indicates how instruction selection should deal with the operation.
1555 /// Most operations are Legal (aka, supported natively by the target), but
1556 /// operations that are not should be described. Note that operations on
1557 /// non-legal value types are not described here.
1558 uint64_t OpActions[ISD::BUILTIN_OP_END];
1560 /// LoadExtActions - For each load of load extension type and each value type,
1561 /// keep a LegalizeAction that indicates how instruction selection should deal
1563 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1565 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1566 /// indicates how instruction selection should deal with the store.
1567 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1569 /// IndexedModeActions - For each indexed mode and each value type, keep a
1570 /// pair of LegalizeAction that indicates how instruction selection should
1571 /// deal with the load / store.
1572 uint64_t IndexedModeActions[2][ISD::LAST_INDEXED_MODE];
1574 /// ConvertActions - For each conversion from source type to destination type,
1575 /// keep a LegalizeAction that indicates how instruction selection should
1576 /// deal with the conversion.
1577 /// Currently, this is used only for floating->floating conversions
1578 /// (FP_EXTEND and FP_ROUND).
1579 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1581 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1582 /// LegalizeAction that indicates how instruction selection should
1583 /// deal with the condition code.
1584 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1586 ValueTypeActionImpl ValueTypeActions;
1588 std::vector<APFloat> LegalFPImmediates;
1590 std::vector<std::pair<MVT, TargetRegisterClass*> > AvailableRegClasses;
1592 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1593 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1594 /// which sets a bit in this array.
1596 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1598 /// PromoteToType - For operations that must be promoted to a specific type,
1599 /// this holds the destination type. This map should be sparse, so don't hold
1602 /// Targets add entries to this map with AddPromotedToType(..), clients access
1603 /// this with getTypeToPromoteTo(..).
1604 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1607 /// LibcallRoutineNames - Stores the name each libcall.
1609 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1611 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1612 /// of each of the comparison libcall against zero.
1613 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1616 /// When lowering \@llvm.memset this field specifies the maximum number of
1617 /// store operations that may be substituted for the call to memset. Targets
1618 /// must set this value based on the cost threshold for that target. Targets
1619 /// should assume that the memset will be done using as many of the largest
1620 /// store operations first, followed by smaller ones, if necessary, per
1621 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1622 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1623 /// store. This only applies to setting a constant array of a constant size.
1624 /// @brief Specify maximum number of store instructions per memset call.
1625 unsigned maxStoresPerMemset;
1627 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1628 /// store operations that may be substituted for a call to memcpy. Targets
1629 /// must set this value based on the cost threshold for that target. Targets
1630 /// should assume that the memcpy will be done using as many of the largest
1631 /// store operations first, followed by smaller ones, if necessary, per
1632 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1633 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1634 /// and one 1-byte store. This only applies to copying a constant array of
1636 /// @brief Specify maximum bytes of store instructions per memcpy call.
1637 unsigned maxStoresPerMemcpy;
1639 /// When lowering \@llvm.memmove this field specifies the maximum number of
1640 /// store instructions that may be substituted for a call to memmove. Targets
1641 /// must set this value based on the cost threshold for that target. Targets
1642 /// should assume that the memmove will be done using as many of the largest
1643 /// store operations first, followed by smaller ones, if necessary, per
1644 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1645 /// with 8-bit alignment would result in nine 1-byte stores. This only
1646 /// applies to copying a constant array of constant size.
1647 /// @brief Specify maximum bytes of store instructions per memmove call.
1648 unsigned maxStoresPerMemmove;
1650 /// This field specifies whether the target machine permits unaligned memory
1651 /// accesses. This is used, for example, to determine the size of store
1652 /// operations when copying small arrays and other similar tasks.
1653 /// @brief Indicate whether the target permits unaligned memory accesses.
1654 bool allowUnalignedMemoryAccesses;
1656 } // end llvm namespace